Computing and the World

Walid Taha

Rice University

The modern computer

How it is built

C++

Verilog

C

Assembly

FORTRAN

VHDL

A programming language (PL)

• Is the face of computing to the world

• Provides tools for managing complexity

• Is the right place to fix old, tough

bugs

My research

• Create and deploy language features

• Study existing languages

• Study important domains

• Extend existing languages

This talk

Overview of three research projects

• General purpose languages (GPLs)

• Hardware description languages (HDLs)

• Physically safe computing (PSC)

General Purpose Languages

Overview

Much of our work is on GPLs

• Real-time and event driven languages

• Multi-stage programming (MSP)

• Indexed types

Overview

Much of our work is on GPLs

• Real-time and event driven languages

• Multi-stage programming (MSP)

• Indexed types

more about this today

Why MSP?

• Abstractions manage complexity

• Abstractions often have runtime cost

• Programmers avoid runtime cost

• Abstractions don’t get used ...

A single stage computation

OPI1

I2

if I1 = 0 then I2*4else I2*8

A staged computation

OPI1

I2

OI1 P1 P2

I2

if I1 = 0 then I2*4else I2*8

if I1 = 0 then “I2*4”else “I2*8”

Stage separation

OPI1

I2

OI1 P1 P2

I2

if I1 = 0 then I2*4else I2*8

if I1 = 0 then “I2*4”else “I2*8”

“I2*4”

“I2*8”

• Strings are not the best way to do this

• Variable capture (Scheme, CPP, etc)

• Static type checking (8 years, a huge effort!)

ApproachBuild“f

(x,y)”

CombineF X

Syntactic correctnes

s?Reject “f (x,)”

Type correctnes

s?Reject “7

(8)”

String Datatype

The hard part

• Strings are not the best way to do this

• Variable capture (Scheme, CPP, etc)

• Static type checking (8 years, a huge effort!)

The hard part

ApproachBuild“f

(x,y)”

CombineF X

Syntactic correctnes

s?Reject “f (x,)”

Type correctnes

s?Reject “7

(8)”

String Datatype MSP

“Killer apps”

Anywhere generality is needed, but expensive

• Interpreters

• Numerical computation• Gaussian elimination• Dynamic programming• The Fast Fourier Transform (FFT)

• Web page generation

Typical speedup

• Interpreters: 10-100 times

• Others: significant variation

• Real win is often in code quality

Hardware Description Languages

Hardware (HW) design today

• Complexity is soaring. Must manage:• Gate count (area)• Wire delays (speed)• Power consumption• Temperature effects

• Mainstream trend: more automation

Our approach

• Say No to Automation!

• Provide better abstractions

• Provide better static checking

Strengths of this approach

• Engineers know a lot about design

• Design and deploy as extension• “The Verilog Preprocessor”

• Working with domain experts • Jim Grundy and John O’Leary at Intel• Target users are Intel chip designers

The Verilog HW description language

• Developed by HW engineers, based on C

• Two very different “Verilogs”• Structural• Behavioral

• Structural is poor in abstractions & checking

Results

• Verilog is a statically checkable

two-level language• Bus (array) bound checking

• Static gate estimation • Example: adder (N,x,y) : 2N+7

• Tight bound for many circuits

• Static delay estimation

Results

• Verilog is a statically checkable

two-level language• Bus (array) bound checking

• Static gate estimation • Example: adder (N,x,y) : 2N+7

• Tight bound for many circuits

• Static delay estimation

more about this today

Bound checking, Part 1:inconsistencies are

padded

module invert4(x,y); input [3:0] y; output [3:0] x; assign x = ~ y;endmodule

y0y3 y2 y1

x0x3 x2 x1

Bound checking, Part 1:inconsistencies are

padded

module invert4(x,y); input [4:0] y; output [3:0] x; assign x = ~ y;endmodule

y0y3 y2 y1

x0x3 x2 x1

y4

Valid Verilog DescriptionPadding Semantics

Bound checking, Part 2:parameter checks are ad

hoc

module invertn(x,y); parameter N = 4; input [N-1 : 0] y; output [N-1 : 0] x; genvar i; generate for(i = 0 ; i < N ; i = i +

1) not (x[i],y[i]); endgenerateendmodule

y0y3 y2 y1

x0x3 x2 x1

Bound checking, Part 2:parameter checks are ad

hoc

module invertn(x,y); parameter N = 4; input [N-1 : 0] y; output [N-1 : 0] x; genvar i; generate for(i = 0 ; i <= N ; i = i +

1) not (x[i],y[i]); endgenerateendmodule

y0y3 y2 y1

x0x3 x2 x1

Off-by-one detected afterelaboration

NB: Recall buffer overflows...

How VPP works

ExtendedVerilog

VPPYices

(SMT Solver)

Integer Satisfiability Problem

Ill-Typed

Well-Typed

Integer Satisfiability Problem

Integer Satisfiability Problem

SMT Problem

Yes/No

Yes/No

Yes/No

Physically Safe Computing

Motivation

Computers

are permeating

our world... Are we

safe?

Copyright 2007 Hyundai

Copyright 2007 New York Times

Inspiration

“A robot may not injure a human being”

- Asimov’s First Law 1942

for i = 1 to 35 read i ...

011001...

010010...

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Goals

• Accelerate the engineering

process

• Improve virtual testing (Acumen)

• Guarantee physical safety

Goals

• Accelerate the engineering

process

• Improve virtual testing (Acumen)

• Guarantee physical safetymore about this today

Acumen = RIDL + PhyDL

• RIDL specifies controller•The discrete, digital world

• PhyDL specifies environment•The continuous, physical world

Small example

F

F

F

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Small example

Semantics

• RIDL is translated into event handlers

• PhyDL is translated into simulation

codes• Identify state variables• Reduce order (to one)• Vectorize• Simulate (currently, numerically)

More telling examples• Goal: Active bus suspension• U is the control force• How do we design controller?

More telling examples

Closing Words

Computing

• Computing has huge impact on our lives

• Better computing requires better

languages

• Significantly better languages are

possible

The World

• Just describing the real world is

hard

• Tinkering Fun Better products

• The most useful computer is

invisible

Computing is too important to leave to old, broken

languages

Thank you

Credits

Multi-stage Programming

Tim Sheard

Zino Benaissa

Emir Pasalic

Amr Sabry

Steven Ganz

Xavier Leroy

Eugenio Moggi

Stephan Ellner

Michael Florentin

Patricia Johann Roumen

Kaiabachev

Hongwei Xi

Cristiano Calcagno

Ed Pizzi

Kedar Swadi

Hardware Description Languages

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Cherif Salama

Yilong Yao

Jim Grundy

John O’Leary

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Jennifer Gillenwater

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Gregory Malecha

Physically Safe Computing

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Walid Taha

Marcie O’Malley

Corky Cartwright

Albert Cheng

Paul Hudak

Angela Zhu

Jun Inoue

Alex

Stoll

Joshua Langsfeld

Katherin Davis

Kevin Hirshberg

Laura Shepard

Ongoing and future work

• MSP and indexed types in Java (“Mint”)

• Deploying VPP

• Physically Safe Computing

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