1
INTERNATIONAL CONFERENCE ON MANAGEMENT OF INFRASTRUCTURE
(ICMI)(FEBRUARY 14-15, 2014)
Title: A Concept Paper on Comparative Study of FPGA Implemented Adhoc Routing
Algorithms
Abstract: Mobile Ad-hoc network is an infrastructure-less wireless communication in which
links between different nodes are not fixed and changes at every instant of time. Because of this
unpredictable and dynamic nature of Ad-hoc network, we always needed a routing algorithm
which can manage the nodes changing behavior and thus communication can be maintained.
There is always a problem of out of range transmission, hidden terminal and thus inefficient
communication in such type or remote areas. So as to overcome these situations, Ad-hoc network
was introduced and thus developed so far. The comparative survey is carried out for the FPGA
implemented Ad-hoc routing algorithms like DSDV, AODV and TORA and their synthesis
results obtained on the basis of various researches done.
Author’s Details:
1. Ms Pooja Srivastava
Assistant Professor, Department of Electronics, Banasthali University, Rajasthan, India.
Mob No: 08766619354, Email Id: [email protected]
2. Dr. Seema Verma
Associate Professor, Department of Electronics, Banasthali University, Rajasthan, India.
Mob No: 09352878355, Email Id: [email protected]
3. Ms. Priya Singh
Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University,
Rajasthan, India. Mob No: 07727031829, Email Id: [email protected]
4. Ms. Bharti Garg
Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University,
Rajasthan, India. Mob No: 08302711821, Email Id: [email protected]
5. Ms. Ankita Rastogi
Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University,
Rajasthan, India. Mob No: 07740943475, Email Id: [email protected]
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INTERNATIONAL CONFERENCE ON MANAGEMENT OF INFRASTRUCTURE
(ICMI)(FEBRUARY 14-15, 2014)
A Concept Paper on Comparative Study of FPGA Implemented
Adhoc Routing Algorithms
Pooja Srivastava1, Dr. Seema Verma
2 , Priya Singh
3 , Bharti Garg
4, Ankita Rastogi
5
1Assistant Professor, Department of Electronics, Banasthali University, Rajasthan, India
[email protected] 2Associate Professor, Department of Electronics, Banasthali University, Rajasthan, India
[email protected] 3Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University, Rajasthan, India
[email protected] 4Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University, Rajasthan, India
[email protected] 5Student, M.Tech. (VLSI Design), Department of Electronics, Banasthali University, Rajasthan, India
Abstract
Mobile Ad-hoc network is an infrastructure-
less wireless communication in which links
between different nodes are not fixed and
changes at every instant of time. Because of
this unpredictable and dynamic nature of
Ad-hoc network, we always needed a
routing algorithm which can manage the
nodes changing behavior and thus
communication can be maintained. There is
always a problem of out of range
transmission, hidden terminal and thus
inefficient communication in such type or
remote areas. So as to overcome these
situations, Ad-hoc network was introduced
and thus developed so far. The comparative
survey is carried out for the FPGA
implemented Ad-hoc routing algorithms like
DSDV, AODV and TORA and their
synthesis results obtained on the basis of
various researches done.
Keywords
MANETs, Routing protocols, DSDV,
AODV, TORA, VHDL, FPGA
Introduction
Ad-hoc network deals with various issues in
mobile networking such as instant
infrastructure, disaster relief, remote areas
[7],[11]. To overcome these problems,
effective routing protocols are used. We can
broadly divide the routing protocols in two
categories 1) On Demand Routing Protocols
eg: AODV & 2) Table driven Routing
Protocol eg: DSDV.
DSDV (Destination Sequence Distance
Vector) is the proactive table driven routing
protocol for MANET [1],[7]. The data is
transferred from one node to another and
exchange of these data is done using route
discovery and forwarding. Every node
includes destination Ids, metrics, next hop
Ids in its routing table. Each entry in table
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has its own sequence number which is
generated by destination station. This
updation is done continuously for every
table and information is exchanged between
each node. These tables show which station
is in reach and after how many hops. The
table always changes dynamically so it is
important to broadcast the entries to each
mobile node and can identify other mobile
node easily and exchange can be done
easily.
AODV (Ad-hoc On Demand Distance
Vector) includes both unicast and broadcast
routing. It has four types of control packets
RREQ, RERR, HELLO and RREP here first
three are broadcasted and RREP is
unicasted. It sends periodically to get the
newly arrived neighbors, packet is not
flooded or forwarded. When the source
wants to send a data to destination AODV
check the table to find if any active route is
present for the destination or not. If any
active route is found then data is sent to the
next node according to route. If no active
route found then RREQ packet is
broadcasted and time is set. This is repeated
until the RREP is received from the
destination. When this RREP is obtained
then reverse path is checked and forwards
the RREP to the source. If any path is
detected as broken, then AODV check for
all the nodes affected and detects it as
invalid route and thus send RERR packet[2]-
[3].
TORA (Temporally ordered routing) is a
reactive protocol which is highly adaptive
and distributed. It does not contain any loop
and is very fast in routing in highly mobile
network. It works by focusing on routing
problem at the local area where topology
had changed. It is done by letting all nodes
maintaining information of neighbors. Main
functions of router are creating routes,
maintaining routes and erasing routes. This
is done using control packets-query (QRY),
update (UPD) and clear (CLR). Routes are
created using QRY and UPD, routes are
maintained by UPD and cleared using CLR
packet [4],[12].
Most of the routing algorithms are made
using software programming language but
by this it experience high power
consumption and long time of execution. As
we know the life time of every node depends
on battery power so a route deeply depends
on power factor. Therefore energy
constraints have the great impact on
MANET. But by hardware implementation
due to increase in speed of operation power
consumption is reduced. The FPGA
implementation also helps in quick handling
and loading of dynamic data according to
traffic condition [10].
VLSI Architecture of DSDV
The architecture of DSDV protocol has been
depicted in figure 1[5].
Figure1. The implemented architecture of MANET
node
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Data-link In-Buffer stores input control
information transmitted from other nodes
and is received by node in the form of table.
Data-link Out-Buffer stores output control
information that is to be forwarded to
neighboring nodes in tabular format. Route
information memory (RIM) stores the
information required to identify the next hop
address for an optimum route to the
destination that too in tabular format.
DSDV Processor has the separate
architecture depicted in figure 2 containing
control unit, input processor, output
processor, system clock and stale node
processor.
Figure2. Architecture of DSDV processor
Control unit Functions control the three
processes- 1. Table Transmission (periodic
update) 2. Receive Input and 3. Check Input
for Stale Nodes periodically depicted in
figure 3 [17].
Figure3. Sequence of three main functions in DSDV
processor
Input Processor processes the information
provided by Data link in-buffer. Output
Processor analyses the data stored in out-
buffer and RIM, then resulting information
is forwarded to Data link out-buffer. Stale
Node Processor identifies the connectivity
of a node with the route network [13].
VLSI Architecture of AODV
The functional block diagram of AODV has
been depicted in figure 4[8].
Figure4. Functional block diagram of AODV
In this approach a buffer memory is present
to store the incoming message packets and
addressing packets. A cache memory is also
provided to store information for all other
nodes. The incoming information is
compared with the cache memory
information and thus a route is developed
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according to the matching. Message is
transferred by this route and this route is
maintained by periodic transfer of hello
message packets.
VLSI Architecture of TORA
It includes input buffer, output buffer, router
processor, link status memory and neighbor
status memory as depicted in figure 5. The
main part which makes it different from
DSDV is neighbor status and link status
memory. They consist of two dimensional
array which have the information regarding
neighboring nodes and link (route)
information respectively. Two main control
signal used in TORA are read and write
signals. Read signals are used to show the
input buffer that it should now read the input
buffer and preserve the data temporarily.
The write signal is used to inform neighbors
that it is going to transmit the data packet.
This signal is provoked by the processor [9].
Figure5. Architecture of node in TORA
FPGA Implementation
The shown architecture of DSDV, AODV,
TORA were implemented by VHDL
program and simulation was done using
MODEL SIM. Synthesis was done using
Xilinx tools such as Project Navigator and
ECS tool [6], [14] & [15].
1. Simulation and Synthesis Reports of
DSDV
Simulation waveform of DSDV input
processor has been depicted in figure 6 and
output processor has been depicted in
figure7. Figure 8 describes the synthesis
report of DSDV
Figure6. Simulation waveform of input processor [1]
Figure7. Simulation waveform of output
processor [1]
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Figure8. Synthesis report of DSDV [1]
For DSDV, Vertex-E FPGA chip was used
for the MANET node and thus it gives the
synthesis result with following figures:
Minimum input arrival time before clock
(min. set up time): 4.39 ns
Maximum required time after clock (max.
hold time): 6.04 ns
2. Simulation and Synthesis Reports of
AODV
Simulation waveform of AODV has been
depicted in figure 9 and synthesis report has
been described in figure 10.
Figure9. Simulation waveform of AODV [2]
Figure10. Synthesis result of AODV [2]
For AODV device used was 4v1x25st363-
12 and thus fact and figures obtained are:
Number of slices: 5925 out of 10752, 55%
Number of slice flip flops: 3693 out of
21504, 17%
Number of 4 input LUTs: 10776 out of
21504, 50%
Number of bonded IOBs: 81 out of 242,
33%
Number of GCLKs: 2 out of 32, 6%
3. Simulation and Synthesis Reports of
TORA
Simulation waveform of TORA has been
depicted in figure 11 and synthesis result has
been described in figure 12.
Figure11. Simulation waveform of TORA [4]
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Figure12. Synthesis result of TORA [4]
For TORA device used was 2s200eft256-7
and thus fact and figures obtained are:
Number of slices: 1327 out of 2352, 57%
Number of slice flip flops: 394 out of 4704,
8%
Number of 4 input LUTs: 2487 out of 4704,
52%
Number of bonded IOBs: 27 out of 182,
14%
Number of GCLKs: 1 out of 4, 25%
Conclusion
From the results obtained we can conclude that
DSDV have maximum frequency of operation
and minimum period of operation. AODV and
TORA have less call set up time and less
architectural complexity as compared to DSDV.
Table 1: Comparative Study of DSDV,
AODV & TORA Routing Algorithms
Routing
protocol
Max.
frequency
Min.
period
DSDV 115.157
MHz
8.684 ns
AODV 75.069 MHz 13.32 ns
TORA 34.164 MHz 29.27 ns
Future Scope
The proposed architecture of the protocols
provide reduction in call setup time and
quick handling of dynamic topology under
large traffic, thus speed and efficiency is
improved. In future, the optimization
concepts can be introduced. AODV and
TORA also have the advantage of reduced
components and complexity in architectural
development and thus reducing the delay in
handling of dynamic topology. As MANET
have various topology for handling the
traffic such as DSR, DSDV, AODV &
TORA and so on but no single protocol can
handle the complex nature of network
changing traffic and environmental
condition. So for efficient utilization of all
these protocol, we need to work on
reconfigurable protocol which can switch on
the routing algorithm based on the
requirement and condition. This future
advancement can be facilitated by hardware
implementation to upgrade the Ad-hoc
network performance [15].
Acknowledgements
We are highly thankful to our university
Banasthali Vidyapith, from where we had
got the great opportunity for writing a
concept paper. We also obliged to the
faculty of Department of Electronics who
helped us in carrying out this work.
References
[1] M. Ramakrishnan, Dr. S. Shanmugavel, ‘FPGA
Implementation of DSDV Based Router In Mobile
Ad-hoc Network’, IEEE, ICIIS, August 2006, Sri
Lanka.
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[2] M. Ramakrishnan, Dr. S. Shanmugavel, ‘FPGA
Implementation of AODV Routing Protocol In
MANET’, IEEE, ICIIS , August 2006,Sri Lanka.
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Improved AODV Routing Protocol for Route Repair
Scheme’, IEEE Conference On Emerging Trends in
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Bibliography
Pooja Srivastava is currently working as
Assistant Professor in Department of Electronics at
Banasthali University, Rajasthan, India. She received her
B.Tech. degree in Electronics and Communication
Engineering from Uttar Pradesh Technical University,
Lucknow, U.P., India in 2006 and M.Tech. (VLSI Design)
from Banasthali University, Rajasthan, India in 2009. She
has five year teaching experience and published several
research papers in National and International Journals. Her
research interest includes Adhoc Networks, Wireless
Communication Systems, Turbo Codes, VLSI Design and
Fabrication Technology.
Dr. Seema Verma obtained her Master and
Ph.D degree in Electronics from Banasthali University in
1999 & 2003. She is currently working as Associate
Professor of Electronics and Head, Department of Aviation
Sciences at Banasthali University. She is Fellow of IETE,
Life Member of Indian Science Congress, Life member of
International Association of Engineers, (IAENG). She is
in the Pearl edition of Who's Who in the World (2013).
She is an active research supervisor and 4 Ph.Ds have been
awarded under her guidance. She has been frequently
invited to present invited or plenary keynote lectures at
international conferences in India & abroad. She has
presented many papers in various international conferences.
She has published many research papers in various journals
of repute. She has many projects from UGC (under R&D
Major research project scheme, UGC Innovative Course
Scheme) & AICTE to her credit. She is currently into the
editorial board of many international journals in the field
Wireless Communication and Coding. Her research areas
are Coding theory, TURBO Codes, Wireless sensor
networks, Aircraft Ad-hoc networks, Network Security &
VLSI Design.
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Priya Singh received her B.Tech. degree from
RGTU Bhopal, M.P., India in 2012 and pursuing M.Tech.
from Banasthali University.
Bharti Garg received her B.Tech. degree from
MDU Rohtak, Haryana, India in 2012 and pursuing
M.Tech. from Banasthali University.
Ankita Rastogi received her B.Tech. degree from
UPTU Lucknow, U.P., India in 2011 and pursuing M.Tech.
from Banasthali University.