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www.flextiles.eu 1 2 / 0 6 / 2 0 2 2 - W h a t i s F l e x T i l e s ? What is FlexTiles? What you always wanted to ask, but never did!
| Date post: | 19-Jun-2015 |
| Category: |
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www.flextiles.eu
13/0
4/20
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W
hat i
s F
lexT
iles?
What is FlexTiles?What you always wanted to ask, but never did!
2 /
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1.1
Project Downview
The hard facts about FlexTiles!
Starting Date 15 October 2011
Ending date 15 April 2015 (pending approval of extension)
Official Project Number TRT/DJ/624412785.2011
Partners: 9 Countries: 5
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1.1
Project Leader
Who are the FlexTiles Consortium Members?
Project Coordinator: Thales, Palaiseau, France.
Expertise Management, Accelerator IP-Core in FPGA, Design of Heterogeneous Systems
4 /
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Fle
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
Industrial Partner: Associated Compiler Experts B.V., Amsterdam, Netherlands
Expertise Parallelisation and Compilation Tools
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Fle
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vers
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
R&D Partner: Commissariat à l’Energie Atomique et aux Energies Alternatives, Grenoble, France
Expertise 3D Stacking Design, Network-on-Chip Design
6 /
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
R&D Partner: CSEM Centre Suisse d’Electronique et de Microtechnique S.A., Neuchâtel,
Switzerland.
Expertise Ultra low-power processors, DSP accelerator
7 /
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ate
vers
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
University Partner: Karlsruhe Institute of Technology, Karlsruhe, Germany
Expertise Virtualisation Layer for Self-Adaptive Systems, Open Virtual Platform
8 /
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
Industrial Partner: Sundance Multiprocessor Technology Ltd., Chesham, UK
Expertise PCB-level design, testing and validation
9 /
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
University Partner: Eindhoven University of Technology, Eindhoven, Netherlands
Expertise Network-on-Chip, Composable kernel, Cyclic Static Data Flow (CSDF)
10 /
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Fle
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ate
vers
ion
1.1
Project Partner
Who are the FlexTiles Consortium Members?
University Partner Université de Rennes 1, Rennes, France
Expertise Re-configurable FPGA design and validation
11 /
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Fle
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ate
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1.1
Project Partner
Who are the FlexTiles Consortium Members?
University Partner: Ruhr University of Bochum, Germany
Expertise FPGA design, System Integration
12 /
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Wha
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Fle
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ate
vers
ion
1.1
Project Challenges
What are the FlexTiles Challenges? To address the steadily increasing application of dynamicity using
self-adaptive capabilities
To increase the software development productivity of manycore for Time-to-Market and cost reasons and to enable legacy software and hardware codes
To increase accessibility to manycore technologies and propose a European alternative on the worldwide market of this technology
To increase energy efficiency for embedded systems and High-Performance Computing (HPC) systems
13 /
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The
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T/D
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785.
2011
). T
empl
ate
vers
ion
1.1
Project Goals
What are the FlexTiles Goals? Raise the programming efficiency of heterogeneous manycores
Develop a dynamic reconfigurable technology with pre-emption and relocation capabilities
Enable self-adaptation with a virtualisation layer
Develop a heterogeneous manycore based on available IP-Core for generic interfaces
14 /
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(TR
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2011
). T
empl
ate
vers
ion
1.1
Project Deliverables
What are the FlexTiles Deliverables? SystemC simulator and FPGA demonstrators for the heterogeneous
manycore architecture
Physical design results for embedded reconfigurable technology on a layer of 3D stacking
Open-sourced demonstrator to enable implementation of an application
Complete A-Z tool chain to develop an application to use FlexTiles demonstrator with virtualisation of each layer
15 /
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ate
vers
ion
1.1
Project Milestones
What are the FlexTiles Major Milestones?
Milestone Year 1 Define the FlexTiles architecture
Define a software simulator (OVP based) and a hardware emulator (FPGA based)
Milestone Year 2 Deliver the PCB for the hardware emulator of the FlexTiles architecture – www.flextilex.biz
Develop a software simulator of the FlexTiles architecture using - http://www.ovpworld.org/
Milestone Year 3 Integrate the VHDL models of the FlexTiles architecture in the FPGA emulator
Complete an application with multiple GPPs and accelerators (DSPs and/or logic in an embedded FPGA) running on the hardware emulator and software simulator
Complete a tool-chain for the use of the FlexTiles architecture
16 /
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(TR
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empl
ate
vers
ion
1.1
Project Disseminations
What are the FlexTiles Disseminations?
Workshop AHS’14 on 18th July 2014 - Leicester, England
http://www2.le.ac.uk/conference/ahs2014/workshops
FPL’14 on 1st September 2014 - Munich, Germany http://www.fpl2014.org/en/workshops/
Papers http://flextiles.eu/WordPress3/?page_id=385
Presentations http://flextiles.eu/WordPress3/?page_id=32
17 /
13/
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(TR
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4412
785.
2011
). T
empl
ate
vers
ion
1.1
Project Disseminations
What are the FlexTiles Disseminations?
FlexTiles Twitter News, etc.
FlexTiles YouTube Demos
FlexTiles LinkedIN Discussions about Heterogeneous Multiprocessing
Open-sourced Hardware Platform The PCB for the hardware emulator (FlexTiles Development Platform) is open source
Quick re-development for later generations of FPGA and demo
18 /
13/
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Fle
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The
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rmat
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ect
(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
The FlexTiles concept?
3D stack of 2 dies in a chip
A number of GPPs
A number of accelerators DSP
embedded FPGA
Project Unique Technology
19 /
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Fle
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(TR
T/D
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4412
785.
2011
). T
empl
ate
vers
ion
1.1
The FlexTiles buzz-words
Project Keywords
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The
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(TR
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2011
). T
empl
ate
vers
ion
1.1
Exploitation of project results
Most project results are available to third parties
Conditions are to be discussed with appropriate project members.
Contacts for Hardware: GPP node: TU/e
Network on Chip: TU/e, CEA
Accelerator interface: Thales
DSP node and tools: CSEM
Embedded FPGA architecture and tools: UR1
FPGA-based hardware emulator: Sundance, RUB, Thales, TU/e, CSEM
21 /
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(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
Exploitation of project results
Most project results are available to third parties
Conditions are to be discussed with appropriate project members.
Contacts for Software: C to CSDF tools: Thales, ACE, TU/e, KIT
OVP-based simulator: KIT
FPGA-based hardware emulator: Sundance, RUB, Thales, TU/e, CSEM
Microkernel, communication, resource management, reconfiguration middleware:
TU/e
Virtualization layer: KIT, TU/e
22 /
13/
04/
2023
-
Wha
t is
Fle
x Tile
s?
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
cop
ying
or
othe
rwis
e us
e of
thi
s do
cum
ent
mus
t be
don
e in
acc
orda
nce
with
the
CA
of
the
proj
ect
(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
FlexTiles Development Platform
What is the FDP? Hardware Emulator
Why did we need FDP? Early validation of architecture
Is it a Commercial Product? Yes! Contact Sundance.
Xilinx University Program Support
One of the project results
23 /
13/
04/
2023
-
Wha
t is
Fle
x Tile
s?
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
cop
ying
or
othe
rwis
e us
e of
thi
s do
cum
ent
mus
t be
don
e in
acc
orda
nce
with
the
CA
of
the
proj
ect
(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
FlexTiles Development Platform (FDP)
One of the project results
SMT166 – FPGA Carrier Board
FPGA_0Virtex 6
LX130T or SX475T
PSUSection
DDR3 MemoryBank 2
SLB/LPC-FMCMezzanine 0
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 1
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 2
SLB/Converter to FMC
PSU
SLB/LPC-FMCMezzanine 3
SLB/Converter to FMC
PSU
FPGA_1Virtex 6
LX130T or SX475T
DDR3 MemoryBank 3
DDR3 MemoryBank 0
DDR3 MemoryBank 1
RSL x2
mRSL x2
n
RSL x4
o i Channels x2
PCIeCable
x4
x4
l
MasterModule
SLB Connector
RSL
RSL
PCIeCable
x4
x4
j
PCIeCable
x1 x1
i
PCIeCable
x1x1
k
USB+CPLD +Flash
To configure Virtex6
FPGAs and access Master
Module Flash
ClockSynthesiser
Synchroniser
Top TIM Connector
Bottom TIM Connector
Dual SATA3.0
Dual SATA3.0
1Gigabit Ethernet
1Gigabit Ethernet
24 /
13/
04/
2023
-
Wha
t is
Fle
x Tile
s?
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
cop
ying
or
othe
rwis
e us
e of
thi
s do
cum
ent
mus
t be
don
e in
acc
orda
nce
with
the
CA
of
the
proj
ect
(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
FlexTiles Development Platform (FDP)
One of the project results
25 /
13/
04/
2023
-
Wha
t is
Fle
x Tile
s?
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
cop
ying
or
othe
rwis
e us
e of
thi
s do
cum
ent
mus
t be
don
e in
acc
orda
nce
with
the
CA
of
the
proj
ect
(TR
T/D
J/62
4412
785.
2011
). T
empl
ate
vers
ion
1.1
FlexTiles-II with 3D interposer andChiplet Processors
What next for FlexTiles ?System Architecture• Scale-out architecture• Coherent island with
remote communications
Chiplet• Small chips• Advanced technology node• Generic• High volume• Low cost
Interposer• Passive or active• Mature technology node• Application specific• Medium volume• Cost effective assembly• European fabs
