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Configuration

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Configuration Schemes Overview 9 n Active configuration schemes - Target FPGA generates control & synchronous signals n Passive configuration schemes - External host controls the configuration process FPGA External Memory Initiates configuration process Provides configuration data Configuration Controller Initiates configuration process and provides configuration data FPGA Configuration Device Configuration Controller Memory
Transcript
  • Configuration Schemes Overview

    9

    n Active configuration schemes - Target FPGA generates control & synchronous signals

    n Passive configuration schemes - External host controls the configuration process

    FPGA

    External

    Memory

    Initiates configuration process

    Provides configuration data

    Configuration

    Controller

    Initiates configuration process

    and provides configuration data

    FPGA

    Configuration

    Device

    Configuration

    Controller

    Memory

  • Active Configuration Schemes

    n Active serial (AS): - Configuration data gets loaded one bit at the time.

    - Supported memory device: serial configuration (EPCS) device.

    n Active parallel (AP): - Configuration data gets loaded 16 bits at a time.

    - Supported memory device: 16 bit parallel flash memory

    - Applicable to Cyclone III and Cyclone IV devices only.

    10

    FPGA

    External

    Memory

    Initiates configuration process

    Provides configuration data

    Configuration

    Controller

  • Passive Configuration Schemes

    n Passive Serial (PS): - Configuration data gets loaded one bit at a

    time

    n Passive parallel schemes: - Configuration data gets loaded 8 bits at a time

    - Supported schemes:

    l Fast passive parallel (FPP)

    l Passive parallel synchronous (PPS)

    l Passive parallel asynchronous (PPA)

    n JTAG Configuration: - Developed by Joint Test Action Group as a

    specification for boundary-scan testing

    - Standardized as IEEE Std. 1149.1

    - Test pin connections and functionality without using physical probes

    - Forced test data is serially shifted into boundary-scan cells

    - Captured data is serially shifted out

    - Captured data is compared with the expected results

    11

    FPGA

    EPC Device

    Configuration

    Controller

    Memory

    FPGA

    MAX II or

    External Processor

    Configuration

    Controller

    External Flash

    Memory

    FPGA

  • Configuration Schemes Comparison

    Active or passive

    configuration scheme

    Configuration

    scheme

    Serial or parallel

    configuration

    External memory and/or

    configuration device

    Width of

    configuration

    data

    Relative

    configuration

    time

    Active AS Serial EPCS device 1 Moderate

    AP Parallel Supported common flash interface

    (CFI) parallel flash memory

    16 Fast

    Passive PS Serial MAX II, MAX3000A/7000, or

    microprocessor with flash memory

    1 Moderate

    Serial EPC device 1 Moderate

    Serial Download cable 1 Moderate

    FPP Parallel MAX II, MAX3000A/7000, or

    microprocessor with flash memory

    8 Fast

    Parallel EPC device 8 Fast

    PPA Parallel MAX II, MAX3000A/7000, or

    microprocessor with flash memory

    8 Moderate

    JTAG Serial MAX II, MAX3000A/7000, or

    microprocessor with flash memory

    1 Slow

    Serial Download cable 1 Slow

    12


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