Microelectronic Engineering 88 (2011) 2941–2945

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Microelectronic Engineering

journal homepage: www.elsevier .com/locate /mee

Contactless read-out of printed memory

Mark Allen a,b,⇑, Mikko Aronniemi c, Tomi Mattila a, Panu Helistö d, Hannu Sipola d, Anssi Rautiainen d,Jaakko Leppäniemi a, Ari Alastalo a, Raimo Korhonen a, Heikki Seppä d

a Printed Functional Solutions, VTT Technical Research Centre of Finland, POB 1000, FI-02044 VTT, Espoo, Finlandb Department of Radio Science and Engineering, Aalto University, Otakaari 5 A, FI-02150 Espoo, Finlandc Vaisala Oyj, Vanha Nurmijärventie 21, FI-01670 Vantaa, Finlandd Sensors and Wireless Devices, VTT Technical Research Centre of Finland, POB 1000, FI-02044 VTT, Espoo, Finland

a r t i c l e i n f o

Article history:Received 16 December 2010Received in revised form 8 March 2011Accepted 7 April 2011Available online 13 April 2011

Keywords:Contactless read-outNon-volatile memoryNanoparticle inkInkjetRapid electrical sintering

0167-9317/$ - see front matter � 2011 Elsevier B.V. Adoi:10.1016/j.mee.2011.04.026

⇑ Corresponding author at: Printed Functional SolutCentre of Finland, POB 1000, FI-02044 VTT, Espoo, Fin

E-mail address: Mark.Allen@vtt.fi (M. Allen).

a b s t r a c t

Contactless read-out of inkjet printed programmable memory is demonstrated. The memory is arrangedas a conducting comb pattern consisting of parallel lines adjacent to a common electrode. The informa-tion content of the memory is stored in memory bits, which modulate the electrical surface-area of thelines. The data is read-out capacitively by sweeping the tip of a printed circuit board over the memory.The memory bits were printed using silver nanoparticle ink and switched from an initial, high-resistancestate to a low-resistance state using rapid electrical sintering, and furthermore, from the low-resistancestate to an open-circuit state via fuse-like action. This read-out approach offers potential for low-costmemory applications as well as e.g. resistance-change sensors.

� 2011 Elsevier B.V. All rights reserved.

1. Introduction

Printed electronics is foreseen to create large markets due to theability to enable the fabrication of a variety of devices on low-cost,flexible substrates using high-throughput printing methods [1–3].Hitherto, various printable non-volatile electronic memory config-urations have been demonstrated [4–9] and the first commercialprinted memory products are currently entering the market [10].

The rapid electrical sintering (RES) method [11] has recently beendemonstrated to enable a fully-printed programmable Write-Once-Read-Many (WORM) memory with low operating power [12]. Thismemory concept is also utilized in [13], where a fully operationalmemory card and a PC-controlled programming/reading deviceare reported.

We introduce and demonstrate contactless read-out of all-printedmemory by sweeping the tip of a printed circuit board (PCB) over thememory structure. A comb-like memory layout is introduced here,where the data is contained in memory bits inkjet printed betweenconducting lines and a conducting common electrode. These ‘‘hotspots’’ can be switched from the initial high-resistance state ‘‘0’’ to alow-resistance state ‘‘1’’ via RES, and, furthermore, from state ‘‘1’’ toan open-circuit state ‘‘2’’ via fuse-like action [13]. Data read-out is en-abled via capacitive coupling between the printed lines and the PCB.

ll rights reserved.

ions, VTT Technical Researchland.

According to the bit state, the line is either (i) electrically connected toor (ii) disconnected from the common electrode. This modulation isclearly detected in the read-out signal as the PCB tip is swept overthe memory.

Here, the length of the printed lines is chosen so as to enableeasy alignment of the PCB tip for read-out. First, we confirm goodagreement between simulations and measurements by comparingthe read-out for a sparse memory layout. Sufficient read-outresolution is also achieved for a memory with increased bit density(bit spacing below 0:5 mm) at a coupling distance above 10 lm.We further demonstrate successive read-out sweeps for this mem-ory as the bit states are switched. The sweep speed is fixed at25 mm=s (the maximum speed of the employed X–Y positioningsystem) although the utilized read-out sampling rate of 9600 bpswould allow for much faster sweep speeds. It should also be notedthat the PCB electrode dimensions and coupling distance can befurther optimized to increase the bit density. The maximum bitdensity is ultimately limited by the resolution of the printingprocess.

2. Read-out method

The memory layout considered in this study consists of parallellines (length lL, width wL and minimum line separation distance gL)adjacent to a conducting common electrode (length lC and widthwC) as shown in Fig. 1. Printed memory bits connect the lines tothe common electrode over a bit gap distance of gB. Part of the lines

lC

wC

lL

wL

Common electrode

Line gL

gB

Closed bit

Memory bit

A B C D E F G

lC

wC

lL

wL

Common electrode

Line gL

gB

Closed bit

Memory bit

A B C D E F G

Fig. 1. Comb-like layout for the all-printed memory, where memory bits separatethe conducting lines from a conducting common electrode. In the imaged sample,the lines (length lL ¼ 5 mm and width wL ¼ 0:7 mm), common electrode (lengthlC ¼ 20 mm and width wC ¼ 2 mm) and memory bits (bit gap distancegB ¼ 0:15 mm) have been inkjet printed with silver nanoparticle ink.

A B

Ground

Common electrode

Line (L)

C1 C2

CGND

CINTCACB

Bit

(a)

VA VBCA CBCGND

C1 C2

CINT

CGND

(L)

Sweep direction

A B

A B

Ground

Common electrode

Line (L)

C1 C2

CGND

CINTCACB

Bit

(b)

VA VBCA CBCGND

C1 C2

CINT

CGND

(L)

Sweep direction

A B

Fig. 2. (a) Schematic illustration of the coupling electrodes (A and B) at the tip ofthe PCB. The information content of the memory is read-out by sweeping the PCBtip over the printed lines. (b) Equivalent circuit model when the inkjet printed linesand common electrode are assumed to have low sheet resistance.

2942 M. Allen et al. / Microelectronic Engineering 88 (2011) 2941–2945

are permanently interconnected to the common electrode for ref-erence (closed bits).

The contactless read-out is based on capacitive coupling be-tween the printed patterning and the PCB. Fig. 2(a) shows thePCB tip above a conducting line. The voltage signal transferredfrom electrode A to electrode B with respect to ground is mea-sured. In Fig. 2, CINT;C1 and C2 represent the internal capacitancebetween the electrodes A and B, and the coupling capacitance be-tween each electrode and the line, respectively, while CA;CB andCGND are the capacitances of the electrodes and the memory pat-tern with respect to the ground electrode. Assuming that the resis-tance across the printed line is negligibly small with respect to thecoupling reactance, the setup can be approximated with the equiv-alent circuit shown in Fig. 2(b).

The information content of the memory is programmed into thesmall memory bits (‘‘hot spots’’) separating each line from thecommon electrode. Here, we program the memory by coupling avoltage across selected bits in order to switch the bit from state‘‘0’’ to state ‘‘1’’, or furthermore, from state ‘‘1’’ to state ‘‘2’’ (thememory operation is described in detail in the following section).The highly conducting lines and common electrode provide a largeeffective surface area for capacitive coupling. When a large PCBground electrode is applied, the switching of the memory bit be-tween the high and low resistance states changes the effective sur-face area of the conducting line and modulates CGND accordingly.This coupling scheme thus facilitates direct read-out of the mem-ory data by simply sweeping over the parallel lines without havingto align the PCB tip precisely to the small memory bits.

From Fig. 2(b), the voltage transfer function can be expressed as

T � VB

VA¼ CINT þ Cy

CINT þ Cy þ CB þ Cz; ð1Þ

where Cy ¼ C1C2=CR and Cz ¼ C2CGND=CR, with CR ¼ C1 þ C2 þ CGND.In the absence of a line below the coupling electrodes (PCB tip onbare substrate), Eq. (1) simplifies to

T ¼ CINT

CINT þ CB� T0: ð2Þ

T0 is assigned here as the reference null-level. Efficient data read-out resolution is achieved when (i) C1 and C2 are large enough withrespect to CINT in order to significantly deviate T from T0 when thePCB tip is above the line and (ii) the magnitude and/or sign of T ismodulated via CGND according to the state of the corresponding

memory bit. For the bit states ‘‘0’’ and ‘‘2’’ (line electrically discon-nected from common electrode), we expect to have weak groundcoupling. If particularly ðCGND=C1Þ < ðCB=CINTÞ, we will have T > T0.For a bit in state ‘‘1’’ (sintered/closed bit), we have strongground coupling via the common electrode preferably such thatðCGND=C1Þ > ðCB=CINTÞ and T < T0.

Contactless read-out of printed memory is demonstrated hereusing a prototype head compiled on an FR4 PCB with 75 lm metal-ization thickness and 75 lm dielectric spacing. The coupling elec-trodes A and B are 500 lm in length and 800 lm in height withthe electrode width and spacing of 75 lm defined by the PCBmetalization thickness and dielectric spacing. The PCB groundelectrode is 55 mm high and 18 mm wide. The operating frequencyis f ¼ 50 MHz, data sampling rate 9600 bps; CA ¼ 20 pF andCB ¼ 1 pF. In this work, the printed memory is covered with anelectrically insulating sheet (12.7 lm thick Kapton HN polyimidefilm used here) to fix the coupling distance.

3. Simulation

Electromagnetic simulations with Ansoft’s high frequencystructure simulator (HFSS) provide CINT � 250 fF for the internalcapacitance in the absence of conducting patterning below the

M. Allen et al. / Microelectronic Engineering 88 (2011) 2941–2945 2943

PCB tip. Thus, from Eq. (2) we obtain T0 ¼ 0:2 for the referencevoltage transfer null-level. The simulated coupling capacitance be-comes C1 ¼ C2 � 120 fF when the PCB tip is centered on a line ofFig. 1 with wL ¼ 0:7 mm and lL ¼ 5 mm. From Eq. (1), we obtainT ¼ T0 when CGND � 480 fF. The simulations indicate that thecapacitance between the memory layout of Fig. 1 and the PCBground electrode is CGND � 160 fF and CGND � 520 fF for an openbit gap ðgB ¼ 0:15 mmÞ and a closed bit, respectively. Moreover,Fig. 3(a) shows the simulated sweep-over response for the line ofwidth wL ¼ 0:7 mm terminated with either an open bit gap or aclosed bit. Here, wC ¼ 2 mm; lC ¼ 20 mm, and the sheet resistanceof the lines and common electrode is assumed to be 100 mX=�.Evidently, the modulation of CGND according to the bit state isclearly visible in the read-out response. The response at the lineedges is asymmetric and depends on which of the coupling elec-trodes, A or B in Fig. 2, first passes over the line. For example, thelarge negative peak at position �0:35 mm in Fig. 3(a) correspondsto an offset, where only electrode B is located above the line. Thesimulation of Fig. 3(a) was completed by shifting the geometry ata spatial resolution of 0:025 mm.

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Position, x [mm]

Open bitClosed bit

0 2 4 6 8 10 12-0.5

0

0.5

1

Position, x [mm]

(a)

(b)

Nor

mal

ized

read

-out

volta

ge, ν

N[a

.u.]

Nor

mal

ized

read

-out

volta

ge, ν

N[a

.u.]

A B C D E F G

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Position, x [mm]

-0.5

0

0.5

1

Position, x [mm]

ν N[a

.u.]

ν N[a

.u.]

A B C D E F G

Fig. 3. Normalized read-out voltage mN ¼ ðT � T0Þ=ðmax jT � T0jÞ as a function ofposition. (a) HFSS simulation result for a line with dimensions wL ¼ 0:7 mm andlL ¼ 5 mm terminated with an open (state ‘‘0’’ or ‘‘2’’) vs. closed (state ‘‘1’’) bit. (b)Measured read-out response for the memory base pattern of Fig. 1. The sequence ofopen bit gaps and intentionally short-circuited (closed) bits is clearly evident. Inboth (a and b), CGND is modulated by selectively connecting/disconnecting thecommon electrode with wC ¼ 2 mm and lC ¼ 20 mm from the lines.

4. Experimental

The demonstrated electrically programmable memory wasprinted in two stages: the conducting base pattern (lines and com-mon electrode) was first printed in one session and the memorybits were printed afterward as a separate processing stage. The Sil-verjet DGP-45LT-15C (denoted DGP from here on) silver nanopar-ticle ink supplied by Advanced Nano Products Co., Ltd. (ANP) wasfirst inkjet printed onto the Epson inkjet transparency film sub-strate (polyethylene terephthalate (PET) film with silica-based li-quid-absorbing coating layer) at room temperature using anindustrial-scale inkjet printer (Apollo II PSK with a Spectra SX-128 head on the iTi system) at 100 mm=s head speed and600 dpi printing resolution. This ink-substrate combination pro-vides conductivity above 8� 106 S=m (corresponding to below� 100 mX=� sheet resistance) via in situ substrate-facilitated sin-tering at room temperature [14]. At this stage, all samples haveidentical base patterns containing the same information hard-coded via the sequence of open bit gaps and intentionally short-circuited (closed) bits.

Fig. 3(b) shows the measured read-out response for the layoutshown in Fig. 1 with wL ¼ 0:7 mm; lL ¼ 5 mm and gL ¼ 0:6 mm(the memory bits visible in Fig. 1 were not yet printed at thisstage). For read-out, the sample was mounted on a motorized stageand covered with an insulating sheet (12.7 lm thick polyimidefilm). With the PCB card held at a fixed position, the sample wasraised until the coupling electrodes came into contact with theinsulating sheet. Read-out was then carried out by sweeping thelines below the PCB tip at 25 mm=s. Fig. 3 confirms a good fit be-tween the simulated and measured response, where the magni-tude of the normalized transferred voltage, mN, for a lineterminated with a closed bit is significantly depressed with respectto that of a line with an open bit.

The memory bits were printed with Silverjet DGH-55HTG (de-noted DGH from here on) silver nanoparticle ink (also suppliedby ANP) using the Microdrop Autodrop lab-scale printer with70 lm nozzle diameter at room temperature. As opposed to theDGP ink,1 the DGH ink2 does not undergo spontaneous substrate-facilitated sintering when printed on the Epson substrate. Hence,after printing, the unsintered bits provide a high interconnect resis-tance (typically above 10 kX).

Here, we utilize RES to program the memory bits from the high-resistance state ‘‘0’’ to the low-resistance state ‘‘1’’. RES is realizedby applying a voltage (i.e., an electric field) over the unsinterednanoparticle layer. The applied voltage generates power dissipa-tion in the printed bit thus enabling rapid sintering of the nanopar-ticles [11]. A variable resistor, Rs, is applied in series with the bit inorder to limit the maximum current once the structure is sintered.Fig. 4(a) shows the measured bit resistance and switching voltageduring the transition from state ‘‘0’’ to state ‘‘1’’ for a typicalprinted bit. The voltage VDC is coupled across the bit and thecurrent-limiting resistor, which in Fig. 4(a) was set to Rs ¼ 533 X.

We also demonstrate bit state switching from the low-resistancestate ‘‘1’’ to an open-circuit state ‘‘2’’ using the same setup compris-ing the voltage source, VDC, and the variable resistor, Rs. Here, thesintered bit, with RB typically below 50 X, is burned open by drivingcurrent through the interconnect (fuse-like action [13]). Fig. 4(b)shows RB and VDC for the transition from state ‘‘1’’ to state ‘‘2’’ whenRs ¼ 12 X. Fig. 4 thus verifies this memory concept to provide low-

1 Silverjet DGP-45LT-15C contains polymer-capped silver nanoparticles withaverage particle diameters of 40—50 nm dispersed in triethylene glycol monoethylether.

2 Silverjet DGH-55HTG contains thiol-capped silver nanoparticles with averageparticle diameters of 8—12 nm dispersed in n-tetradecane.

(a)

(b)

102

103

104

105

Bit

resi

stan

ce, R

B[Ω

]

3002001000

Time, t [ms]

10

8

6

4

2

0

Total voltage, V

DC

[V]

102

103

104

105

Bit

resi

stan

ce, R

B[Ω

]

3002001000

Time, t [ms]

10

8

6

4

2

0

Total voltage, V

DC

[V]

Bit

resi

stan

ce, R

[Ω]

Time, t [ms]

10

8

6

4

2

0

VD

C[V

]

Bit

resi

stan

ce, R

B[Ω

]

Time, t [ms]

10

8

6

4

2

0

VD

C[V

]

Fig. 4. Measured bit resistance, RB, and applied voltage, VDC, during bit stateswitching. (a) Transition from the high-resistance state ‘‘0’’ to the low-resistancestate ‘‘1’’ via RES. (b) Transition from state ‘‘1’’ to the open-circuit state ‘‘2’’ via bitburning (fuse-like action).

A B C D E F

-0.5 0 0.5 1 1.5 2 2.5 3 3.5-0.5

0

0.5

1

Position, x [mm]

Nor

mal

ized

read

-out

volta

ge, ν

N[a

.u.]

Sweep 1 Sweep 2 Sweep 3

A B C D E F

(a)

(b)

200 µm

A B C D E F

-0.5 0 0.5 1 1.5 2 2.5 3 3.5-0.5

0

0.5

1

Position, x [mm]

Nor

mal

ized

read

-out

volta

ge, ν

N[a

.u.]

Sweep 1 Sweep 2 Sweep 3

A B C D E F

(a)

(b)

200 µm

Fig. 5. Contactless read-out of printed memory. (a) An electrically programmableinkjet printed memory. Memory bits connecting the conducting lines to thecommon electrode are shown in the inset. (b) Normalized read-out voltagemN ¼ ðT � T0Þ=ðmaxjT � T0jÞ when the PCB tip is swept over the selected lineslabeled A–F. In sweep 1, the bits corresponding to lines A, C, E and F are in state ‘‘0’’.In sweep 2, lines A, E and F are short-circuited to the common electrode via state‘‘1’’ bits. In sweep 3, line E is once again disconnected from the common electrodevia a state ‘‘2’’ bit. The reference lines B and D remain connected to the commonelectrode via closed bits during all sweeps.

2944 M. Allen et al. / Microelectronic Engineering 88 (2011) 2941–2945

voltage, two-state memory operation with below 100 ms switchingtimes demonstrated.

The memory layout shown in Fig. 5(a) has been modified fromthat of Fig. 1 to increase the bit density. Now wL ¼ 0:3 mm andgL ¼ 0:15 mm while the other layout dimensions ðlL ¼ 5 mm;gB ¼0:15 mm; lC ¼ 20 mm and wC ¼ 2 mmÞ remain unchanged. The in-set of Fig. 5(a) provides a close-up of the printed memory bitsinterconnecting the lines to the common electrode.

Fig. 5(b) shows the read-out response for the lines marked withthe letters A–F in Fig. 5(a). The reference lines B and D are termi-nated with closed bits, which remain permanently in state ‘‘1’’. Insweep 1 of Fig. 5(b), the bits connecting the lines A, C, E and F tothe common electrode, are in the high-resistance state ‘‘0’’ and,expectedly, these lines induce positive-valued peaks in the read-out signal due to weak ground coupling. In sweep 2, the bits corre-spondent to lines A, E and F have been switched (via RES) to state‘‘1’’. This switch is visible in the read-out response as a change fromhigh signal peaks to almost non-existent ripple about the null-level.In sweep 3, the memory bit joining line E to the common electrodeis further switched from the low-resistance state ‘‘1’’ to the open-circuit state ‘‘2’’. Now, the amplitude peak corresponding to line Ehas reappeared in the read-out signal. An unsintered bit can also

be programmed directly from state ‘‘0’’ to state ‘‘2’’ as is demon-strated with line C in Fig. 5. Evidently, with the bit resistance andcoupling reactance values applied here, it is not possible to distin-guish between the bit states ‘‘0’’ and ‘‘2’’ arbitrarily.

5. Conclusions

Contactless read-out of all-printed programmable memory wasreported. The demonstrated memory design offers potential forhigh-throughput roll-to-roll (R2R) production. A significant benefitof the introduced read-out scheme is that only a very small volumeof the memory bit material joining the conducting lines to thecommon electrode is required. Thus, the switching voltages andmaterial costs remain low. In fact, an equivalent contactless cou-pling method could possibly be utilized also for electrically switch-ing the bit states by inducing an appropriate AC voltage over thebits. This approach would allow for the complete encapsulationof the memory with a moisture-protective barrier film in orderto extend the shelf-life of the state ‘‘0’’ bits (retention times of

M. Allen et al. / Microelectronic Engineering 88 (2011) 2941–2945 2945

more than 100 days for unsintered bits stored at low relativehumidity are reported in [12]).

This read-out method does not require accurate alignment ofthe PCB tip to the actual memory bits. The coupling electrodesand memory layout dimensions can be adjusted to provide a max-imum output ratio for a targeted coupling distance (to enable e.g.read-out through a thicker packaging material without line-of-sight required). The presented read-out scheme can, more gener-ally, be applied to e.g. printed resistance-change sensors such asthe all-printed hydrogen sulfide sensor reported in [15].

Acknowledgments

The authors thank Mr. Seppo Kuosmanen of VTT for performingpart of the printing work. The research leading to these results hasreceived funding from the Finnish Funding Agency for Technologyand Innovation (Tekes, Grant 40250/07) and the Seventh Frame-work Program FP7/2007 2013 of the European Commission underGrant Agreement No. 215132 (project PriMeBits).

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