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MobileMAN Hardware development for the MAC module:

current state and outlook by

Ralph Bernasconi, Ivan Defilippis, Silvia Giordano, Alessandro Puiatti

SUPSI Manno

Cambridge, March 23 2004

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Contents

Introduction Steps done Where we are Next steps Data structure description Cross-layering questions

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IntroductionProject’s SUPSI-DIE goals (reminder)

Provide flexible development- and test-bed for enhanced WLAN protocol (CNR)

Bursty responsive MAC Better contention scheme (backoff); avoid collisions even

for dense and active networks Ensure compatibility with 802.11x

Provide few samples to partnersProvide inputs for new standard

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Analysis of the Market for the 802.11 implementationso Which kind of solutions were presento Which solution best suited our needs

- Cost- Reliability- Flexibility- Access to the software code- Access to the firmware- Easy development environment- Secure and prompt technical support

Steps Done (1/5)

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Analysis of the implementation starting point in relation with the market analysis

o Starting from scratch: - Implementation fo all the chain: MAC - BB - RF

o Starting from a “middle point“:- Implementation of the MAC only

o Starting from an already implemented solution:- Change software and firmware for our pourpose

Steps Done (2/5)

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Choosed solution

o Starting from a “middle point“

o BB and RF already developed by Elektrobit AG:

- DT20 Modem

o Ourselv MAC implementation on Texass Instrument DSP:

- TI C6713 board

Steps Done (3/5)

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Analysis of 802.11 standard in deepo Procedures and flowchart for the TX/RX farther implementation

Implementations on a single boardo CRC on FPGAo TX/RX between MAC and BBo Channel Sensig machanism on MAC, (MAC – RF)o MAC TX mechanism on DSPo MAC RX mechanism on DSPo Standard Backoff mechanismo Regular 802.11 frame generationo Fragmented frame generation

Steps Done (4/5)

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Steps Done (5/5)

Duplicate above steps in a second boardStress tests in TX between boards connected by

cableStress tests in RX between boards connected by

cableStress tests in TX/RX between boards connected by

cableStress tests in TX/RX between boards in wireless

mode

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Where we are

TX/RX of regular 802.11 frames OKBackoff mechanism implementedTX/RX of fragmented frame OKRTS/CTS/DATA/AK handshake not yet implemented

Level-Switch interfaces

DT20 - Modems

TI C6713 boards

JTAG interface

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Next Steps

RTS/CTS/DATA/AK handshakeTest of Backoff standardImplementation on a third boardCommunication tests with three cardsImplementation of new Backoff algorithmCommunication between board and PC through

FireWire interfaceImplementation of Data structure

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Data Structure description (1/4)

Memory slotted in parameterized slot length (default frame max length)

Descriptor mechanism for handling data Different queues for managing data transfer:

o From MAC to PHY and from PHY to MAC

o From MAC to Host and from Host to MAC

Implementation of priority mechanisms for each queue Control flags in descriptor in which:

o DATA = Frame

o DATA = parameters for/from cross-layering

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Data Structure description (2/4)

MAC header x

FCS x

Frame

Memory Data Area

MAC(DSP)

Frame body x+1

Frame body x

Descriptor x

Descriptorx+1

End HMQ

Descriptor x+n+1

MAC h. y+n-1

Frame body y+n-1

FCS y+n-1

MAC h. y+n

Frame body y+n

FCS y+n

Descriptorx+n

Frame body x+n

Frame body x+n+1Descriptor y+n-1

Descriptory+n

End MPQ

MAC to PHY Queue

BeginHost to MAC

Queue

BeginHost to MAC

Queue

End MPQ

End HMQ

MAC h. y+n+1

FCS y+n+1

Frame body y+n+1

Descriptor y+n+1

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Data Structure description (3/4)

MAC header y

FCS y

Frame

Memory Data Area

MAC(DSP)

Frame body x+1

Frame body x

Descriptor x

Descriptorx+1

End MHQ

MAC h. y+1

Frame body y+1

FCS y+1

MAC h. y+2

Frame body y+2

FCS y+2

Descriptorx+n

Frame body y

Descriptory+2

Descriptor y+1

End PMQ

PHY to MAC Queue

BeginMAC to Host

Queue

Begin

Descriptor y

Frame body x+n

End MHQ

PHY to MAC Queue

Begin

Frame body x+n+1

Descriptor x+n+1

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Data Structure description (4/4)

Management of queues with different levels of priority

Descriptor 1Pn

Descriptor 1Pn-1

End Q

DescriptorP0

Descriptor 2Pn

Descriptor 3Pn

Descriptor 4Pn

Descriptor kPn

End Q-PnDescriptor 2

Pn-1Descriptor h

Pn-1

End Q-Pn-1

Descriptor 2P0

Descriptor 3P0

Descriptor gP0

End Q-P0

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Cross-Layering Questions

How we think to implement the cross-layering:o A shared memory area in the host?o A s.m.a made in two blocks: one in the host and one in the

MAC?o Other?

Who is the manager of the cross-layering data flow?In which way the layers access the cross-layer area?Which parameters we have to put in the cross-layer

area?

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Questions?Thanks for your attention!