Control Loop Coockbok 41 Pag.

INTRODUCTION:Switching power supplies use closed-loop

feedback to achieve design objectives for line andload regulation and dynamic response.Fortunately, the closed-loop systems used inswitching power supplies are usually not very com-plicated, permitting the use of simple analyticaltechniques to achieve loop stabilization. A simpli-fied version of the Nyquist stability criteria can beused because unity gain crossover occurs onlyonce in the gain vs. frequency characteristic. Bodeplots provide a simple and powerful method of dis-playing and calculating the loop gain parameters(see Appendix B). This paper begins with a quickreview of basic control loop theory.

Linear Control Loop TheoryAs shown in Figure 1, a power supply feedback

loop can be described in terms of small-signal lin-ear equivalent gain blocks. The (s) appended tocertain gain blocks indicates that the gain varies asa function of frequency.

KEA(S) Error amplifier with compensation

KMOD Pulse width modulator

KPWR Power switching topology

KLC(S) Output power filter

KFB Feedback

Although the pulse width modulator and powerswitching circuit are really not linear elements, theirstate-space averaged linear equivalents can be used at frequencies below the switchingfrequency, fS.

Open-loop and closed-loop gain:The open-loop gain, T, is defined as the total

gain around the entire feedback loop (whether theloop is actually open, for purpose of measurement,or closed, in normal operation).

T(s) = KEA • KMOD • KPWR • KLC • KFB (1)

Closed-loop gain, G, defines the output vs.control input relationship, with the loop closed:

5-1 Control Loop Cookbook

Control Loop CookbookLloyd H. Dixon

Figure 1. - Feedback Loop

G(s) = (2)

At low frequencies, open-loop gain T is nor-mally very much greater than 1, so that closed-loopgain G approaches the ideal 1/KFB. At higher fre-quencies, T diminishes, mostly because of thelow-pass filter characteristic KLC(S). The frequencywhere T has diminished to 1 (0dB) is defined as thecrossover frequency, fC. Referring to Eq. 2 andFigure 2, at fC (where T = 1, with associated 90°phase lag), the closed-loop gain G(s) is 3db down(with 45° phase lag). Thus, the open-loop cross-over frequency is also the closed-loop “cornerfrequency”, where G(s) rolls off.

In a power supply voltage control loop, G(s)defines the power supply output vs. the referencevoltage. KFB is usually a simple voltage divider. Forexample, if VREF is 2.5 V, a 2:1 divider (KFB = 0.5, G= 2) results in VOUT = 5 Volts. (Refer to Appendix A.)

In a two-loop system (as with current-modecontrol, to be discussed later) the closed-loop gainG(s) of the inner loop is one element of the open-loop gain T(s) of the outer loop.

“Gain” elements as shown in Figure 1 need nothave the same units for their output and input(such as Volts/Volt). If Fig. 1 is a current mode con-trol loop, “Output” is a current source, and KFB ismost likely a current sense resistor. KFB “gain” isthen expressed in Volts/Amp, and closed loop gainG(s) is actually a transconductance (Amps/Volt).Pulse width modulator KMOD has its gainexpressed as d/V (Duty cycle/Volt). This discrep-ancy in “gain” units is resolved in the next gainblock, KPWR, whose characteristic is V/d.

Overall open-loop gain T(s) determines howmuch output error results from a disturbance intro-duced at any point in the loop compared to the resultif the loop was open. Project the disturbance forwardto the output (multiply by the gain between the dis-turbance and the output), then divide by totalopen-loop gain, T. For example, with no feedback(open loop, constant duty cycle), a 10% change inVIN results in a 10% VOUT change. With the feed-back loop closed, if T is 100 at the frequency of thedisturbance (DC in this example), then the VOUTchange is only 0.1% (10%/100). Note that theOutput accuracy does not depend significantly onopen-loop gain accuracy. In the example above, if Twas 80 instead of 100, VOUT would change by0.125% (10% ³VIN/80), instead of 0.1%. However,output accuracy does depend directly on the accu-racy of the feedback portion of the control loop, KFB.

Alternatively, a disturbance can be projectedback to the summing point at the input of the erroramplifier. For example, the 1Volt “valley” voltage ofthe sawtooth ramp applied to the PWM compara-tor is effectively a 1Volt DC offset or “disturbance”.If the E/A gain is 1000, this 1V error is equivalentto a 1mV error in the reference voltage, and trans-lates into the same percentage error at the output.

Nyquist Stability Criteria:Referring to Figure 2, if the open-loop gain T

crosses 1 (0 dB) only once, the system is stable ifthe phase lag at the crossover frequency, fC, is lessthan 180° (in addition to the normal 180° phaseshift associated with any negative feedback sys-tem). Let us define the term “phase lag” to refer toany additional amount of phase lag beyond the180° inherent with negative feedback. If the (addi-

T1 + T

1KFB

5-2Control Loop Cookbook

Figure 2. - Open & Closed Loop Gain

tional) phase lag at fC exceeds 180°, the loop willoscillate at frequency fC.

The “phase margin” is the amount by which thephase lag at fC is less than the critical value of180°. The ‘gain margin’ is the factor by which thegain is less than unity (0 dB) at the frequencywhere the phase lag reaches 180°. If the phase lagat fC is only a few degrees less than 180° (smallphase margin), the system will be stable, but willexhibit considerable overshoot and ringing at fre-quency fC. A phase margin of 45° provides forgood response with a little overshoot, but noringing.

Note that Nyquist’s 180° phase limit appliesonly at fC. At frequencies below fC, the phase lagis permitted to exceed 180°, even though the open-loop gain is very much greater than 1. The systemis then said to be conditionally stable. But if theloop gain temporarily decreases so that fC movesdown into the frequency range where the phaselag exceeds 180°, conditional stability is violatedand the loop becomes unstable. This actually doesoccur whenever the system runs into large signal

bounds, such as when a large step load changeoccurs. The system will then oscillate and probablynever recover. So it is not a good practice todepend upon a conditionally stable loop.

How can the loop be stable with 180° phaselag and gain much greater than 1 ??

Figure 3 shows the summing point voltagevectors at a frequency where the open loop gain is10, for three different amounts of phase lag aroundthe loop.

Figure 3a shows the vector relationship withzero additional phase lag. This condition usuallyoccurs at low frequencies where there are noactive poles, so that the gain characteristic slope iszero (flat). The feedback voltage vFB is 10 timesgreater than error voltage vE and 180° out ofphase. (Note that with an open-loop gain of only10, the vE magnitude causes vC to be less thanvFB. This inequality diminishes with higher loopgain.)

Figure 3b shows the vector relationship with again of 10 but at a frequency where one pole isactive, resulting in –1 gain slope and 90° phase


Figure 3. - Vector Diagrams - Gain = 10

lag. Feedback voltage vFB is 10 times greater thanvE, but lags by 270°. Note that vE now causes verylittle inequality between vC and vFB because of itsphase. This situation is perfectly stable. With vC =1 V and open-loop gain of 10 with 90 ° phase lag,only this outcome is possible.

In Figure 3c, two poles are active at the fre-quency where the gain is 10, resulting in –2 gainslope and 180° additional phase lag. Feedbackvoltage vFB is now in-phase with vE and 10 timesgreater. Our intuition tells us that this should be arunaway situation. But intuition is wrong, when ourthinking is restricted to this one frequency. Thevector relationships in Fig. 3c are perfectly stable.They are locked in to each other. This is the onlyway they can exist, under the defined conditions.Note that vE now causes vFB to be greater than vC.This does not signify instability – in fact, if the gainis increased further, vFB becomes smaller, reduc-ing the error without becoming unstable.

Why does oscillation occur only at fC, wherethe open loop gain equals 1 ??

The vectors of Figure 4a show the stable con-dition that exists when the gain slope is –1 as itpasses through the crossover frequency. The sin-gle active pole results in 90° phase lag. Feedbackvoltage vFB is equal to vE, but lags by 270°. Again,this is the only possible relationship between thesevectors under the conditions defined. Note thatvFB, which represents the output, lags control volt-age vC by 45° (plus 180° negative feedback), andthe magnitude is down 3dB to .707 (compared withFig. 3). This represents the closed-loop gain cornerat the open loop crossover frequency, as shown inFig. 2.

The vector diagram for a –2 gain slope at fCwhere open-loop gain equals 1 cannot be drawn,as it is unstable. Figure 4b shows the vectors at again of 1.2, instead. With a –2 slope, vE and vFBare in-phase. With a control voltage vC of 1V, afeedback voltage of 6 V with an error voltage of 5 Vis required to resolve the vector diagram. As theloop gain approaches 1, it can be seen that eithervC must become zero, or vE and vFB must becomeinfinite. Thus, the closed loop gain, vFB/vCbecomes infinite, even though the open-loop gain

is 1. The system is definitely unstable.

How to design a stable loop:The first step in the design of a stable, high per-

formance feedback loop is to define the gain/phasecharacteristic of each of the known loop elements(usually everything except the error amplifier, KEA).Then, the characteristic of the remaining elements(KEA) is tailored to complement the combinedcharacteristics of the other elements in a way thatwill meet the overall loop stability criteria whileachieving the highest possible loop gain and band-width.

In a switching power supply, the loop elementswhich actually handle the power are mostly definedby the parameters of the application. However,many options do exist, and they should beexplored. (Design experience helps to narrowdown the list of possible options.) Bode plots(Appendix B) are used to display the overall char-acteristics of all of the loop elements except KEA.With performance objectives and stability require-ments in mind, a strategy for closing the loop isdeveloped and a tentative gain characteristic isplotted to define the goal for the entire loop. Therequired KEA characteristic (Appendix B) is thendeduced from the difference between the Bodeplot of the overall loop goal and the plot of theknown loop elements without KEA.

Limitations on crossover frequency:


Figure 4. – Vector Relationships at Crossover

Achieving a high fC is a worthwhile objectivebecause the system can respond more rapidly tominimize the effects of high frequency and tran-sient disturbances. In a purely linear feedbackloop, fC is limited by cumulative phase lags in var-ious system elements. These phase lags inevitablyincrease with frequency in a manner that oftenvaries unpredictably. Compensation becomesimpossible, forcing the designer to set fC at a fre-quency where the phase lags are still manageable.

In switching power supply loops, an additionalimportant limitation occurs. Sampling delays inher-ent in any switched system introduce additionalphase lags that force the crossover frequency tobe well below the switching frequency. This will bediscussed later.

Transient Response:Transient behavior, in the time domain, is pre-

dictably related to the shape of the loop frequencydomain characteristics as shown in the Bode plot.

A power supply can function without the help ofa feedback loop. The duty cycle could be adjustedmanually to the value that would provide thedesired VOUT. But without feedback, even smallchanges in VIN or IOUT (the usual disturbances ina power supply application) would send VOUTcareening out of spec. With a functional feedbackloop, when an ac disturbance at a specific fre-quency is introduced, the open-loop gainmagnitude at the frequency of the disturbancedefines how much the output disturbance isreduced compared to what would have occurredwithout feedback.

Figure 5a is the Bode plot of a loop having thegain characteristic of a single pole (–1 slope,20dB/decade). A crossover frequency of 10kHz isshown, with the open-loop gain rising to 1000 at10Hz. The gain shown at each frequency indicatesthe amount by which the feedback loop will reducea disturbance at that frequency.

The gain vs. frequency plot can also be used toshow the reduction in the Fourier components of atransient disturbance, or how the loop will respondto the Fourier components of a step change in thecontrol signal. Fortunately, Fourier analysis is usu-ally not required to interrelate the Bode plot

characteristic, in the frequency domain, with thetransient response in the time domain. For exam-ple, the initial slope of the transient response to astep change is directly related to the crossover fre-quency.

The simple single pole characteristic of Fig. 5ahas an exponential characteristic with a time con-stant equal to 1/2πfC, as shown in Figure 5b. Inresponding to a step change, the initial slope wouldreach the final value in exactly one time constant(16µsec in this example), but like any exponential,it falls away to 63% of the final value at 1 time con-


Figure 5a. – Single Pole Characteristic

Figure 5b. – Single Pole Characteristic

stant and reaches 98% (2% error) in 4 time con-stants (64µsec). It takes a long time for the error todiminish ultimately to 0.1% because the loop gainreaches 1000 only for the Fourier componentsbelow 10Hz.

The single pole characteristic depicted inFigure 5 is extremely conservative. The –1 slopewith its 90° phase margin results in the exponentialcharacteristic which takes a long time to achievegood accuracy.

Figure 6 shows a less conservative approachwhich reduces the error much more rapidly. Twoactive poles provide a –2 slope below fC raisingthe gain below fC. This improves audio susceptibil-ity at these frequencies, and improves response tothe higher frequency Fourier components of a tran-sient disturbance or control signal. As shown inFig. 6a, the gain reaches 1000 at 300Hz, ratherthan at 10Hz. Note that at fC, the –2 gain slopetransitions to a single pole –1 slope. This is neces-sary because if the –2 slope continued above fC,the phase margin would be too small, resulting insevere underdamped oscillations at fC. The transi-tion to a single pole at fC results in an acceptablephase margin of 52°.

Figure 6b shows that the initial slope is thesame as in Figure 5b, because fC is the same inboth cases. But the transient response holds upbetter because the gain rises more rapidly at thefrequencies below fC. However, this results in 16%overshoot, which occurs at .58/fC (58µsec in thisexample).

Although the peak error with the –2 slopeexceeds the error at the same time with the –1slope, it subsequently diminishes more rapidly.What is more, the overshoot is actually beneficial insome situations.

For example, in a power supply applicationwith an inner current control loop and an outer volt-age control loop, assume Figure 5b shows thetransient response of the current control loop to astep change in load current at time 0. The load cur-rent rises immediately to the final value, but thesource current follows the transient response char-acteristic. Area “A” shows the charge deficit thatresults. The load draws this deficit from the output

filter capacitor, whose voltage sags as a result.Ultimately, the output voltage is restored and thecharge deficit made up only because the voltageloop responds to the voltage sag and calls forsource current temporarily greater than the finalvalue. However, this voltage loop interventiontakes considerable additional time.

Figure 6b shows that with two active poles, notonly is the charge deficit “A” reduced, but the over-shoot results in a charge excess “B” which cancelsall or part of the charge deficit immediately, without


Figure 6a. – Two Pole Characteristic

Figure 6b. – Two Pole Characteristic

requiring voltage loop intervention.

Switching Power Supply LoopsPower Circuit Design:

Just as the power supply is often the step-childin the design of the complete system, the controlloop is often the step-child in the design of thepower supply. The power handling circuit topologywith its associated components is the most signifi-cant portion of the control loop design, causingmost of the problems and complexity. The powercircuit is usually defined first, attempting to imple-ment system requirements in the most cost-effective way, with little consideration given to con-trol loop closure. The control loop design usuallymust adapt to a predefined power circuit.

Before proceeding with the control loop it isnecessary to examine some of the power circuitchoices that must be made. This is a difficult sub-ject to organize, because of the complexinteractions between these choices.

Choices:• Power Circuit Topology

• Control Method

• Transformer Turns Ratio

• Switching Frequency

• Filter Capacitor

• Filter Inductor

Considerations:• Cost

• Size/Weight

• Efficiency

• Noise

Switchmode Topologies:In the basic buck, boost and flyback power cir-

cuit topologies, shown in Figure 7, the inductor isthe element which transfers power from the input tothe output. (In the unique Cuk converter — a dualof the flyback — a capacitor is the energy transferelement.) The power switch is turned on and offduring each switching period by a Pulse WidthModulator (PWM). The duty cycle, D, (the percent-age of time the switch is ON) is the basis for

controlling the output. An output filter averages the

power pulses to obtain a DC output with acceptableripple.

Continuous Current Mode (CCM):This operating mode occurs, by definition,

when inductor current flows continuously through-out the switching period. The CCM currentwaveforms, shown in Figure 8, apply to all threetopologies. But, referring to Figure 7, input and out-put currents differ for each topology because of thedifferent locations of the inductor, switch and diode.There are two operational states –Switch ON,when it carries the inductor current, or Switch OFF,when the diode carries the inductor current.

Under steady-state conditions, inductor volt-age VL must average zero during each switchingperiod. With only two states, a specific, rigid rela-


Fig. 7. - Basic Buck, Boost, Flyback Topologies

tionship exists between input voltage VI, outputvoltage VO and duty cycle D, a relationship that isindependent of load current and is unique for eachtopology:

Most switching power supplies are designed tooperate in the continuous mode, especially at high-er power levels, because filtering is easier andnoise is less. Boost and flyback circuits operated inthe CCM have a unique problem — their controlloop characteristic includes a right half-plane zerothat makes loop compensation very difficult.

Discontinuous Current Mode (DCM):As shown in Figure 9, the discontinuous induc-

tor current mode occurs when the inductor current,flowing through the diode, reaches zero before theend of the switching period. The diode prevents thecurrent from continuing in the negative direction.Thus, the inductor current remains at zero until the

switch turns on at the beginning of the next switch-ing period. This zero current interval is a thirdoperating state in addition to the two that exist withCCM, and the additional degree of freedom thatthis provides destroys the rigid VI, VO, and D rela-tionship. With DCM operation, the small signal gainof the power circuit is much less than in the contin-uous mode, and DCM gain varies considerablywith load.

However, the DCM control characteristic issimpler, especially with the boost and flybacktopologies because the right half-plane zero doesnot exist. For this reason, the flyback topology isoften used in the discontinuous mode at low powerlevels where noise and filtering problems are notas severe.

The Pulse Width Modulator controls the dutycycle of the power switch — the fraction of timethat the switch is ON during each switching period.


Fig. 8. - Continuous Mode Waveforms

Fig. 9. - Discontinuous Mode

The ON/OFF action of the power circuit is aver-aged and filtered to provide a dc output. The outputmagnitude is related to the duty cycle, D, thus thepulse width modulator (PWM) provides the basisfor control and regulation of the output.

There are many varieties of pulse width modu-lators: Fixed frequency - variable duty cycle, FixedON-time (Variable Frequency), Fixed OFF-time(VF), Hysteretic (VF), The choice of PWM methodsignificantly affects power circuit behavior andsmall-signal characteristics and thus on the strate-gy for closing the feedback loop.

This paper considers only fixed frequencyPWM methods, which are used in the great major-ity of control ICs. Fixed frequency operation is

preferred because it permits the switching frequen-cy to be synchronized with other power supplies ina system, or with video terminal horizontal sweepfrequency, to prevent spurious beat frequenciesand other undesirable effects. Also, fixed frequen-cy control loops have simpler relationships whichare much easier to understand and optimize.

Fixed frequency PWMs function on the basis ofa latching comparator as shown in Figures 10 and11. (Latching prevents spurious reset due tonoise.) A control voltage, Vc, (usually the amplifiederror signal from the controlled output) is comparedto a fixed frequency linear sawtooth ramp, Vs. Thecomparator output provides fixed frequency pulsesof variable duty cycle which drive the power switch-ing transistors. The duty cycle D of the powerswitch conduction is thereby controlled by varyingVC according to the relationship shown in Eq. 3.(D, VC, VS are dc values, d, vC are small-signal acor incremental values.)

D = ; d = (3)

The PWM waveforms of Fig. 11 can beobserved only in very low bandwidth loops. In ahigh-performance loop with fC near optimum, con-trol voltage vC is not flat, as shown, but has asuperimposed triangular waveform (derived frominductor ripple current) that approaches the magni-tude of sawtooth voltage VS. The superimposedtriangular waveform modifies the duty cycle rela-tionship of Eq. 3, and can also cause subharmonicoscillation. This will be discussed later. Until then,the idealized waveforms of Fig. 11 will be used.

Modulator Phase Lag:Virtually all fixed-frequency PWM control ICs

use the simple comparator method shown in Figs10 and 11. The output pulse is terminated accordingto the instantaneous value of the feedback controlvoltage at the moment of pulse termination. This“naturally sampled” method of pulse width modula-tion ideally results in zero phase lag in the modulatorand in the converter power switching stage.(1) Inpractice, however, comparator delays and turn-offdelays in the power switch will cause a phase lag

vCVS

VCVS


Figure 10. - PWM Comparator

Figure 11. - PWM Waveforms

directly proportional to the delay time, td, and signalfrequency, f, according to the relationship:

øm = 360tD/T = 360tDf (4)

This additional phase lag reduces the phasemargin at the unity gain crossover frequency andtheoretically may contribute to control loop instabil-ity. However, the additional lag is usually negligible.For example, at an fC of 25kHz, consistent with fS= 200kHz, a turnoff delay of 0.4 µsec in the IC andthe power switch causes only 3.6° additional phaselag, reducing phase margin by that amount.

Most control ICs have additional “housekeep-ing functions” such as UVLO - UnderVoltageLockOut, HVLO - HighVoltage LockOut, and SoftStart, which are not discussed in this paper as theyare not directly relevant to control loop design.

Design Relationships –Buck-Derived Topologies:

In addition to the basic buck regulator, trans-former-coupled buck-derived topologies includethe single-ended Forward Converter and a varietyof push-pull converters: Center-tap, Full Bridge,and Half-Bridge.

The basic relationship governing the power cir-cuit of all buck-derived topologies operated withcontinuous inductor current is:

VO = VID; vO = VId (5)

VImin = VO/Dmax (6)

Duty Cycle Range:It is theoretically possible for the basic buck

regulator and its push-pull transformer-coupledderivatives to utilize the full 0 to 1 duty cycle range,but D close to 1 is best, as it results in the lowestprimary-side current and lowest secondary volt-ages. (The boost topology functions mosteffectively with D close to 0, the flyback with Dclose to 0.5.)

As shown in Eq. 6, for the buck regulator, theminimum VI at which the circuit can function isdefined by DMAX. In transformer coupled topolo-gies, the minimum VI defines the transformer turnsratio.

DMAX can never reach 1 because of practicallimitations. Some of these limitations are: turn-onpropagation delays and switch delay & rise times,resonant transition times, and reset time for thecurrent sense transformer, if a CT is used. DMAX istypically limited to between 0.85 – 0.95. Any appli-cation involving a transformer must provide time toreset the transformer core – the reverse volt-sec-onds must equal the forward volt-seconds to getthe flux back to the starting point. Push-pull circuitsautomatically reset the core by driving it in oppositedirections during successive switching periods.The Forward Converter has the most serious prob-lem – it is driven in only one direction, and thesubsequent voltage reversal required for core resettypically equals the time driven in the forward direc-


Fig. 12. - Forward Converter

tion, thus limiting DMAX to less than 0.5. Thismeans that the minimum VIN referred to the sec-ondary side must be greater than twice VOUT.

Minimum Duty Cycle:Likewise, DMIN cannot reach zero. Once the

switch is turned ON to initiate a power pulse, theswitch is committed to stay ON for a certain mini-mum time. This minimum pulse width at a fixedswitching frequency equates to a minimum dutycycle. Some of the items that contribute to DMINare: Turn-off propagation delays and switch delay& fall times, resonant transition times, and noiseblanking (which disables the PWM comparator fora short time after turn-on to prevent a spuriousnoise pulse from causing premature turn-off).

In normal operation, D is always much greaterthan zero. Certain events will cause D to approachzero temporarily, such as when load current dimin-ishes at a rate faster than inductor current candecrease (max diL /dt = VOUT /L). In this situationthe DMIN value attained is not critical. The DMINvalue does become critical when the output isshort-circuited. When VOUT is pulled down to zero,and VIN is at its normal value, then D must bebrought to zero to maintain control and keep thecurrent within the limit. This bleak situation isremedied by the output rectifier forward drop whichacts as a minimum VOUT. But when VIN is nearmaximum, and especially when VOUT is 28 V orhigher and the rectifier drop has less significance,the required D value may still be less than DMIN.This is then a serious problem. Many control ICsalways initiate an output pulse at the beginning ofeach clock cycle, relying on current limiting to turnoff the power pulse quickly under overload or shortcircuit conditions. But “quickly” may not be quickenough.

The solution employed in many modern ICs isto skip pulses, or shift the frequency downward.Under overload conditions, if pulses are skippedentirely, the switching frequency effectively adjustsdownward. The minimum pulse width does not getsmaller, but D does become small enough to retaincontrol. Pulse skipping requires a control IC thathas the logic to completely inhibit switch turn-on ifcurrent exceeds the limit at the beginning of the

clock cycle.

Transformer Turns Ratio:First, the minimum input voltage referred to the

secondary side, min VI, is determined. Using Eq. 6,calculate min VI based on DMAX, then add full loadswitch, diode and IR drops. Allow for some addi-tional voltage across the inductor, or its currentcannot increase rapidly under min VI conditionswhen necessary to keep up with a load currentincrease. With this adjusted min VI value, and theminimum source voltage, VIN, the turns ratio canbe calculated:

VI = ; (n = )

In this paper, to minimize the complexity of thecontrol loop relationships, all circuit values arereferred to the secondary side. Thus, turns ratio nand actual input source VIN do not appear, only VI,the input voltage referred to the secondary.

For low voltage outputs, accuracy is improvedby adding the output rectifier forward drop to theactual output voltage, using this “corrected” valueof VO in the design equations.

Inductor Ripple Current is inversely propor-tional to inductance value. In buck-derivedtopologies a small inductor with large ripple currenthas these disadvantages: (1) a bigger output filtercapacitor is required, (2) large ripple dictates alarge minimum load current to avoid discontinuousoperation. (This disadvantage is overcome byusing Average Current Mode Control.)

Advantages of the smaller inductor are: (1)Lower size and cost, (2) inductor current canchange more rapidly in response to a sudden loadchange and (3) together with the larger CO,reduces over/undershoot occurring with a largestep load change.

The inductance value obviously plays a keyrole in the control loop design.

Filter CapacitorsOutput filter capacitors are almost certainly the

most troublesome element in the control loop. Intheir power filtering role, they typically absorbAmperes of ripple current and hold the output rip-ple voltage to a small fraction of a Volt. The low

NpNS

VINn


impedance required usually dictates the use ofelectrolytic capacitors. Ceramic capacitors are notusually considered practical unless the switchingfrequency is well over 500kHz and/or with high out-put voltages.

Electrolytic Capacitors – Series Resistance:

At the 50-400kHz switching frequencies main-ly used in today’s SMPS applications, electrolyticcapacitor impedance is determined by its seriesresistance, SR. As frequency is increased, whencapacitive reactance drops below series resis-tance, the impedance curve tends to flatten out atthe SR value. The frequency at which this occurs(the ESR zero frequency) is 1 to 10kHz forAluminum electrolytics, 10 to 60kHz for Tantalum.Almost all power supplies today switch at frequen-cies well above this. Electrolytic capacitors mustthen be selected and specified on the basis of theirseries resistance. The resulting capacitance val-ues are much greater than would be required if theSR were not dominant – often 100 times greaterwith aluminum electrolytics at 200kHz switchingfrequency.

At switching frequencies above fESR, theimpedance characteristic flattens out at the SRvalue, so that the same capacitor is requiredregardless of the frequency. Going to a higher fSdoes not change the filter capacitor or reduce itscost.

SR or ESR??Electrolytic capacitors have both series and

parallel resistance components. At low frequencieswhere capacitive reactance is large, the parallelresistance (leakage through the dielectric) domi-nates, and true series resistance (mostly in theelectrolyte) is negligible. Measurements taken on abridge cannot distinguish between actual paralleland actual series resistance. Bridge measure-ments lump both resistances together – the actualseries resistance plus the parallel resistance con-verted to its series equivalent. This combination iscalled “Equivalent Series Resistance”, or ESR. Atlow frequency (50-60Hz), the converted parallelresistance dominates. Capacitive reactance, thefulcrum of the parallel to series conversion, varies

inversely with frequency, which makes ESRappear to vary inversely with frequency squared.

In a switching power supply application, theactual series resistance SR is of key importance,but the parallel resistance is of little or no signifi-cance (except possibly for reliability concerns). SoESR data is very misleading until the frequency ishigh enough that the converted parallel resistancebecomes smaller than the true series resistance.At higher frequencies, the ESR characteristic flat-tens out at the true SR value. Capacitors intendedfor high frequency application are measured andspecified at 100kHz which reveals the true seriesresistance. Low frequency ESR measurementsare totally irrelevant. However, bowing to commonusage, this document uses “ESR” to refer to theactual series resistance evident at high frequency.

Capacitance and ESR variation:The impedance transition from capacitive (with

–1 slope) to resistive (with 0 slope) puts a zero inthe control loop Bode plot. The frequency at whichthis occurs is called the ESR zero frequency, fESR.

fESR = (7)

The problem with aluminum electrolytics in thecontrol loop is that fESR is usually near or below thedesired crossover frequency. ESR variation caus-es a corresponding fESR variation. This results invariable loop gain and variable phase margin,making it difficult to cross over above fESR. If thesupply must operate over a wide temperaturerange, the large ESR variation with temperaturecan make it impossible, forcing the design to crossover at a low frequency (probably below 1kHz).

Capacitance variation is quite small, so thatbelow fESR the characteristic is stable and pre-dictable. Data from Panasonic on the FA SeriesAluminum Electrolytics:

Capacitance:20°C distr.: 100%–120% of spec. value+10% @ 105°C; –10% @ –55°C

ESR:20°C distr.: 60% – 85% of specified max.

1


x.33 @105°C; x2 @ –10°C; x12 @ –55°C

A Little Trickery:Electrolytic capacitors with the same case size

and manufacture but with different voltage ratingsand capacitance values all tend to have the sameESR. The dielectric oxide thickness which deter-mines the voltage vs. capacitance tradeoff is“formed” late in the manufacturing process. Thedielectric thickness does not significantly affectESR. For example, in a 16x20 mm case size,Panasonic FA series 10V, 3300µF and 50V, 680µFcapacitors have the same ESR: 25 mΩ max.

For SMPS ripple filtering, electrolytic capacitorselection is based entirely on the ESR require-ment. A 5V output requiring 25 mΩ max. ESRcould use either of the above capacitors. The3300µF, 10V capacitor puts a 2kHz ESR zero intothe control loop, But the 680µF, 50V puts the ESRzero at 10kHz. Thus, if it is necessary or desirableto make the loop gain crossover below fESR toavoid the problems caused by ESR variability andunpredictability, the smaller capacitance value withthe higher fESR is clearly the better choice.

There is a downside to this choice, however. Inthe continuous conduction mode, the filter induc-tance prevents the inductor current fromresponding rapidly to a step load current change.The output filter capacitance (not the ESR)absorbs the load current change while the inductorcurrent catches up. The extravagantly excessivecapacitance value necessary with electrolyticcapacitors does become very useful by providing avery low output surge impedance – it “holds thefort” until reinforcements arrive. The faster controlloop does nothing to help in this situation – this isa large-signal limitation dictated by inadequateinductor current slew rate, during which the controlerror amplifier is driven to its limits and the loop istemporarily open and non-functional.

Ripple Current Rating:AC ripple current flowing through the capacitor

ESR generates heat. Temperature rise and reliabil-ity considerations are the basis for an rms currentlimit. The low ESR capacitors normally used inSMPS applications have rms current ratings that

are usually adequate for their purpose. To calculatethe rms equivalent of the peak-peak triangularinductor ripple current waveform:

Irms = (8)

Capacitor Inductance:The path for ac current flow within an aluminum

electrolytic capacitor is quite long, simply becauseof their relatively large size. This results in largerseries inductance than other capacitor types. Theimpedance characteristic is determined by ESRabove fESR, but at approximately 500kHz, theimpedance rises because the series inductancebecomes dominant. Other capacitor types thenbecome more advantageous.

Tantalum Capacitors:Characteristics are similar to aluminum elec-

trolytics, but tantalum electrolytics are better: TheESR zero frequency is 5-10 times higher than alu-minum, making it easier to achieve greater loopbandwidth, with improved dynamic response. (ButESR remains the impedance determining factor forripple filtering at SMPS switching frequencies.) TheESR has a much lower temperature coefficient,making tantalum much better suited to military andother wide temperature range applications. Size ismuch smaller for the same ESR. The smaller sizealso results in lower inductance, enabling opera-tion up to 1MHz.

The downside for tantalum capacitors is sub-stantially higher cost for the same ESR required.Also, the lower capacitance value associated withthe necessary ESR (the reason why fESR isgreater) results in a higher output surge imped-ance, so the output does not stand up as well to alarge step load change.

Ceramic Capacitors:Radically different from the electrolytics, ESR

is negligible — an ESR zero frequency doesn’texist. Impedance is not determined by ESR, but bycapacitance (or by inductance at frequenciesabove 1-2MHz). Small size, surface mount pack-aging keeps inductance the lowest of all thealternatives.

But the cost of obtaining the necessary capac-

Ipp

2 3


itance with ceramic is excessive at switching fre-quencies below 500kHz. Even at higherfrequencies, to achieve the required capacitance ata reasonable cost, high K dielectrics are used. Thelarge temperature coefficients of these dielectricsmake it difficult to optimize the loop over a widetemperature range. Also, the C value required toobtain the required ripple reduction is much lessthat the capacitance obtained by default with theelectrolytics. This results in relatively high outputsurge impedance and little tolerance for step loadchanges.

Polymer Aluminum Electrolytics:Similar to ceramics, these new arrivals in the

capacitor catalog have negligible ESR, small size,low inductance, but high output surge impedance.But here the similarity ends. Available capacitancevalues are not only much greater than ceramics,but capacitance distributions are tight, and temper-ature coefficients are low. Polymer aluminumelectrolytics approach the ideal for filter capacitors.

The limitations of the existing devices are: Lowvoltage ratings:16V max. One small size surfacemount package available: (8mm x 5.3mm x 3.3mmhigh) limits C values to the range of 6 - 33 µF.Higher cost unless the switching frequency is highenough to overcome this.

In a 200kHz power supply, one of the present-ly available polymer aluminum electrolytics willhandle the filtering of a 5V, 25A buck regulator out-put at perhaps twice the cost (in Jan’96) of acompetitive (but much larger) aluminum electrolyt-ic. At fS of 400kHz, they are probablycost-competitive.

Panasonic states that their polymer electrolyt-ics are now being used as output filters in switchingpower supplies. If these devices fulfill their promiseand are made available in larger sizes with greatercapacitance values and/or if switching frequenciescontinue to rise, perhaps they will some day cometo dominate this application.

Switching Frequency:The rationale for the inexorable rise in SMPS

switching frequency over the years has beenreduced cost as well as reduced size and weight.The smaller magnetic components made possible

by raising the frequency have helped the most toachieve these goals. But at frequencies above500kHz, core losses in today’s best magneticmaterials (1996) rise to the point where this trendslows down and then reverses — the magneticcomponents start to get larger. The filter capacitormight be expected to get smaller with increasedfrequency, but it does not because its impedancedepends on ESR, not capacitance – until the fre-quency is reached where ceramic capacitorsbecome economically feasible. At higher switchingfrequencies, there is more high frequency noisegenerated, but less low frequency noise, so thatconducted EMI is easier and less costly to filter.The control loop bandwidth can of course be raisedproportional to fS, but this is seldom part of therationale for increased frequency.

The obstacles to achieving higher switchingfrequencies at reduced cost all seem to boil downto one thing: increased losses, which lower effi-ciency and raise the cost of heat removal. Ongoingimprovement involves circuit topologies and innov-ative techniques such as the recently popular“resonant switching transitions” which reduce loss-es and noise. Improved high frequency magneticmaterials are needed, as well as faster semicon-ductors. New concepts in the “wiring” and layout ofhigh frequency circuits and magnetic componentsare needed to reduce parasitic inductances whichincrease losses, impair regulation, and radiateEMI.

Control MethodsVoltage Mode Control:

The earliest control method, implemented inmost older control IC’s. This was discussed previ-ously (refer back to Figs. 10 and 11). The fixedamplitude sawtooth ramp is usually taken from thecontrol IC’s clock generator. VMC disadvantagesare: (1) No voltage feedforward to anticipate theaffects of input voltage changes. Thus, slowresponse to sudden input changes, poor audiosusceptibility and poor open loop line regulation,requiring higher loop gain to achieve specifica-tions. (2) In continuous mode regulators, providesno help in dealing with the resonant two pole filtercharacteristic with its sudden 180° phase shift.


Control changes must propagate through thesetwo filter poles to make a desired output correction,resulting in poor dynamic response. While VMCmight appear to be less costly because there is nocurrent loop with its need for current sensing, butcurrent limiting is almost always required, and thisrequires the current to be sensed. With CurrentMode Control, current limiting is automatic and“free”.

(Peak) Current Mode Control:This control method (CMC) also controls the

duty cycle by comparing the control voltage to afixed frequency sawtooth ramp, but the ramp is notderived artificially from a ramp generator, as with

Voltage Mode Control. The ramp is actually theinductor ripple current, as it rises while the switch isON, translated into a voltage by a current senseresistor. This ramp, representing the inductor cur-rent, is fed back to the PWM comparator, formingan inner current control loop. When the currentrises to the level of the control voltage, the switch isturned off. The control voltage (which is the ampli-fied output voltage error), thus defines the peakinductor current. The outer voltage control loop pro-grams the inductor current via the inner loop whilethe current loop directly controls the duty cycle .

In the forward converter shown in Figure 13,the inductor is on the secondary side. But since the


Figure 13. - Peak Current Mode Control

control IC is on the primary side, it is easier tosense primary-side switch current. This worksbecause the switch current is the inductor current(while it is rising) divided by the transformer turnsratio. This eliminates the problem of bringing thecurrent information across the isolation boundary.

The advantages of CMC are profound. Most ofthe problems of Voltage Mode Control are elimi-nated or reduced. CMC has inherent voltagefeedforward and responds instantaneously to inputvoltage changes. The inductor pole is now locatedinside the current loop. Instead of the two pole sec-ond order filter of the VMC loop the outer voltageloop now has a single pole (the filter capacitor),greatly simplifying loop compensation. The capac-itor ESR with its variability remains in the voltageloop.

The CMC closed loop is part of the outer volt-age control loop. The CMC closed-loopcharacteristic approaches an ideal transconduc-tance amplifier. Closed-loop gain is flat up to itsopen-loop crossover frequency, which is optimally1/3 to 1/6 of the switching frequency. At the CMCcrossover frequency, its closed-loop gain rolls offwith a –1 slope, adding a second pole into theouter voltage loop, but at a much higher frequencythan the capacitor pole.

Peak current mode control does have its ownset of problems: Average current is what should becontrolled, but peak is controlled instead. Thepeak-to-average error is quite large, especially atlight loads, and the voltage loop must correct forthis, which hurts response time. Open loop gain ofthe CMC loop is already quite low (5 - 10) in thecontinuous current mode, but when the load dimin-ishes to the point where inductor current becomesdiscontinuous, the CMC loop gain plummets andthe peak-to-average error becomes huge.Operation becomes unsatisfactory in the discontin-uous mode.

Subharmonic Instability:Switching power supply control loops are all

subject to subharmonic instability if the waveformsapplied to the two inputs of the PWM comparatordo not cross over each other at their points ofintersection. This instability is observed as a

tendency to oscillate (or a full-blown oscillation) atfrequency fS /2.

Figure 14 shows the subharmonic instability ina peak CMC loop. Normal operation is shown bythe solid triangular waveform labeled iL. This volt-age, representing the inductor current, is applied toone side of the comparator. The switch is turned onby a clock pulse, and iL rises until it reaches con-trol voltage VC at the other comparator input. Theswitch turns off, and the current decreases until thenext clock pulse occurs. (It does not matter of thecurrent downslope is observed through the currentsense resistor—referring to Fig.13—becauseswitch turn-on is by the clock, and not dependenton the current level.)

Using perturbation analysis, a small deviation,∆, is assumed in the inductor current. The deviatedwaveform has the same slopes as before, becausethe voltages across the inductor have not changed– just the initial current has been changed. Thedash line in Fig. 14 reveals the instability. In a sta-ble system, the perturbation gets smaller everyswitching period.

True subharmonic instability can be eliminatedusing a slope compensation technique, discussedbelow. Sometimes, what appears to be subhar-monic instability is really noise at the comparatorinput. When the clock pulse turns the power switchon, much noise is generated. A noise spike at thecomparator input can easily turn the switch offimmediately, effectively causing one or more entireswitching period to be skipped.

Latching Comparator:When the voltages at the PWM comparator

inputs intersect, and the power switch is turned off,the comparator must be designed to latch in that


Figure 14. - Peak CMC Subharmonic Instability

state until reset by the next clock pulse. Otherwise,if the waveforms trajectories diverge withoutcrossing over, as in Fig. 14, the switch will turnback on immediately. Even if the waveforms docross over, a noise spike could cause the com-parator to reset and turn on the power switchprematurely. The latching comparator preventsthese undesired occurrences.

Slope Compensation:Subharmonic instability is eliminated simply by

forcing the waveforms at the two inputs of the com-parator to cross over each other at their points ofintersection. This can be accomplished by addingan artificial ramp to one of the comparator inputs.Figure 15 shows an optimum slope compensationramp added to the control voltage comparator input,labeled “VC + VS”. The optimum ramp, as shown,causes the two waveforms at the comparator inputsto coincide during the interval when the switch is offand the inductor current is decreasing, rather thanactually cross over. This is ideal, because, asshown, a perturbation is erased in the very firstswitching period after its occurrence!!

The compensation ramp reduces the currentloop gain. If the ramp slope is increased further sothat the waveforms actually cross over, the systemis stable but the gain is reduced below optimum(and it actually takes longer for the perturbation tobe erased). Optimum is when slopes coincide, or

match.The crossover frequency is directly related to

the gain. Middlebrook has shown that for a buck-derived regulator with optimum slopecompensation, the crossover frequency is:

fc = (9)

Thus, depending on duty cycle D, fC rangesfrom 1/3 to 1/6 of fS.

Although Fig. 15 shows a ramp with a negativeslope added to the control voltage waveform(because it is easier to visualize), in practice a pos-itive ramp slope is usually added to the inductorcurrent waveform, simply because a positive rampis available in the IC’s clock generator.

It can be argued whether subharmonic instabil-ity results from the sampling delays inherent in aswitched system, or whether it is just a geometryproblem. Certainly this instability can either be gen-erated or corrected by adding a purely artificialramp, unrelated to the loop elements.

Linear models have been attempted so that theeffects of subharmonic instability can be includedin frequency domain analysis. However, theseempirical models lose sight of the underlyingcauses and are blind to the slope manipulationtechniques which can optimize bandwidth withoutinstability. The underlying causes of instability arebest demonstrated and corrected in the timedomain, observing and appropriately modifying thewaveform trajectories on opposite sides of thePWM comparator.

Average Current Mode Control:The deficiencies of the Peak CMC loop basi-

cally relate to its low internal loop gain. AverageCMC, as shown in Figure 16, eliminates this prob-lem by adding an error amplifier to the current loop(in addition to the amplifier in the outer voltageloop). Inductor current is sensed through a resistor.The resulting voltage is compared with voltageVCP which sets the desired inductor current. Thedifferential, representing the current error, is ampli-fied by CA, the current error amplifier. The CAoutput is compared to a sawtooth ramp taken fromthe IC clock generator to determine the duty cycle

fs


Figure 15. - Peak CMC with Slope Compensation

– the same technique commonly used with VoltageMode Control.

Figure 17 shows the comparator voltage wave-forms when the E/A gain is optimized using theslope matching criteria discussed below. Note thatamplifier CA inverts the error signal, so the trian-gular waveform VCA is an upside-downrepresentation of the inductor ripple current. Therising portion of the VCA waveform (coincident withsawtooth waveform VS) represents falling inductorcurrent, when the switch is OFF. As Figure 17shows, where the waveforms intersect (near themidpoint of the sawtooth ramp) and the switchturns OFF is where the inductor current is at itspeak (the waveform is inverted). Why is this calledaverage CMC if it really functions at the peak??Actually, average CMC when optimized is identicalin its behavior to peak CMC with all of its positive

attributes – it has the same crossover frequency,the same instantaneous response to a currentoverload, etc. But at frequencies below fC, wherethe peak CMC loop gain flattens out at a gain ofonly 5 or 10, the gain of the average CMC loopkeeps rising, ultimately to a gain of more than 1000if desired. This much higher loop gain at lower fre-quencies eliminates the peak-to-average error andenables the average CMC loop to function well atlight loads when the inductor current becomes dis-continuous.

Reference (2) describes Average CMC in detail.

Slope Matching:In the basic PWM system used with Voltage

Mode Control (Fig. 10 and 11), and with peak CMC(Fig. 14 and 15), the error signal applied to oneside of the comparator is usually thought of as a dclevel crossing over the sawtooth ramp, as shown inFig. 11. This is only true if the open loop band-width, fC, is extremely low — at least a factor of 10below optimum. As the error amplifier gain isincreased (and bandwidth along with it), the trian-gular inductor ripple current becomes evident atthe output of the error amplifier. In Figure 17, wheregain and bandwidth are optimum, the inductor rip-ple current (seen as vCA) has become quite large.Optimum error amplifier gain is achieved when theslopes of the two waveforms coincide as shown inFigure 17 during the interval preceding the nextclock pulse. In this case, it also happens to be the


Figure 16. – Average Current Mode Control

Figure 17. – Average CMC Waveforms

interval following switch turn-off when the inductorcurrent is falling (the amplifier inverts the wave-form).

Note that when the slopes coincide, the peaksalso must coincide. Also, a perturbation applied tothe VCA waveform is eliminated in the very firstswitching period, just like with optimum slope com-pensation with peak CMC (Ref. Fig. 15).

If the amplifier gain is increased beyond this opti-mum condition, two bad things happen:

(1) The triangular waveform VCA increases, mak-ing its positive peak exceed the positive peakof sawtooth VS. Depending upon the ICdesign, the E/A output may clamp VCA at avoltage not much larger than the VS peak. (Theamplifier should be designed to clamp at thislevel. Otherwise during large signal eventswhen the amplifier is “in the stops”, the E/A out-put would rise substantially, increasing the timerequired to recover from such an event.) If thewaveform becomes clamped, the gain will sud-denly appear to drop. Slope matching isconsistent with the vC waveform not exceedingthe sawtooth VS.

(2) Even if clamping does not occur, the increasedtriangular amplitude means the waveforms donot cross over or coincide after the switch turnsoff, and a tendency toward subharmonic insta-bility begins.

It should be obvious that slope matching andslope compensation are closely related. In factthey are two sides of the same coin – the problemsare identical, the optimization criteria are identical,and the benefits are identical. The only differenceis that with Peak CMC, the triangular voltage rep-resenting inductor current is fixed, and a sawtoothcompensating ramp is introduced whose magni-tude is adjusted to obtain coincident slopes. WithAverage CMC, the sawtooth ramp is fixed, and thetriangular voltage representing inductor current isadjusted (by varying the E/A gain) to obtain coinci-dent slopes. In both systems, when the slopes aremade to coincide, their crossover frequencies willnot only be optimum, they will be the same.

How to Implement Slope Matching:The inductor current downslope is translated

into a voltage downslope by a current sense resis-tor, RS. The gain of the Current amplifier, CA, (atthe switching frequency fS) is set so that the slopeat CA output equals the ramp slope at the otherinput of the PWM comparator. For buck and boosttopologies, the inductor current downslope is VO/L.The ramp slope is VS/TS, or VSfS. Therefore:

GCA = VSfS; GCA = (10)

Slope Matching with Voltage Mode:The slope-matching criteria for loop bandwidth

optimization applies not only to the Average CMCloop, but to any system that uses a similar PWMtechnique. For example, the single-loop VoltageMode Control described earlier benefits from thesame strategy. With VMC, an electrolytic outputcapacitor appears resistive at fS, so the triangularinductor current waveshape appears across thecapacitor ESR, just as it does across the AverageCMC current sense resistor. The voltage erroramplifier gain is adjusted until its output slope coin-cides with the sawtooth ramp slope. Thecomparator waveforms look exactly like the Avg.CMC waveforms in Figure 17. The result is that,when optimized by slope matching, the lowly sin-gle-loop Voltage Mode Control not only has (a) thesame crossover frequency as Current ModeControl,[3] the optimized VMC loop has (b) con-stant gain, independent of VIN. Even moreimportantly, the optimized VMC control loop (c)responds instantly to changes in VIN, just likeCMC. The advantage of CMC remains that it iseasier to implement, because the frequencydependent elements are apportioned between thetwo loops, thus are easier to deal with.

Slope Matching Effect on PWM Gain:It was not recognized until recently that the

optimized triangular waveform applied to the PWMcomparator causes a change in the PWM gaincharacteristic. The relationship given in Eq. 3 iscorrect for low-gain, low-bandwidth loop whoseamplified error signal appears as a dc level, as

VSfSLVORS

VORSL


shown in Fig. 11. But when the E/A gain is opti-mized, the slope of the initial portion of thetriangular waveform, when the switch is ON, variesas a function of duty cycle. As shown in Figure 18,when the slope is relatively flat with D almost 1, anincremental change in the control voltage, vC,causes a large incremental change in the dutycycle, d. When D is near zero, the initial slope issteep, so the same incremental vC change causesa much smaller change in d. By inspection, it canbee seen that with slope-matched waveforms, thePWM “gain” is directly proportional to the dutycycle D:

d = D (11)

Whereas the PWM characteristic with a low-bandwidth “flat” control voltage from Eq. 3 does notchange with D.

This modified PWM characteristic was notknown at the time several earlier papers onAverage CMC were written, and some of their gainexpressions are in error. For example, with a Buck-derived regulator, duty cycle D = VO/VI. InReference (2), “Average Current Mode Control ofSwitching Power Supplies,” Eq. (2), the expressionfor the power circuit plus PWM gain is:

= Ref. (2), Eq.(2)

Using the modified PWM characteristic in Eq.10 above, instead of Eq. 3, the power circuit plusPWM gain becomes:

= corrected Ref. (2), Eq.(2)

Replacing VIN by VOUT may seem like a minorcorrection, but VIN changes, VO is fixed. Thus inthe optimized version, gain is constant, with theoriginal version, gain varies directly with VIN.

Also, in Reference (2), Eq. (3) changes:

fc = becomes: fc = (12)

With the loop gain and crossover frequencynow constant and independent of VIN, closing thecurrent loop and the outer voltage loop becomemuch easier.

Interaction in Two-Loop Systems:In a two-loop system, the inner current control

loop determines the response to input voltagechanges, while the outer voltage control loop deter-mines response to load current change. Theseloops do interact, especially if their respectivecrossover frequencies are close to each other.

If both loops must be optimized for fastresponse, interaction is involved in the slope-matching process. There is only one PWM in atwo-loop system. The triangular waveform vCA atthe output of the current error amplifier CA actual-ly has two components – the inductor ripple currentseen across the current sense resistor and fedthrough CA, and the inductor current seen acrossthe output capacitor ESR and fed through voltageerror amplifier VA and CA. These two triangularwaveforms are in-phase. VA and CA gains must beadjusted so the combined slopes match the saw-tooth waveform, but this can be accomplished indifferent ways. For example, in a buck regulatorwith a single loop optimized by slope matching, fSequals fC/2π. But with two loops, if VA and CAgains are adjusted so that each loop contributes 1/2

fs2š

fs2šD

VOsL

RSvRSvCA

VINRSvRSvCA

vCVS


Figure 18. – Modulator Gain vs. Duty Cycle

of the total slope-matched triangular waveform,each will have fS equal to fC/4π. However, if thecurrent loop has more gain and the voltage loop less, the current loop contributes more than 1/2 of the total triangular waveform so its crossover frequency fCI will be greater than fCV ofthe voltage loop.

The closed-loop gain of the current loop is partof the open-loop gain of the voltage loop. The cur-rent loop closed-loop gain rolls off at its crossoverfrequency, fCI, adding an additional –1 slope to thevoltage loop above fCI. It is best to have fCV belowfCI to minimize this interaction.

The Right Half-Plane Zero:In the boost and flyback topologies, the output

is driven through a diode, as shown in Figure 7.The inductor current flows to the output only whenthe power switch is off and the diode conducts. Ifload current increases, the duty cycle must beincreased temporarily to make the inductor currentrise. But operating in the continuous inductor cur-rent mode, when D is increased the diodeconduction time decreases, before the slowly risinginductor current has time to change. The result isthat the average diode current decreases at first,then as inductor current rises, the diode currentultimately reaches to the proper value. This action,where the average diode current must actuallydecrease before it can finally increase, results inthe small-signal phenomenon known as a righthalf-plane zero.[4]

ωRHPZ = (13)

A “normal” zero occurs in the left half of thecomplex s-plane, and has a gain characteristic thatrises with frequency, with 90° phase lead (+1slope). The right half-plane zero also has a risinggain characteristic, but with a 90° phase lag (-1slope). This combination is almost impossible tocompensate within the control loop, especially asthe RHP zero frequency varies with load current.So most designers give up and cross over the volt-age control loop below the lowest RHP zerofrequency. One argument in favor of Average

CMC is that it can operate in the discontinuousinductor current mode, which permits the use of asmaller inductor value. This not only saves size,weight and cost, it raises the RHP zero frequencyto permit greater bandwidth for these topologies.

Loop Design Procedure:Normally, the power circuit topology is decided

upon and the power circuit values are determined,based on the application requirements, before con-trol loop design begins. Occasionally, problemsencountered in the control loop design processmay force a rethinking of these power circuit deci-sions. The steps in the control loop design processwill generally proceed as follows:(1) Define the control loop strategy and plot the

tentative goal.

(2) Plot the known part of the loop.

(3) Define the crossover frequency, fS.

(4) Try to meet the goal — Define and plot theerror amplifier and overall loop characteristics.

Examples given in Appendix C should help toclarify this process.

Step 1. Define the Control Loop Goal andStrategy:

Based on application requirements for line andload regulation and transient response, output filtercapacitor type. Define and crudely plot a tentativegoal for the overall loop characteristic. The idealgoal is shown in Fig. 6a (two active poles belowcrossover, one above). Several strategies for prac-tical situations are outlined below. Implementationis shown in Appendix C.

Strategy #1 – The Easiest but not the Best: Fora buck-derived topology with aluminum electrolyticcapacitor. Line and load variations are small and/orslow. Use single loop Voltage Mode Control. Crossover well below 1kHz, don’t worry about slopematching. The only problem to deal with is that theloop gain varies with VIN. The result of this shortcut stabilization method is poor dynamic response,but if this is acceptable, who can argue.

Strategy #2 — How to handle large stepchanges in load: Output regulation in the face of alarge step load change depends heavily on the out-put filter capacitor by itself, backed up by the

(1-D)2

DRLOAD

L


voltage control loop. In a two-loop system, the cur-rent loop does not provide any help in respondingto a load change. In this situation with a continuousmode buck-derived topology, it will take severalswitching periods for the inductor current to slew tothe new value (especially for a current rise at lowVIN). While the inductor current is slew-rate limited,the control circuit is non-functional because theamplifiers have been driven into their limits.

The salvation of this problem is an electrolyticoutput filter capacitor, especially an aluminum elec-trolytic whose C is huge because of the ESRrequirement. The aluminum electrolytic does sucha good job of “holding the fort”, that the voltageloop bandwidth does not need to be pressed to thelimit. Thus, the current loop can be designed withslope matching for optimum fC, and the voltageloop designed on a strictly linear basis to crossover at or below the capacitor ESR zero frequency.

Ceramic or polymer capacitors make a verypoor showing with large rapid load changes —ESR is negligible but the C value used to achievethe desired output ripple is orders of magnitudeless than an electrolytic. A really big help is tomake the inductor smaller and the capacitor bigger– lower the surge impedance -L/C . The smaller Lcan slew the current faster, the larger C will holdthe fort longer. The increased ripple current willraise the minimum load where discontinuous oper-ation begins, but Average CMC can cross themode boundary nicely.

Strategy #3 – Large ESR Variation: An auto-motive application must operate over a widetemperature range and must have rapid responseto input surges and load changes. Optimizing fC byslope matching, along with the input voltage feed-forward that slope matching provides, wouldprovide a satisfactory solution. However, an ESRvariation of 6:1 including initial distribution and tem-perature coefficient causes a 6:1 variation in loopgain and crossover frequency. The triangular ripplewaveform which is the basis for slope matchingvaries by the same amount.

In this difficult situation, it is best to use CurrentMode Control. The current loop does not containthe ESR, so it will be very stable and can be

designed with slope matching to optimize band-width and input transient response. The voltageloop should then be designed to cross over at alower frequency than the current loop. Then, thevoltage loop will not significantly affect slopematching, and the roll-off of the closed current loopwill be above the range of concern for the voltageloop. The voltage loop is definitely simplified, butthe ESR is still there. If the variable ESR zero is inthe vicinity of the desired fC, it may be necessaryto reduce fC to below the ESR zero frequency. Theresponse of the voltage loop will not be excellent,but the aluminum electrolytic’s huge C value willprobably handle this problem better than the bestcontrol loop, if the control loop gets knocked out ofaction by the inductor current slew rate.

The original single-loop VMC approach wouldbe much more workable with Tantalum electrolyt-ics, which have much smaller ESR temperaturevariation. If the frequency is high enough for eco-nomic viability, polymer capacitors might be worthconsidering.

As demonstrated above, many of the problemsencountered while developing a control strategylead back to the power circuit components or evento complete replacement of the original power cir-cuit topology. This is to be expected, but this isclearly an area where experience can help to makethe right choices the first time (or maybe the sec-ond time!).

Step 2. Plot the Known Part of the Loop:After the power circuit topology and the control

method have been at least tentatively defined, andthe power circuit values established according toapplication requirements, Make a Bode plot of theentire loop but not including the error amplifier,KEA. This plot must include the control-to-outputcharacteristic plus feedback KFB. The characteris-tic of the PWM, power circuit and filter must beknown – see examples in Appendix C. In a twoloop system, do the complete design of the innerloop first, before starting outer loop design.

Step 3. Define the Crossover Frequency:If slope-matching to optimize fC, the slope

matching process defines the E/A gain at fS. Thecrossover frequency will be optimum, but the spe-


cific frequency will not be know until the next step.If slope matching in a two-loop system, rememberthat each loop will contribute its share of the totalslope. The relative share contributed by each loopdetermines the relative crossover frequency ofeach loop. It is best to have the current loop con-tribute most of the slope. This will result in currentloop crossover frequency greater than the voltageloop which is desirable because the closed currentloop is contained within the voltage loop.

If fC is put at a frequency less than optimum toavoid problems, or just because there is no needfor high bandwidth and fast response time in thisapplication, then subharmonic instability will notoccur, and loop stability can be totally handled withBode plots. Steps 3 and 4 meld together. Again, intwo-loop systems, there is loop interaction. Theclosed current loop within the voltage loop adds apole to the voltage loop at the current loopcrossover frequency, so it is best to have the cur-rent loop cross over at a higher frequency than thevoltage loop.

Step 4: Try to Meet the Goal — Define the E/Aand Overall Loop:

Since fC has been determined, E/A gain at fCis by definition the complement of the gain fromstep 2. Starting at fC, work up and down in fre-quency, combining E/A characteristic with gainfrom step 2, to obtain overall loop gain. Tailor E/Again as needed to shape the overall loop gain char-acteristic working toward the ideal defined in Step1. The examples in Appendix C should helpexplain this process.

Error Amplifier Compensation Circuits: Two cir-cuit models given in Appendix A will handle mostE/A compensation requirements. In most applica-tions, fewer poles and zeros are required, and thecircuit models can be simplified accordingly byomitting components. One of the two models has acurrent sense resistor input and is intended for anAverage Current Mode Control loop. The “refer-ence” voltage is actually the E/A output of thevoltage loop, which sets the current level for theinner loop.

The other circuit model has a voltage dividerinput and is intended for use either as the outer

voltage control loop of a two-loop CMC system, oras a single-loop Voltage Mode Controller.

Note that both circuit models include the feed-back loop gain element, KFB, in addition to KEA,the E/A gain element. This is because with the volt-age divider input, it is difficult to separate KFB fromKEA. The divider resistors in series form KFB, buttheir parallel combination forms all or part of theE/A input resistance, which determines KEA. Theonly problem this causes is mental – KFB is part ofthe Step 2 Bode plot, KEA is defined in Step 4.

Problems Preventing Optimization: There aremany problems that can get in the way of achiev-ing optimum fC. Such things as excessive ESRvariation or excessive gain variation with VIN, orwith RHP zero, or insufficient amplifier bandwidthcan all add tremendous uncertainty in both gainand phase in the region near crossover, especiallyif several factors are at play. The effects of thesevariable elements must be examined at theirextremes. Either the uncertainties must be reducedto manageable proportions, or fC must be shifted toa much lower frequency. But some of these prob-lems can be reduced or eliminating by makingdifferent choices, including rethinking some thedecisions made regarding the power circuit:

If the RHP zero is a problem in a continuousmode boost or flyback circuit, making L smallerraises the RHP zero frequency. If the smallerinductor means crossing into the discontinuousmode at light loads, where peak CMC or VMC fallsapart because of the large drop in loop gain (whichchanges the crossover frequency!), consider usingAverage CMC which adds enough gain to makediscontinuous operation feasible. And the smallerinductor cost less. The penalty is increase rippleand noise.

ESR variation over a wide temperature rangewith aluminum electrolytics is a tough problem toget around. Tantalum capacitors have much lessvariation, but they cost a lot more. Polymer alu-minum electrolytics have no ESR, but limitedcapacitance and low voltage rating make themunsuitable for most applications.

Gain variation due to wide swings in VIN canbe eliminated using peak or average CMC.


Insufficient Amplifier Bandwidth: As switchingfrequencies rise, error amplifier bandwidth may notbe sufficient for slope matching or optimization offC. If the amplifier bandwidth is not enough for thedesired compensation scheme, there are somealternatives other than backing down on thecrossover frequency: (1) use an IC with a betteramplifier. (2) In the current loop, use a larger cur-rent sense resistor or a current transformer with alarger turns ratio. Two cascaded amplifiers can pro-vide a very large gain increase at frequencies wellbelow their crossover frequencies.

Control Problems your Mother NeverTold You About

A tremendous amount of effort has been putinto the development of small-signal techniquesand linear models of the various switching powersupply topologies. Hundreds, if not thousands ofpapers have been written over the years. Your aca-demic “mother”, whoever “he” may be (note the PCsexual ambiguity), typically focuses on new topolo-gies and/or linear modeling.

While not disparaging any of these efforts – farfrom it, these contributions have been immenseand totally necessary – there has been a lack ofbalance and a tendency to try to force behaviorthat is uniquely related to switching phenomenainto linear equivalent models (with sometimesuncertain results). Many of the major significantproblems with switching power supplies do notshow up in the frequency domain, or in the timedomain using averaged models, unless theseproblems are anticipated in advance and providedfor in the models. Simulation in the time domainusing switched models, although slower, revealsthese problems that would have been hidden:

• Modulator gain, d/vC, varies with duty cycle Dwhen E/A gain is adjusted to optimize fC. Thismakes buck regulator gain independent of VINprovides input voltage feed-forward (Fig. 16).This is a geometry problem dealing with the ripplewaveform at the E/A output.

• Subharmonic instability and the slopecompensation / slope matching solution.

• Leakage inductance leading edge delay causes

dc cross-regulation problems.

Large signal problems involve changes thatare so large or so rapid that the control loop cannotkeep up. Error amplifier outputs are driven to theirlimits, and the loop(s) become temporarily open.Large signal events include: start-up, input voltagedrop-outs, rapid input voltage changes, rapid loadcurrent changes.

All energy storage elements within the loop arelikely to either become the cause of large signalproblems, or to behave badly as a result. Thisincludes not only the filter inductor and filter capac-itor, but even the small compensation capacitorsaround the error amplifier.

• The inductor is the main cause of large signalproblems, because of its limited ability to slew thecurrent rapidly to accommodate a large, rapidload change, or during start-up or after a line volt-age drop-out. In a buck regulator with increasingcurrent demand, di/dt = (VIND - VO). If min VINtimes max D is only marginally greater than VO, itwill take forever for the inductor current to rise.Even if the loop bandwidth is 1MHz — The loopis open! Under normal operating conditions, it willstill take several switching periods. Once theinductor slews to the proper current, the filtercapacitor, whose voltage has sagged, takes moretime to recharge, further delaying loop recoverySoft start is helpful only during start-up. A smallerinductor certainly helps at the expense of greaternoise and output filtering. If the inductor is smallenough for discontinuous operation, the slew rateproblem disappears.

• A unique overshoot problem can occur at startupunless soft start is used. Without soft-start, L andC will start to charge resonantly toward 2xVIN, butas soon as the current limit is reached, inductorcurrent stabilizes at this value. The capacitor volt-age now rises linearly toward the desired VOUT.But the inductor current is at the current limit, andif the load current happens to be minimal, there isway too much current. It takes time for the induc-tor current to slew back down to the load currentdemand. During this time the capacitor voltagekeeps rising, above the required VOUT value. The


overshoot is probably only a few percent with thehuge C value of aluminum electrolytics, but withthe much smaller C values that would be usedwith ceramic or polymer capacitors (if frequencyis high enough to make this viable) the overshootcan be quite large – 30-50% — requiring soft-start to prevent this from happening. A lower L/Cratio helps here, as well.

• It may be tempting to add a zero to the erroramplifier to boost low frequency gain andimprove accuracy. Even though the resultingsmall signal plot appears optimum, adding thiscapacitor in the E/A feedback can hurt more thanit helps. If a situation arises where a rapid loadcurrent increase causes inductor current tobecome slew-rate limited, the power supply out-put will sag, and the E/A output will be driven intoits positive limit. The feedback loop is temporari-ly non-functional. The compensation capacitorwill charge to an abnormal voltage which later willdelay recovery of the loop to normal operation.The lower the frequency of the pole or zeroinvolving the compensation capacitor, the longerit will take to recover.

Many IC’s in wide use today have error ampli-fiers whose outputs can swing from 0 to +VCC. Ifthe sawtooth voltage against which the E/A outputwill be compared ramps from 1 to 4 Volts, what isthe virtue of allowing the E/A output to swing to18 V whenever the E/A is temporarily driven into itslimits by a large signal event?.

IC designers should include clamps from theE/A output to its input to prevent the output frombeing driven significantly beyond the useful range.Not only might this hasten recovery of the amplifi-er itself, the amplifier input will always remain at itsnormal operational level, and external feedbackcapacitors will not charge to abnormal voltagesand thus will not delay recovery from large signalevents.

It may seem paradoxical, but the VOUT toler-ance band can be cut in half by reducing thevoltage loop gain. Figure 19 shows the output volt-age waveforms that result when the load currentchanges suddenly and then, at some later time,changes back. The magnitude of VPK is a function

of fC and the loop gain at high frequency. VSS, thesteady-state voltage deviation or error from light toheavy load, is a function of the loop gain at low fre-quency. Fig. 19a demonstrates what happens withvery high low frequency gain resulting in minimalsteady state error, VOUT starts near the nominalvalue and returns there following each loadchange. Thus, the total swing is twice the peakvalue, exceeding the permissible tolerance band.Figure 19c shows what happens with the high fre-quency loop gain unchanged, but with lowfrequency gain reduced to the amount necessaryto result in VSS much larger but within the toler-ance band. The initial shape and amplitude is thesame in Fig 19a and 19b, but the voltage neverreturns to nominal because of the deliberatelylarge dc error. The required gain is easy to calcu-late, especially with current mode control innerloop. If the current sense resistor is .02 Ω, then 0.2V E/A output swing is required for a 10 A current


Figure 19. – VOUT Tolerance

change. If the desired VOUT swing is 0.1 V (withina 0.15 V tolerance band), then the E/A gain mustbe set at 0.2V/0.1V = a gain of 2.0. In Strategy #2above, this technique would be helpful.

Triangle vs. Sawtooth PWM Waveform:In a fixed frequency PWM using a sawtooth

waveform, a switching decision is made once perswitching period based on the control signal levelat that instant when the decision is made. A sec-ond switching action is taken at the clock pulse atthe beginning of the sawtooth ramp, but this is notinfluenced by the control signal. Thus, the dutycycle is modulated according to a single controlsignal sample per switching cycle. In order for theduty cycle to be modulated effectively by a small acsignal, it is obvious that a minimum 2 samplesmust be taken during the period of the signal inorder to define its amplitude. From this point ofview, the highest signal frequency that can passthrough the PWM is one-half of the switching (sam-pling) frequency.

With a triangular waveform, decisions to switchON and OFF are each made on the basis of sepa-rate intersections of the control signal vs. thetriangular waveform. The argument in favor of thetriangular waveform is that since two control signalsamples are taken per switching period, the PWMshould be able to handle twice small signal fre-quency as the sawtooth PWM. Therefore a highercrossover frequency, greater bandwidth andimproved performance should be attainable.

Some counter arguments are: Although thereare two decisions per switching period, they affectonly one power pulse per period. Also, the twopoints of decision converge upon each other atduty cycle extremes. However, the real limitationon crossover frequency is not related to the num-ber of samples taken. The real limitation on fC isthe subharmonic instability which start to occurwhen the slopes of the inductor ripple currentwaveform seen at the error amplifier output exceedthe slopes of the sawtooth (or triangular) waveformat the other comparator input. This slope-matchingcriteria limits the E/A gain, and thereby limits thegain and the crossover frequency of the entireloop. In this regard, the triangular waveform is nobetter and perhaps worse than the sawtooth.Certainly it is more difficult to implement. Slopematching is much more difficult to optimize whenthere are two slopes to consider. The PWM com-parator must latch in both states, and unlatch ateach subsequent peak of the triangular waveform,otherwise the comparator will false trigger on thetiniest noise pulse and will not function at all if thecontrol signal slope exceeds the triangular wave-form at any point.

REFERENCES:(1) R. D. Middlebrook, “Predicting Modulator

Phase Lag in PWM Converter FeedbackLoops,” POWERCON 8, pp. H4.1-H4.6, April1981.

(2) L. H. Dixon, “Average Current Mode Control ofSwitching Power Supplies,” Unitrode SeminarSEM700 1990, reprinted in the UnitrodeDatabook, Application Note U-140.

(3) J. R. Wood, “Taking Account of Output Re-sistance and Crossover Frequency in ClosedLoop Design,” POWERCON 10, pp. D4.1-D4.16, March 1983.

(4) “The Right Half-Plane Zero – A SimplifiedExplanation,” Unitrode Seminar SEM300,1984, Reprinted in SEM400, SEM500,SEM600, and SEM700.


Figure 20. – Triangular PWM Waveform

The error amplifier with its associated compen-

sation network completes the closed loop system

by comparing the output voltage to a voltage refer-

ence at the input of the error amplifier and feeding

the amplified and inverted error signal to the con-

trol input of the PWM or the control input of an

inner loop. The compensation networks provide

phase leads and lags at appropriate frequencies to

cancel excessive phase lags and leads of the

power circuit. The goal is to obtain an overall loop

gain characteristic with a crossover frequency, fc

(where loop gain equals 1, or OdB) as high as pos-

sible, with a single pole (-1 slope) characteristic for1 decade above fc to provide adequate phase

margin, and a two-pole characteristic below fc to

provide a rapidly rising gain characteristic below fc.

If fC is not limited to lower frequencies by prob-

lems such as ESR variation or right half-plane

zeros, fc is ultimately limited by subharmonic oscil-

lation and should be optimized using the

slope-matching technique discussed in the main

body of this paper.

The error amplifier circuits shown in Figures

A-1 and A-2 each apply to a broad range of cir-

cumstances and simplify considerably in most

applications, by eliminating some of the feedback

elements. Figure A-1 is for use in voltage loops,

either single-loop Voltage Mode Control, or the

VREF -~KFB= ~- R1+R2

RIR1=-

KFB

RI

R2=~

1(l)PI = Cp(RF+Rp)

roZ1 = ~ 1

1 )(J)Z2 = Cz(RI +Rz

O)P2 = -fz1 fz2

1

Figure A-1 -Voltage Error Amplifier

[!::!)- 5-A1 Error Amplifier Design

In both circuits, Ap limits the dc and low fre-

quency gain. Making Ap infinite (by omitting it),

pole fp1 is eliminated, and the gain continues to

rise at low frequency until finally reaching the

amplifier gain limit.

With an Average CMC current loop, only the

inductor pole is active at fs. A triangular ripple

waveform is seen across As. There is no reason

not to optimize the crossover frequency by slope

matching. E/A gain should be flat (ApAv down to

fC, resulting in -1 slope in overall loop gain above

fc. Put zero fZ1 at fc to boost overall loop gain with

-2 slope below fc. This current loop crossover fre-

quency will be called fcl. The closed loop gain of

the current loop equals 1/AS and rolls off with a

pole at fCI. This pole at fcl appears in the outer volt-

age loop.There are several possible scenarios for the

outer voltage loop, depending on whether elec-

trolytic capacitors or ceramic/polymer (with

negligible ESAs) are used, and where it is desired

ol1er loop with a Current Mode Control inner loop.

Fig. A-2 is for Average Current Mode Control loops.

The compensated error amplifier gain charac-

teristic has been referred to as KEA, separate and

distinct from the feedback factor for the entire loop,

KFB. However, it is difficult to separate KEA and

KFB physically, and so both of these gain elementsappear in Figs. A.1 andA-2. Note how, in Fig. A-1,

resistors A 1 and A2 in series form the voltage

divider gain element KFB, but these same resistors

in parallel form AI, part of the network which deter-

mines gain KEA. It is important to keep these two

elements separate conceptually, even though they

are combined physically. In Fig. A-2, the loop feed-

back element is the current sense resistor, As.

Although As is physically separate and plays norole in KEA, it is shown here for the sake of consis-

tency with Fig. A-1.

In most voltage loop situations, fZ2 and fp2, tl:t~

pole-zero pair in Fig. A-1 is not required, so Az is O

and Cz is omitted.

100 --Z1 -CpRF

-

fz1

Figure A-2 -Current Error Amplifier

(b!]-E"or Amplifier Design 5-A2

Amplifier Gain limits:

After the desired ElA compensation network

has been designed and plotted, make sure the

intended error amplifier gain characteristic

exceeds the required gain over the entire range of

frequencies. The high frequency end of the El A

gain characteristic is usually a -20 dB/decade

(-1 )slope crossing 0 dB at the specified Unity

Gain-Bandwidth frequency. This slope terminates

at lower frequencies at the specified open loop

voltage gain.

Slope Compensation:Strongly recommended for all continuous

mode regulators using peak current mode control,

even though it is not absolutely necessary for sta-

bility when duty cycle is less than 50%. Ideal slope

compensation is achieved by introducing a ramp

whose slope equals the downslope of the inductor

current ramp, as seen across the current sense

resistor. The ramp could be negative going, super-

imposed on the current programming voltage (the

output of the error amplifier), but it is easier to

derive a positive ramp from the existing IC oscilla-

tor, and add it to the current ramp. For example, a

0.2 V ramp is easily added to the current ramp by

a 10:1 voltage divider taken from a 2 Volt oscillator

ramp to the top of the current sense resistor. Be

careful not to load the oscillator excessively.

to put the voltage loop crossover frequency. These

are best explored by looking at the examples in

Appendix C.

The rising gain characteristic of the zero-pole

pair fZ2 and fp2 shown in Fig. A-1 is required in the

voltage loop to cancel one pole when two poles are

active above the proposed voltage loop crossover

frequency, fcv. This will occur in these circum-

stances: (a) With CMC, when fcv is less than 1

decade below fcl pole, and output filter capacitor

ESR is negligible (capacitor pole). (b) With single-

loop VMC, when the proposed fcv is less than 1

decade below output filter resonance or between

filter resonance and the ESR zero frequency

(L and C poles).

Amplifier Output loading:The starting point in the design of the E/A cir-

cuit is to decide upon an appropriate value for RF.

Too small a value of feedback resistance and/or

other loading on the E/A output may exceed its

source/sink output current capability, so that the

amplifier will not be able to swing its output voltage

over the necessary range. Every amplifier (whether

voltage or transconductance type) has a limited

source and sink output current capability. This is

usually defined on the spec sheet, although some-

times indirectly as the load currents in VOUT High

and VOUT Low tests. Don't make RF too large or

noise sensitivity is increased. If the E/A input is at

2.5V (reference), 25K for RF requires :l:100mA to

drive O to 5V.

Transconductance Amplifiers have high imped-

ance (current source) outputs instead of the low

impedance output of the more common voltage

amplifiers. However, with either type of amplifier,

the E/A voltage gain is established by the feedback

impedance ratio, ZFfZI, and with feedback, the

amplifier type within is indistinguishable.

Transconductance amplifiers used in early power

control IC's developed a reputation for application

problems, but this was because their source/sink

output current capability was low, not because of

the amplifier type.

(1J]- 5-A3 Error Amplifier Design

Low Pass -Single Pole: Figure 8-1

I 1 LF(s) = -S ; rop =RCor R1+-

rop

Gain Slope: -20 dB/decade; Phase Lag: -90° total

Single Zero: Has the same gain and phase char-

acteristic as the single pole shown in Figure 8-1,

except gain increases with frequency. Gain and

phase slopes are both positive.

1 LO>z = RCor Rs .F(s) = I+ 00;: ,

Gain Slope: +20 dB/decade; Phase Lead: +90° total

The Bode plot is a method of displaying com-

plex values of circuit gain (or impedance). The gain

magnitude in dB is plotted vs. log frequency. Phase

angle is plotted separately against the same log

frequency scale.

Bode plots are an excellent tool for designing

switching power supply closed loop systems. They

provide good visibility into the gain/phase charac-

teristics of the various loop elements. Calculation

of the overall loop is made simply by adding the

gain expressed in dB and adding the phase angle

in degrees.

The process is further simplified by using

straight line approximations of the actual curves,

called asymptotes. Calculations are then made

only at the frequencies where the asymptotes

change direction.

Bode's theorem for simple systems, which

includes most switching power supplies: The

phase angle of the gain at any frequency is depen-

dent upon the rate of change of gain magnitude vs.

frequency. A single pole (simple RC low-pass filter)

has a gain slope of -20 dB/decade above its cor-

ner frequency and has a corresponding -90°

phase shift.

First Order Filters (A-C or L-A):

Single pole or zero first order filters both have

gain slopes of 20 dB/decade above the comer fre-

quency. The phase shift asymptotes slope

45°/decade, extending 1 decade each side of the

comer frequency for a total 90° phase shift (see

Rgure 8--1).The maximum gain error is 3 dB between exact

values (curved lines) and the straight line approxi-

mations. The maximum phase error is 5.7°. These

small errors can be safely ignored in the control

loop design.Figure 8-1- Single Pole

I1J]- 5-81 Bode Plots

Right Half-Plane Zero:Refers to its location on the complex s-plane.

The RHP zero has the same positive gain slope as

the conventional (left half-plane) zero, but the

phase slope is negative, like a single pole. Abovethe RHP zero comer frequency, loop gain is held

up, yet more phase lag is added. This makes it vir-

tually impossible to achieve an open loop

crossover frequency above the RHP zero frequen-

cy. Fortunately, the right half-plane zero is

encountered only in boost and flyback regulators

and then only when operated in the continuous

inductor current mode.

The effective series resistance RS determines

a. Rs includes capacitor ESR: Rc, inductor: RL,

rectifier dynamic: Rc, leakage inductance effective

resistance: RI, and load resistance: ROo trans-

formed into its equivalent series R.

a seldom reaches a value greater than 4 or 5.

At full load, low Ro transforms into high Rs. At light

loads, diode Ro limits a.

The phase characteristic slope is approximate-

ly -120°/decade at a a of 0.5. At higher a values,

Figure 8-4 shows that the phase slope becomes

much steeper, making compensation more difficult.

Phase asymptote intercepts:F(s) = ]- -!-

COz

K =52QGain Slope: +20 dB/decade; Phase Lag: -90° total

Second Order Filters (Resonant LC):

The resonant LC filter of Figure 8-2 has a 2

pole --40 d8/decade gain slope above its comer

(resonant) frequency, and a total phase lag of 180°.The gain characteristic has a resonant peak which

varies with a, as shown in Figure 8-3. The reso-

nant effect is suppressed in the closed-loop

characteristic, although it can reduce gain marginand cause loop instability if the resonance is close

to the crossover frequency.

Fs = I

1 + (s/roo)/Q + (S/roo)2

LQ=roo~

where roo = ..[LC ,

~Rs=Rc+RL+RD+RR+ RO ;

Gain Slope: -40 dB/decade; Phase Lag: -180° total

Gain peak at ~ : 20 log Q

Fig. B-2- Two-Pole Resonant

0=:!)-Bode Plots 5-82

Figure 8-3- Two-Pole Resonant GAIN

Figure B-4 -Two-Pole Resonant PHASE

0:::!]- 5-83 Bode Plots

t.

Buck-Derived Topologies --Continuous Inductor Current

Pulse Width Modulator Gain shown here applies to all Buck topologies

PWM Gain: KMOD = d = ~ E/A gain < 1/5 of optimum:

Vs

=J!.-=~Vs VSV1

Vc

d

Vc

PWM Gain (Opt.): Optimized EtA gain (slope-matched)KMODX =

(1) Average Current Mode Control Loop

Feedback Gain: KFB = Rs ; VIA effective current sense R, incl. current xfmr turns ratio

~Power Circuit Gain: KMODX X KpwR =

Filter Gain:

Closed-Loop Gain: G1 KFB (l+sI21rfcl) ; fCloptimal)yequalsfs/21r

~

2) Voltage Loop with Current Mode Control Inner Loop

Feedback Gain: ~B = ~Vo

p Co " G oo K Vo Ro " .ower Ircult alno PWR = -= G I Ro =- R 1 12 f )-; KMQO IS not In voltage loop

s ( +s n- CIVcv

l+sRESRC~c = l+sRoCFilter Gain:

(3) Voltage Mode Control -Single Loop

Feedback Gain: VREF~B = ~

Yo--

-YsPower Circuit Gain: ~x~

-~ ; Kuooxx ~R

-Vs

I -1+$RESRC"'Lc -1 + $.[iC IQ + $2 LC

Filter Gain:

[1:!]- 5-C1 Small Signal Characteristics and Control Loop Examples

Buck Regulator Application Examples

A 1 DO Watt Forward converter is used to illustrate several different approaches to closing thefeedback loop. The input voltage values are referred to the transformer secondary, making the actualprimary voltage and the turns ratio irrelevant to this procedure.

Current sensing is actually performed on the primary side of the forward converter power trans-former. Thus, with a turns ratio of 10:1, for example, an effective sense resistance of 50 m.Q is actually5DO m.Q (10 x 50 m.Q) on the primary side, producing a sense voltage of 1 V on the primary side for20 A secondary side current, and with much less loss .

Calculations:

DMAX= Vo+VF)N,min = 0.46; DMIN = Vo+VF)Nimax = 0.23

Perio~ T = 5~ec. 4~ecTOFFma.= T(I-DMIN) ""

5.5~L = (Vo+VF)to~L1IMAx =

A/ 12xT/2

A.Vp-p

25JlFI

CMIN = 6Q/6Vp.p = -

2=

25mQESRMAX = L1 V p-p/ L1Ip-p =

Application Parameters:

Switching freq., fs; 200kHz

Input Voltage, V,; 12 -24 V

Output Voltage, V 0; 5 Volts

Output Ripple, ~Vp.p; 0.1 V

Output Current, 10; 2 -20 A

Output Rectifier V F; 0.5 VOutput Ripple, ~Ip.p; 4 A

Reference, V REF; 2.5 V

Current Sense, Rs: 50 mil

Oscillator Ramp, V s: 2.5 V Output Resistance. Ro = 2.5 -0.25 .0,

Two different output filter capacitor types will be explored for this application --

1. Panasonic FA Series Aluminum Electrolytic:10V, 3300~F, 25 m.Q. max ESR, (D-16mm, H-20mm): 3300~F, 25 m.Q. max, 12 m.Q. min

RoC Output pole frequency: fo = 19.3 -193 Hz; L-C resonant frequency: fR = 1200 Hz ;

ESR Zero Frequency: fESR = 1900 -4000 Hz

2. Panasonic SP/CB Series Polymer Aluminum Electrolytic:BV, 15~F, zero ESR, (Bmmx5.3mmx3.3mmH), TWO in parallel: 30~F

RoC Output pole frequency: fo = 2.1 -21 kHz L-C resonant frequency: fR = 12.4 kHz

The triangular inductor ripple current waveform (at the switching frequency) will retain its triangularshape across the 3300~F Aluminum Electrolytic because its impedance at fs is the ESR resistance. Ina single loop Voltage Mode Control, if the crossover frequency, fc, is to be optimized, the ErrorAmplifier gain must be flat (0 slope) from fs down to fc, to retain the triangular shape used for slopematching, and to provide a net -1 slope in the overall loop gain to preserve adequate phase margin.Although the waveshape is triangular, its amplitude will vary with ESR, and if ESR variation is large,optimizing fc may be impossible.

With the 30~F Polymer Electrolytic, there are two active poles at fs. The triangular inductor currentwaveform is integrated by the output capacitor, resulting in a quasi-sinusoidal waveshape. If the VMCloop is to be optimized, The E/A characteristic must differentiate this waveform (+ 1 slope) in order torecover the triangular waveform as well as to obtain the -1 slope needed for overall loop phase margin.

[!='J-Small Signal Characteristics and Control Loop Examples 5-C2

\, Forward Converter -Avg. CMC Loop -Aluminum Electrolytic

Use the previously defined Average Current Mode Control Loop equations (1 ). and the parameters ofthis application:

0.1

Ro

KKKK = KMODX X KpWR x KFB X ~C =xKLC

Vo VI VoRs-x-xRs XKLC= -XKLC =VSVI Ro VsRo

I

ZERO to=1

2-POLE Resonant f R ="2;;"JLC

21rRoC

At 10 = 20A, Ro = 0.25; KKKK = 0.4 ~c (-8 dB) ; Zero fo = 193 Hz; fR = 1200 Hz

At 10 = 2A. Ro = 2.5; KKKK = .04 ~c (-28 dB) ; Zero fo = 19.3 Hz; fR = 1200 Hz

Slope Matching Criteria -fs = 200 kHz

dVs Vs dlL (VO+VF)-=-= Vsfs =-RsKEA =RsKEAdt Ts dt L

Put E/A zero at fc : 30 kHz

Put E/A pole at to: 193 Hz

E/A gain at 193 Hz = 10x30K/193 = 1550 (64dB)

Using Error Amplifier Circuit A-2:

Let RF = 10K

Gain above fc = R/R. = 10 ; ...R, = 1 K

1Zero at fc: 30kHz= ; Cp = 560pF

21t"RFCp

Pole at 193Hz =

E/A Summary -Circuit A-2:

R, = 1K, RF = 10K, Rp = 1.5M, Cp = 560pF

Time Constant RFCp = 5.61.lSec

[!:JJ- 5-C3 Small Signal Characteristics and Control Loop Examples

Forward Converter -A vg. CMC Loop -Polymer Electrolytic

Use the previously defined Average Current Mode Control Loop equations (1 ). and the parameters ofthis application:

KKKK = ~ODX X KpWR x ~B X ~C = ~x!.LXRs XKLC =Ro

-

VSV1 VsRo

l+sRoC , --.

~

I~ 2 " ..2-POLE Resonant fR= ~

l+s"LCIQ+s LC .21C"LC

At 10 = 20A. Ro = 0.25; KKKK = 0.4 ~c (-8 dB) ; Zero fo = 21 kHz ; fR = 12.4 kHz

At 10 = 2A. Ro = 2.5 ; KKKK = .04 ~c (-28 dB) ; Zero fo = 2.1 kHz ; fR = 12.4 kHz

~c=


dVs Vs dlL (VO+VF)~="'T;= Vsfs = ~RsKEA = LRsKEA

Put E/A zero at fc : 30 kHz

Put E/A gain below 100 Hz = 2500 (68dB)


Let RF = 10K

Gain above fc = AIR, = 10; :.R, = 1K

1Zero at fc: 30kHz= ; Cp = 560pF

2nRFCp

Gain below 100 Hz = 2500 + RIAl; Rp = 2.5M


R, = 1K, RF = 10K, Rp = 2.5M, Cp = 560pF

Time Constant RFCp = 5.6~sec

0

.-

w(/) -90

<:1:Q.

.180

0:!1-Small Signal Characteristics and Control Loop Examples 5-C4

Forward Converter- Voltage Loop with CMC -Aluminum Electrolytic

Use the previously defined Voltage Loop with CMC equations (2), and the parameters of this applica-tion. The PWM is within the current loop and does not appear in the outer voltage loop. The lowfrequency power circuit gain equals the current loop closed loop gain times load resistance:

~WRPole at fc, = 30 kHz

Ro .R = .05.Q ;

, s = G,Ro =~(I+s/21rfc,)

&x~x.Rs Vo

RoxKLC = -x

(l+snnfcl) 0.1

KKK = KpWA x KFB X ~C = .XKLC(l+s/21t" f CI )

l+sRESRC .KLC = l+sRoC . ; Zero at f ESR =

27rRESRC

fESR = 1900- 4000 Hz

tESR = 1900 -4000 Hz

Pole at f o =2iiR;;C

At 10 = 20A, Ro = 0.25; KKK = 2.5 ~c (+8 dB) ; fo = 193 Hz ;

At 10 = 2A, Ro = 2.5; KKK = 25 ~c (+28 dB) ; fo = 19.3 Hz ;

Slope matching is not used, voltage loop crosses over at 4 kHz (max fesR)' to avoid problems withcurrent loop crossover frequency, fC,"

Put E/A pole at to: 193 Hz

R R .012KKK at 4 kHz =-fl-x~=-=0.12 (-18dB)

0.1 Ro 0.1

:.E/A gain at 4 kHz = 8.33 (+18dB)

E/A gain at pole to = 8.33x4000/193 = 173 (45dB)

Using E"or Amplifier Circuit A-1 :

RF. Rz = O (omit) ; Omit Cz

LetR,=1K

R1 = R/~ = 2K; R2 = R/(1-K.B) = 2K

Gain below fc = R;R, = 173; :.Rp = 173K

IPole at fo: 193Hz = "'i"i"i;-c-; ; Cp = 4700pF

E/A Summary- Circuit A-1:

R1 = 2K, R2 = 2K, Rp = 173K, Cp = 4700pF

Rz, RF, Cz omitted

~- 5-C5 Small Signal Characteristics and Control Loop Examples

Forward Converter -Voltage Loop with CMC -Polymer Electrolytic

Use the previously defined Voltage Loop with CMC equations (2), and the parameters of this applica-tion. The PWM is within the current loop and does not appear in the outer voltage loop. The lowfrequency power circuit gain equals the current loop closed loop gain times load resistance:

; As = .OSQ ; Pole at fcl = 30 kHz

.XKLC(l+s/21r f CI )

RoxxKLC = QI (l+s/21rfc/)

fo = 21 kHz ; fCt = 30 kHz

fo = 2.1 kHz ; fcl = 30 kHz

Slope matching is not used, voltage loop crosses over at 21 kHz (max to),

Put E/A pole at max to; 21 kHz

KKK at fcl = 21 kHz = 2.5 (+8dB)

Using Error Amplifier Circuit A-1 :

.R:.EtA gain at 21 kHz = 0.4 (-8d8) = F

R1 +Rz60

40

m 20~

Z< 0~

Zero: fa: 29kHz = ; Cp =220pF21t"(Rr+RzCz

For noise reduction

Pole at 1010: 300kHz = 21rRJCZ ' 0',

R1 = R/~ = SK; R2 = R/(1-~) = SK

Rz = (R, + RJ -R, + 22.SK.

..Rr=25K -20

-40

10 100 1K 10K

FREQUENCY

100K 1M

0


R1= 5K, R2 = 5K, Rz = 22.5K, RF = 10K

Cp = 750pF , Cz = 220pF

Rp. omitted

;-

w(/) -90<:1:Q.

180

l!=:!J-Small Signal Chamcteristics and Control Loop Examples 5-C6

Ro~WR = GIRO =R;(I+s/21t"fcl

t , Forward Converter -Voltage Mode Control- Aluminum Electrolytic

Use the previously defined Voltage Mode Control -Single Loop equations (3), and the parameters ofthis application:

~

Vo

KKKK = KMODX X KpWR X KFB X KLC = xKLC = lxKLCv v

~xVlx--B§LxKLC=VSVl Vo

K -l+sRESRC .LC- l+sJLC IQ+S2 LC ,

I2-POLE Resonant f R =~ ZERO f ESR =

21t'RESRC

Resonant frequency fA = 1200 Hz ; ESR Zero fESR = 1.9 kHz (.0250) ; 4.0 kHz (.0120)


dVs Vs dJL (VO+VF )~=T;= Vsfs = &RESRKFBKEA = L RESRKFBKEA

KEA = VsfsL(VO+VF)RESR K = 40 (32dB)

max FB

:.Crossover, fcl' occurs where KKKK = -32 dB

From the Bode plot: fCI = 30 kHz

Put EtA zero at fJ6: 200 Hz

60

40


Rp. Rz = 0 (omit); Omit Cz

Let RF = 40K;

EtA Gain above 200 Hz = 40 = R/R, ; R, = 1Km 20'C

Z< 0(!)

Zeroatfc: 200HZ=~; Cp =.03.uF)

R1 = R/KFB = 2K; R2 = R/(1-~) = 2K

-20

-40

1K 10K

FREQUENCY

100K 1M10 100

E/A Summary -Circuit A-2:12

R1 = 2K, R2 = 2K, RF = 40K, Cp = .02~F

Rp, Rz, Cz omitted

Time Constant RFCp = 800~sec

0

~

w -90(/)<:1:no

.180

~- 5-C7 Small Signal Chatacteristics and Control Loop Examples

Use the previously defined Voltage Mode Control -Single Loop equations (3), and the parameters ofthis application:

KKKK = KMoox X KpWA x ~B X ~C =

~c= fR = 12.4 kHz, .

2-POLE Resonant f R ="2;;-JLC' .

l+sJLCIQ+s2LC


Optimum crossover frequency for a buck regulator with slope matching is f/2n, or 30 kHz in thisexample. However, the ripple voltage across output capacitor C is not triangular, but a quasi-sinusoiddue to double integration (L and C, ESR is negligible). The E/A must differentiate the waveform acrossC to recover the triangular waveshape at the PWM comparator input.

:.Crossover, fc" will occur at 30 kHz

KKKK at 30kHz = 1x(12.4kHzl30kHz)2 = 0.17

:.E/A gain at 30kHz = 1/0.17 = 5.8 (15dB)

Put E/A double-zero at fR: 12.4 kHz

E/A gain at fR = 2.4 (7.6dB); at fs = 38.6

60

~40

~m 20"0

Z< 0f!J

lKKKK-KOA

-20

TO

-40

1K 10K

FREQUENCY

100K 1M10 100

Zero at fR: 12.4 kHz= 21t"(R1 ;Rz )Cz

Cz = 1200 pF

R, = 500n -high freq. pole for noise reduction:

Pole: f~(R,+RJ/R, = 260 kHz

R1 = R/KF8 = 1 K; R2 = R/(1-KF8) = 1 K

E/A Summary -Circuit A-2:12

R 1 = 1 K, R2 = 1 K, Rz = 10K,

Cp = 510 pF, Cz = 1200 pF

Rp omitted

RF = 25K

~ v

0

;-

w(/) -90<:1:Q.

-180

[!:J]-Small Signal Chalacteristics and Control Loop Examples 5-C8

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas InstrumentsPost Office Box 655303Dallas, Texas 75265

Copyright 2002, Texas Instruments Incorporated

Date post:	13-Apr-2015
Category:	Documents
Upload:	moises-pedraza-castillo
View:	27 times
Download:	2 times

Control Loop Coockbok 41 Pag.

Documents