Controlled growth of a graphene charge-floating gate for organic non-volatile memory transistors
Yunhwan Park a, 1, Subeom Park b, 1, Insu Jo b, Byung Hee Hong b, **, Yongtaek Hong a, *
a Department of Electrical Engineering and Computer Science, Inter University Semiconductor Research Center (ISRC), Seoul National University, Seoul151e744, Republic of Koreab Department of Chemistry, Seoul National University, Seoul 151e747, Republic of Korea
a r t i c l e i n f o
Article history:Received 18 December 2014Received in revised form2 September 2015Accepted 12 September 2015
Keywords:GraphenePentaceneNon-volatile memoryOrganic thin film transistor
We report memory application for graphene as a floating gate in organic thin-film transistor (OTFT)structure. For graphene floating gate, we demonstrate a simpler synthesis method to form a discretegraphene layer by controlling the growth time during a conventional CVD process. The resulting organicmemory transistor with the discrete graphene charge-storage layer is evaluated. The device wasdemonstrated based on solution-processed tunneling dielectric layers and evaporated pentacene organicsemiconductor. The resulting devices exhibited programmable memory characteristics, includingthreshold voltage shifts (~28 V) in the programmed/erased states when an appropriate gate voltage wasapplied. They also showed an estimated long data retention ability and program/erase cycles endurancemore than 100 times with reliable non-volatile memory properties although operated without encap-sulation and in an ambient condition.
With continued development in information technology, thereis increasing interest in non-volatile memory for use as data storagein electronic devices. There are currently several types of memorydevices available, which are categorized on the basis of theiroperating methods. Among these, a floating gate memory tran-sistor have beenwidely studied owing to their non-destructive dataprocessing, reliable data storage, and simple structure; whichtypically comprises a single transistor [1,2]. Those based on organicsemiconductors, such as pentacene, have received particular in-terest by virtue of their simple process and potentials for beingused as flexible or stretchable device [3]. In all floating gatememory transistors, however, the memory properties can bedetermined by the floating gate and tunneling dielectric. To date,conventional thin films floating gate have been used in memorytransistor devices, but these conventional memory devicesencounter difficulties of floating gate interference and parasitic
capacitance; both of which affect the overall device performanceand reliability, when used with miniaturized cell sizes and in highdensities [4e9]. To overcome these problems, a number of researchgroups are currently searching for suitable materials that could beused to replace those used in the conventional floating gates.
Among the various potential candidates for the charge storagelayer, graphene offers an advantage of introducing metallic prop-erties [10]. Therefore, it can enhance the performance of currentmemory devices in a facile manner, owing to its unique propertiesof high density of state, high work function, and low dimensionality[11e16]. However, the two-dimensional continuous planar struc-ture of graphene typically has difficulty in storing sufficient chargefor non-volatile memory function, because the charge carrierstored in the continuous charge storage layer is easily lost throughthe thin tunneling dielectric. Some groups have, therefore, selectedto use discrete charge storage layers, such as metal nanoparticles,for the floating gate in non-volatile memory devices [17,18].
In this study, we fabricated the graphene floating gate into theorganic nonvolatile memory transistors (ONVMT) with bottom-gate/top-contact structure using pentacene and polystyrene (PS)as active and charge tunneling dielectric layers, respectively. For thefloating gate, we propose a discrete graphene layer formed bycontrolling growth time of the graphene layer during a conven-tional CVD process, and then simply transferring it onto the gate
Y. Park et al. / Organic Electronics 27 (2015) 227e231228
dielectric layer. The fabricated ONVMT showed an anti-clockwisehysteresis in transfer curves with large memory windows (~40 V)and a reasonable program/erase cycle endurance greater than 100times and an estimated long data retention time of >1 yearalthough it was operated without encapsulation in an ambientcondition.
2. Experimental procedure
In order to fabricate the partially grown graphene layer, a roll ofcopper foil containing 150 ppm of silver was first inserted into aquartz tube of the CVD system and then heated to 1000 �C for40 min with flowing 40 sccm CH2 and 5 sccm H2 at 50 mTorr. Afterreaching 1000 �C, the sample was annealed for 20 min withoutchanging the flow rate and pressure. Partially grown graphene layerwas synthesized by controlling the growth time, which was varied(1, 20, 40 and 60 s) maintaining the total pressure at 100 mTorr. TheCVD chamber was cooled down to room temperature with flowingonly 5 sccm H2. After the sample was taken out of the chamber,polymethylmethacrylate (PMMA) was poured on the graphene filmgrown on the copper foil. When floated in an aqueous solution of0.1 M ammonium persulphate ((NH2)4S2O8), the PMMA with thepartially grown graphene layer was separated from the copper foil[19,20].
For the memory device fabrication, a heavily doped silicon (Si)substrate with thermally grown 200 nm thick silicon dioxideinsulator was used. In order to evaluate the charge storage function,two types of devices were fabricated: onewith and onewithout thegraphene floating gate. For the device with the floating gate, thepartially grown graphene filmwas first transferred from the PMMAlayer onto the SiO2 surface and then, the charge tunneling dielectricPS was deposited from a toluene solution having the concentrationof 3.5 mg/ml by spin-coating at 3000 rpm for 40 s. The film wasthen annealed at 120 �C for 60min in the nitrogen atmosphere. Thethickness of the obtained layer were approximately 15 nm. Finally,to deposit the active semiconductor layer and source/drain elec-trodes, 50 nm pentacene and 70 nm Au layers were sequentiallydeposited by a thermal evaporation process. The channel lengthand width were 50 and 1000 mm, respectively.
Atomic force microscopy (AFM) images of the graphene filmswere taken by using a non-contact mode of atomic force micro-scopy system (XE-100, Park System). Raman spectrum wasmeasured by using Raman microsystem 2000 (Renishaw). Allfabricated devices were electrically characterized in ambient anddark conditions by using a semiconductor parameter analyzer(Agilent HP 4145B).
3. Results and discussion
Fig. 1(a) illustrates schematic image of graphene growth processon Cu foil. By controlling of growth time of graphene, partiallygrown graphene layers with various flake size were synthesized. Asshown in FE-SEM images of Fig. 1(c)e(f), graphene seed and graingrow larger with time. After 60 s (Fig. 1(f)), graphene covered allarea of Cu foil with a continuous single layer. For the discrete gra-phene floating gate, we selected the partially grown graphene with40 s growth time in order to ensure a large coverage of surface andguarantee discrete flake formation simultaneously. Raman spec-troscopy was also used to ensure the quality of the transferredsingle layer graphene, the results of which are shown in Fig. 1(b).The Raman spectrum of graphene is characterized by three maincharacteristic peaks. The G peak, D band, and 2D peak showed atnear 1580 cm�1, 1350 cm�1, and near 2700 cm�1, respectively. TheRaman spectra are measured on the edge, middle and center areasof one partially grown graphene (10 � 10 mm2). The formation of
monolayer graphene flakes is confirmed by a sharp 2D-band(~40 cm�1) and no peak at D band (~1350 cm�1).
A schematic illustration of the fabricated ONVMT is depicted inFig. 2(a). AFM images of the evaporated pentacene and spin-coatedPS layers are also shown in Fig. 2(b) and (c), respectively. The PSlayer was measured to have an average thickness of ~15 nm and aroot mean square roughness of 0.3 nm, which are good for aneffective tunneling dielectric layer with a smooth surface forgrowth of the terraced pentacene film. The partially grown gra-phene used for the floating gate is shown in Fig. 2(d). It is noted thatthe graphene flake is 10 mm in the longest size and 1 nm high onaverage. The graphene approximately covers 80% of the totaltransferred area. Transmission electron micrographs (TEM) images(Fig. 2(e) and (f)) for the cross-section of the areas with andwithoutgraphene flakes in the transferred area clearly show the discretefloating gate formation.
The electrical properties of the fabricated ONVMTs are shownand comparedwith those of the conventional OTFTs that contain nographene floating gate (Fig. 3). It is noted that the same structure ofpþþSi/SiO2/PS/pentacene/Au source-drain for OTFTs to compare thecharge storage capability in both ONVMTs and OTFTs. Fig. 3(a)shows the transfer and output characteristics of the fabricatedTFTs, which show a typical p-channel TFT behavior. Fig. 3(b) showsa double transfer curve, which obtained by sweeping gate voltagefirst from positive to negative values and then vice versa. Althoughthere is a certain amount of hysteresis for the conventional OTFTs aspreviously reported for OTFTs with PVP gate dielectric [21e23], thehysteresis amount is very small (<5 V) in comparison with that ofthe ONVMTs (~40 V) when the gate voltage was swept from þ80 Vto �80 V and then swept back to þ80 V [22]. Therefore, it can beconcluded that there is almost negligible charging and dischargingof the charge carriers in the bulk, or at the interfaces of the gatedielectric layer in our devices. For the fabricated OTFTs, we ob-tained a saturation mobility of 0.39 cm2/V$s, a threshold voltageof �13.2 V, a subthreshold swing of 2.6 V/decade, and an Ion/Ioffratio of ~106.When a graphene floating gate is inserted (pþþSi/SiO2/graphene/PS/pentacene/Au source-drain), we obtained a largerhysteresis effect and enhanced charge storage capability. Thetransfer and output characteristics of the fabricated ONVMTs areillustrated in Fig. 3(c). Similar to the devices without a graphenecharge layer, they exhibit typical p-channel TFT characteristics butwith a saturation mobility of 0.061 cm2/V s, a threshold voltageof �10.1 V, a subthreshold swing of 8.5 V/decade, and an Ion/Ioffratio of 105. It is thought that the mobility degradation is caused bythe graphene floating gate and the trapped charge carriers in thegraphene layer close to the pentacene surface, which introducepositive charges at the semiconductor/dielectric interface anddegrade the channel conductance [17]. Fig. 3(d) shows the transfercharacteristics of the fabricated ONVMTs for various sweep rangesof gate voltages (VG), in both the forward (þVG to �VG) and reverse(�VG to þVG) directions, at the same drain voltage (VD) of �20 V.This demonstrates a clear hysteresis loop for all gate voltages andfor the range ofþ80 V to�80 V, the resulting memory windowwas40 V. This confirms that the charges were successfully transferredbetween the pentacene and the graphene layers. Moreover, theanticlockwise hysteresis direction indicates that electrons wereinjected from the pentacene to graphene layer when a positive gatebias was applied, and ejected from the graphene to pentacene layerwhen a negative gate bias was applied [24].
To evaluate the programming and erasing properties, the shift inthe transfer curves from the initial state was measured afterapplying a gate voltage of þ80 V and �80 V, respectively, for100 ms. The drain-source voltage was kept constant at �20 V inboth measurements. Fig. 4(a) shows the programming and erasingcharacteristics of the ONVMT, in which large Vth shifts are shown.
Fig. 1. (a) Schematic diagram of graphene growth on Cu foil using Ag as nucleation seeds. (b) The Raman spectra measured on edge, middle and center area of the partially growngraphene. c) SEM images of (c) 1 s (d) 20 s (e) 40 s (f) 60 s of graphene seeds and grains after the CVD process, respectively; All images were obtained on Cu foils.
Fig. 2. (a) Device schematics of ONVMTs. AFM topology images: (b) Pentacene layer on PS. (c) PS charge-tunneling dielectric on graphene. (d) Partially grown graphene flakes. TEMimages: partially grown graphene on SiO2 (e) with graphene, and (f) without graphene.
Y. Park et al. / Organic Electronics 27 (2015) 227e231 229
Specifically, the transfer curves were shift toward positive directionduring programming, while erasing brings the transfer curves backclose to their original states. The difference of the drain current wasas large as 104 at VGS ¼ 0 V and VDS ¼ �20 V. The total shift in thethreshold voltage (DVth) was about 23 V. The observed memorybehavior can be explained on the basis of the charging/dischargingof the electrons in the graphene layer during the programing/erasing operations as shown in Fig. 4(b). When a high positive gatebias is applied, electrons from the lowest unoccupied molecularorbital (LUMO) of pentacene are transferred into the graphenethrough the PS tunneling dielectric [22,25,26]. Similar electrontunneling and memory effect of the organic TFT memory with afloating gate structure has been explained by Fowler-Nordheimtunneling followed by charge trapping, which is a dominantmechanism for charge injection through relatively thick tunnelingdielectric (~15 nm) in the ONVMT [1,16,24,27]. When a high
negative gate bias is applied during the erasing period, the trappedelectrons are tunneled back from graphene to pentacene, and thuscause the threshold voltage to be negatively shifted.
In fact, from the amount of the Vth shift, we can calculate thesurface density of the transferred charges (Dn) from pentacene tographene after the programming process using the followingequation [26,27].
Dn ¼ DVthCie
;
where e, DVth, and Ci are the elementary charge, the shift in Vth, andthe capacitance of the gate dielectric, respectively. With a gatedielectric capacitance Ci ¼ 1.6 � 10�8 F/cm2, and DVth ¼ 23 V, thesurface density of charges transferred from pentacene to graphene,Dn, was estimated to be 2.3 � 1012 charges/cm2. The total coverage
Fig. 3. (a) Transfer and output characteristics of organic thin film transistors without a graphene layer (b) Double sweep of gate bias of organic thin film transistors from þ80 Vto �80 V (c) Transfer and output characteristics of organic memory thin film transistors with a graphene layer (d) Double sweep of gate bias of organic thin film transistors forvarious gate voltage ranges.
100 101 102 103 104 105 106 10710-11
10-10
10-9
10-8
10-7
10-6
)A(tnerru
Cniar
D
Time (sec)
VG=0 V, VDS= -20 V Programed state Erased state
103
1 year
-40 -30 -20 -10 0 10 20 30 40 5010-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Gate Voltage (V)
)A(tnerru
Cniar
D
Initial state After writing @ 80 V for 0.1 sec After erasing @ -80 V for 0.1 sec
Writing
Erasing
(a)
(c)
0 10 20 30 40 50 60 70 80 90 10011010-10
10-9
10-8
10-7
10-6
P/E cycle (number)
)A(tnerru
Cnia r
D Erased state
Programmed state
(d)
(b)
Fig. 4. (a) Transfer characteristics of the organic memory devices according to the programming/erasing operations. Programming (þ80 V) and erasing pulses (e 80 V) were appliedto the gate for 100 ms. (b) Operating mechanism of floating gate memory device. (c) Data retention characteristics of organic memory devices. (d) Endurance characteristics ofmemory devices after writing and erasing processes. A program/erase gate bias of 80 V was repeatedly applied for 0.5 s, and a reading bias of �20 V was applied after each cycle tomeasure the drain current.
Y. Park et al. / Organic Electronics 27 (2015) 227e231230
Y. Park et al. / Organic Electronics 27 (2015) 227e231 231
of partially grown graphene is about 80% of the total channel area,and so the surface density of charges transferred in the graphenesurface was estimated to be 2.87 � 1012 charges/cm2, which issimilar to the stored charges for other ONVMTs with various typesof the floating gates such as Au nano particles and graphene oxide[26e28].
Two factors that are the most important for a memory deviceare data retention ability and program/erase cycle stability. To firstexamine how long the memory device can sustain the storedcharges, the drain current was monitored at the programmed/erased states with the same programming and erasing conditionsthat were used. The drain current was measured at 0 V of gatevoltage with a �20 V drain voltage for each state. The measured onand off currents are illustrated in Fig. 4(b), in which the ON statecurrent is dropped by half of the initial value after 105 s while theOFF state current remains almost constant at 10�10 A over the sameperiod of time. By extrapolating this result we can obtain a 103 on/off ratio after 1 year, which indirectly confirms that the device canmaintain data and a distinguishable on/off ratio over this longperiod of time. The program/erase cycle properties were alsomeasured as shown in Fig. 4(c). In order to measure the enduranceproperties, the programming/erasing operations were repeatedwith continuous application of bias pulses with the magnitude of80 V and �80 V, and time width of 0.5 s. In each programming/erasing operation, the drain current measured at 0 V of gate voltagewith a�20 V drain voltage. Although some degradation of the draincurrent was observed with the program/erase cycles, a distin-guishable on/off ratio of 103 is nonetheless obtained after 100program/erase cycles. It is noted that the device was not encapsu-lated and measured in air. The measured current for the pro-grammed and erased states degraded with time, but the memoryperformance was well maintained compared to other organicmemory devices under similar conditions. Overall, our ONVMTsshowed good data sustainability and endurance ability, makingthem promising candidates well suited to memory deviceapplications.
4. Conclusion
The ONVMTs based on the graphene floating gate have beensuccessfully demonstrated. In order to use graphene as a floatinggate, partially grown graphene was synthesized by controlling thetime of the graphene growth during a CVD process. The solution-processed PS dielectric layer was used as a charge-tunnelingdielectric layer and pentacene was used as an active layer. Thefabricated ONVMTs exhibited largememory windows (~40 V) and agood data retention ability. The shift of the transfer curves atvarious gate biases indicated a clear charge-trapping and de-trapping behavior in the partially grown graphene within a shortperiod of time (100 ms). The data retention properties of our de-vices showed an on/off ratio of about 5� 104 even after 105 s, which
leads to the estimated charge storage time of more than a year. Thefabricated ONVMTs were reliable after more than one-hundredrepeated programming/erasing cycle tests. Although the memoryperformance needs to be further improved, the mechanical flexi-bility and optical transparency of the organic and the partiallygrown graphene layers are expected to show great promise for usein transparent and flexible next generation memory applications.
References
[1] J.C. Scott, L.D. Bozano, Adv. Mater. 19 (2007) 1452e1463.[2] Y.L. Guo, G. Yu, Y.Q. Liu, Adv. Mater. 22 (2010) 4427e4447.[3] G. Darlinski, U. Bottger, R. Waser, H. Klauk, M. Halik, U. Zschieschang,
G. Schmid, C. Dehm, J. Appl. Phys. 97 (2005) 093708.[4] J.Y. Kim, K. Lee, N.E. Coates, D. Moses, T.Q. Nguyen, M. Dante, A.J. Heeger,
Science 317 (2007) 222e225.[5] W.L. Leong, P.S. Lee, A. Lohani, Y.M. Lam, T. Chen, S. Zhang, A. Dodabalapur,
S.G. Mhaisalkar, Adv. Mater. 20 (2008) 2325e2331.[6] C. Novembre, D. Guerin, K. Lmimouni, C. Gamrat, D. Vuillaume, Appl. Phys.
Lett. 92 (2008) 103314.[7] L.J. Zhen, W.H. Guan, L.W. Shang, M. Liu, G. Liu, J. Phys. D Appl. Phys. 41 (2008)
135111.[8] K.J. Baeg, Y.Y. Noh, H. Sirringhaus, D.Y. Kim, Adv. Funct. Mater. 20 (2010)
224e230.[9] T. Sekitani, T. Yokota, U. Zschieschang, H. Klauk, S. Bauer, K. Takeuchi,
M. Takamiya, T. Sakurai, T. Someya, Science 326 (2009) 1516e1519.[10] A.J. Hong, E.B. Song, H.S. Yu, M.J. Allen, J. Kim, J.D. Fowler, J.K. Wassei, Y. Park,
Y. Wang, J. Zou, R.B. Kaner, B.H. Weiller, K.L. Wang, ACS Nano 5 (2011)7812e7817.
[11] E.B. Song, B. Lian, S.M. Kim, S. Lee, T.-K. Chung, M. Wang, C. Zeng, G. Xu,K. Wong, Y. Zhou, H.I. Rasool, D.H. Seo, H.-J. Chung, J. Heo, S. Seo, K.L. Wang,Appl. Phys. Lett. 99 (2011).
[12] R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, Proc. IEEE 91 (2003) 489e502.[13] A.K. Geim, K.S. Novoselov, Nat. Mater. 6 (2007) 183e191.[14] T.J. Echtermeyer, M.C. Lemme, M. Baus, B.N. Szafranek, A.K. Geim, H. Kurz,
IEEE Electron Device Lett. 29 (2008) 952e954.[15] B. Standley, W.Z. Bao, H. Zhang, J. Bruck, C.N. Lau, M. Bockrath, Nano Lett. 8
(2008) 3345e3349.[16] D.I. Son, T.W. Kim, J.H. Shim, J.H. Jung, D.U. Lee, J.M. Lee, W. Il Park, W.K. Choi,
Nano Lett. 10 (2010) 2441e2447.[17] S.J. Kim, J.S. Lee, Nano Lett. 10 (2010) 2884e2890.[18] S.J. Kim, Y.S. Park, S.H. Lyu, J.S. Lee, Appl. Phys. Lett. 96 (2010) 033302.[19] K.S. Kim, Y. Zhao, H. Jang, S.Y. Lee, J.M. Kim, K.S. Kim, J.H. Ahn, P. Kim, J.Y. Choi,
B.H. Hong, Nature 457 (2009) 706e710.[20] S. Bae, H. Kim, Y. Lee, X.F. Xu, J.S. Park, Y. Zheng, J. Balakrishnan, T. Lei,
H.R. Kim, Y.I. Song, Y.J. Kim, K.S. Kim, B. Ozyilmaz, J.H. Ahn, B.H. Hong, S. Iijima,Nat. Nanotechnol. 5 (2010) 574e578.
[21] X. Gao, X.-J. She, C.-H. Liu, Q.-J. Sun, J. Liu, S.-D. Wang, Appl. Phys. Lett. 102(2013).
[22] K.-J. Baeg, Y.-Y. Noh, J. Ghim, B. Lim, D.-Y. Kim, Adv. Funct. Mater. 18 (2008)3678e3685.
[23] J.-C. Hsu, W.-Y. Lee, H.-C. Wu, K. Sugiyama, A. Hirao, W.-C. Chen, J. Mater.Chem. 22 (2012) 5820e5827.
[24] M. Kang, Y.-A. Kim, J.-M. Yun, D. Khim, J. Kim, Y.-Y. Noh, K.-J. Baeg, D.-Y. Kim,Nanoscale 6 (2014) 12315e12323.
[25] M. Debucquoy, M. Rockele, J. Genoe, G.H. Gelinck, P. Heremans, Org. Electron.10 (2009) 1252e1258.
[26] K.J. Baeg, Y.Y. Noh, J. Ghim, S.J. Kang, H. Lee, D.Y. Kim, Adv. Mater. 18 (2006)3179e3183.
