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3 typical $%&'it, "#&only PCI card, in thi cae a 4C4I adapter from 3daptec

Conventional PCI (part of the PCI "ocal #us tandard and often hortened to PCI) i a

computer 'u for attaching hard5are device in a computer 6 !hee device can take either the

form of an integrated circuit fitted onto the mother'oard itelf, called a planar device in the PCIpecification, or an epanion card that fit into a lot6 !he name PCI  i an initialim formed

from Peripheral Component Interconnect 6 !he PCI 7ocal 0u i common in modern PC, 5here

it ha diplaced I43 and #+43 7ocal 0u a the tandard epanion 'u, and it alo appear inmany other computer type6 8epite the availa'ility of fater interface uch a PCI&9 and PCI

+pre, conventional PCI remain a very common interface dated info;6

!he PCI pecification cover the phyical i<e of the 'u (including 5ire pacing), electrical

characteritic, 'u timing, and protocol6 !he pecification can 'e purchaed from the PCI4pecial Interet =roup (PCI&4I=)6

!ypical PCI card ued in PC include: net5ork card, ound card, modem, etra port uch a

>40 or erial, !# tuner card and dik controller6 ?itorically video card 5ere typically PCI

device, 'ut gro5ing 'and5idth re@uirement oon outgre5 the capa'ilitie of PCI6 PCI videocard remain availa'le for upporting etra monitor and upgrading PC that do not have any

3=P or PCI +pre lot6;

/any device traditionally provided on epanion card are no5 commonly integrated onto the

mother'oard itelf, meaning that modern PC often have no card fitted6 ?o5ever, PCI i tillued for certain peciali<ed card, although many tak traditionally performed 'y epanion

card may no5 'e performed e@ually 5ell 'y >40 device6

Contents

hide;

•

?itory • % 3uto Configuration 

• $ Interrupt 

• - Conventional hard5are pecification 

o -6 Card keying 

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o -6% Connector pinout 

• " #ariant 

o "6 Conventional 

o "6% PCI&9 

• . Phyical card dimenion 

o .6 Full&i<e card 

o .6% Card 'ackplate 

o .6$ ?alf&length etenion card (de&facto tandard) 

o .6- 7o5&profile (half&height) card 

o .6" /ini PCI 

.6"6 !echnical detail of /ini PCI 

o .6. 2ther phyical variation 

• A PCI 'u tranaction 

o A6 PCI addre pace 

o A6% PCI command code 

• B PCI 'u ignal 

o B6 4ignal timing 

o B6% 3r'itration 

o B6$ 3ddre phae 

B6$6 3ddre phae timing 

B6$6% 8ual&cycle addre 

B6$6$ Configuration acce 

o B6- 8ata phae 

B6-6 Fat 8+#4+7 on read 

o B6" +nding tranaction 

o B6. 0urt addreing 

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o B6A !ranaction eample 

o B6B Parity 

o B6* Fat 'ack&to&'ack tranaction 

o B6 .-&'it PCI 

o B6 Cache nooping (o'olete) 

• * 4ee alo 

• Reference 

• +ternal link 

$edit% History

Work on PCI 'egan at IntelD 3rchitecture 8evelopment 7a' circa **6

3 team of Intel engineer (compried primarily of 387 engineer) defined the architecture anddeveloped a proof of concept chipet and platform (4aturn) partnering 5ith team in the

companyD dektop PC ytem and core logic product organi<ation6 !he original PCI

architecture team included, among other, 8ave Caron, Eorm Ramuen, 0rad ?oler, +d

4olari, 0ruce oung, =ary 4olomon, 3li 2<takin, !om 4akoda, Rich ?alam, Jeff Ra'e, and4teve Ficher6

PCI 5a immediately put to ue in erver, replacing /C3 and +I43 a the erver epanion 'u

of choice6 In maintream PC, PCI 5a lo5er to replace #+43 7ocal 0u (#70), and did notgain ignificant market penetration until late **- in econd&generation Pentium PC6 0y **.

#70 5a all 'ut etinct, and manufacturer had adopted PCI even for -B. computer6%; +I43

continued to 'e ued alongide PCI through %6 3pple Computer  adopted PCI for profeional

Po5er /acintoh computer (replacing Eu0u) in mid&**", and the conumer Performa  product line (replacing 7C P84) in mid&**.6

7ater reviion of PCI added ne5 feature and performance improvement, including a .. /?< 

$6$ # tandard and $$ /?< PCI&9, and the adaptation of PCI ignaling to other form factor6

0oth PCI&9 6' and PCI&9 %6 are 'ack5ard compati'le 5ith ome PCI tandard6

!he PCI&4I= introduced the erial PCI +pre in %-6 3t the ame time they rechritened PCI  a Conventional PCI 6 4ince then, mother'oard manufacturer have included progreively fe5er

Conventional PCI lot in favor of the ne5 tandard6

$edit% &uto Configuration

PCI provide eparate memory and I12 port addre pace for the B. proceor family, .- and

$% 'it, repectively6 3ddree in thee addre pace are aigned 'y oft5are6 3 third addre

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pace, called the PCI Configuration 4pace, 5hich ue a fied addreing cheme, allo5

oft5are to determine the amount of memory and I12 addre pace needed 'y each device6 +ach

device can re@uet up to i area of memory pace or I12  port pace via it configuration paceregiter6

In a typical ytem, the firm5are (or operating ytem) @uerie all PCI 'ue at tartup time (viaPCI Configuration 4pace) to find out 5hat device are preent and 5hat ytem reource

(memory pace, I12 pace, interrupt line, etc6) each need6 It then allocate the reource andtell each device 5hat it allocation i6

!he PCI configuration pace alo contain a mall amount of device type information, 5hich

help an operating ytem chooe device driver for it, or at leat to have a dialogue 5ith a uera'out the ytem configuration6

8evice may have an on&'oard R2/ containing eecuta'le code for  B. or  P3&RI4C 

 proceor, an 2pen Firm5are driver, or an +FI driver6 !hee are typically neceary for device

ued during ytem tartup, 'efore device driver are loaded 'y the operating ytem6

In addition there are PCI "atency 'imers that are a mechanim for PCI #us()astering deviceto hare the PCI 'u fairly6 GFairG in thi cae mean that device 5onDt ue uch a large portion

of the availa'le PCI 'u 'and5idth that other device arenDt a'le to get needed 5ork done6 Eote,

thi doe not apply to PCI +pre6

G?o5 thi 5ork i that each PCI device that can operate in 'u&mater mode i re@uired toimplement a timer, called the 7atency !imer, that limit the time that device can hold the PCI

 'u6 !he timer tart 5hen the device gain 'u o5nerhip, and count do5n at the rate of the

PCI clock6 When the counter reache <ero, the device i re@uired to releae the 'u6 If no other

device are 5aiting for 'u o5nerhip, it may imply gra' the 'u again and tranfer moredata6G$;

$edit% Interrupts

8evice are re@uired to follo5 a protocol o that the interrupt line can 'e hared6 !he PCI 'uinclude four interrupt line, all of 5hich are availa'le to each device6 ?o5ever, they are not

5ired in parallel a are the other PCI 'u line6 !he poition of the interrupt line rotate 'et5een

lot, o 5hat appear to one device a the IE!3 line i IE!0 to the net and IE!C to theone after that6 4ingle&function device ue their IE!3 for interrupt ignaling, o the device load

i pread fairly evenly acro the four availa'le interrupt line6 !hi alleviate a common pro'lem

5ith haring interrupt6

PCI 'ridge ('et5een t5o PCI 'ue) map the four interrupt trace on each of their ide invarying 5ay6 4ome 'ridge ue a fied mapping, and in other it i configura'le6 In the general

cae, oft5are cannot determine 5hich interrupt line a deviceD IE!3 pin i connected to acro

a 'ridge6 !he mapping of PCI interrupt line onto ytem interrupt line, through the PCI hot 'ridge, i imilarly implementation&dependent6 !he reult i that it can 'e impoi'le to

determine ho5 a PCI deviceD interrupt 5ill appear to oft5are6 Platform&pecific 0I24 code i

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meant to kno5 thi, and et a field in each deviceD configuration pace indicating 5hich IRH it i

connected to, 'ut thi proce i not relia'le6

PCI interrupt line are level&triggered6 !hi 5a choen over edge&triggering in order to gain anadvantage 5hen ervicing a hared interrupt line, and for ro'utne: edge triggered interrupt

are eay to mi6

7ater reviion of the PCI pecification add upport for  meage&ignaled interrupt6 In thi

ytem a device ignal it need for ervice 'y performing a memory 5rite, rather than 'yaerting a dedicated line6 !hi alleviate the pro'lem of carcity of interrupt line6 +ven if

interrupt vector are till hared, it doe not uffer the haring pro'lem of level&triggered

interrupt6 It alo reolve the routing pro'lem, 'ecaue the memory 5rite i not unpredicta'lymodified 'et5een device and hot6 Finally, 'ecaue the meage ignaling i in&'and, it reolve

ome ynchroni<ation pro'lem that can occur 5ith poted 5rite and out&of&'and interrupt line6

PCI +pre doe not have phyical interrupt line at all6 It ue meage&ignaled interrupt

ecluively6

$edit% Conventional hard*are specifications

8iagram ho5ing the different key poition for $%&'it and .-&'it PCI card

!hee pecification repreent the mot common verion of PCI ued in normal PC6

• $$6$$ /?< clock  5ith ynchronou tranfer

•  peak tranfer rate of $$ /01 ($$ million  'yte per econd) for $%&'it 'u 5idth

($$6$$ /?< $% 'it B 'it1'yte K $$ /01)

• $%&'it 'u 5idth

• $%& or .-&'it memory addre pace (- giga'yte or . ea'yte)

• $%&'it I12 port pace

• %".& 'yte (per device) configuration pace

• "&volt ignaling

• reflected&5ave 5itching 

!he PCI pecification alo provide option for $6$# ignaling, .-&'it 'u 5idth, and .. /?<

clocking, 'ut thee are not commonly encountered outide of PCI&9 upport on erver

mother'oard6

!he PCI 'u ar'iter perform 'u ar'itration among multiple mater on the PCI 'u6 3nynum'er of 'u mater can reide on the PCI 'u, a 5ell a re@uet for the 'u6 2ne pair of

re@uet and grant ignal i dedicated to each 'u mater6

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$edit% Card +eying

3 PCI&9 =iga'it +thernet epanion card6 Eote 'oth "# and $6$# upport notche are preent6

!ypical PCI card preent either one or t5o key notche, depending on their ignaling voltage6

Card re@uiring $6$ volt have a notch ".6%mm from the front of the card (5here the eternalconnector are) 5hile thoe re@uiring " volt have a notch -6-Amm from the front of the card6

4o called G>niveral cardG have 'oth key notche and can accept 'oth type of ignal6

$edit% Connector pinout

!he PCI connector i defined a having .% contact on each ide of the edge connector , 'ut % or -

of them are replaced 'y key notche, o a card ha . or "B contact on each ide6 Pin i cloet

to the 'ackplate6 0 and 3 ide are a follo5, looking do5n into the mother'oard connector6-;";

.;

,-(bit PCI connector pinout

Pin Side # Side & Comments

. L%# !R4!

J!3= port pin (optional)

- !CM N%#

, =round !/4

/ !82 !8I

0 N"# N"#

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1 N"# IE!3

Interrupt line (open&drain)2 IE!0 IE!C

3 IE!8 N"#

4 PR4E! Reerved Pulled lo5 to indicate A6" or %" W po5er re@uired

.5 Reerved I2PWR N"# or N$6$#

.. PR4E!% Reerved Pulled lo5 to indicate A6" or " W po5er re@uired

.- =round =round

Mey notch for $6$#&capa'le card

., =round =round

./ Reerved $6$#au 4tand'y po5er  (optional)

.0 =round R4! 0u reet

.1 C7M I2PWR $$1.. /?< clock  

.2 =round =E! 0u grant from mother'oard to card

.3 R+H =round 0u re@uet from card to mother'oard

.4 I2PWR P/+ Po5er management event (optional)

-5 38$; 38$; 3ddre1data 'u (upper half)

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-. 38%*; N$6$#

-- =round 38%B;

-, 38%A; 38%.;

-/ 38%"; =round

-0 N$6$# 38%-;

-1 C10+$; I84+7

-2 38%$; N$6$#

-3 =round 38%%;

-4 38%; 38%;

,5 38*; =round

,. N$6$# 38B;

,- 38A; 38.;

,, C10+%; N$6$#

,/ =round FR3/+ 0u tranfer in progre

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,0 IR8 =round Initiator ready

,1 N$6$# !R8 !arget ready

,2 8+#4+7 =round !arget elected

,3 =round 4!2P !arget re@uet halt

,4 72CM N$6$# 7ocked tranaction

/5 P+RR 4/0C7M  SDONE Parity errorO 4/0u clock or Snoop done (obsolete)

/. N$6$# 4/083! SBO  4/0u data or Snoop bac!off (obsolete)

/- 4+RR =round 4ytem error  

/, N$6$# P3R +ven parity over 38$:; and C10+$:;

// C10+; 38"; 3ddre1data 'u (lo5er half)

/0 38-; N$6$#

/1 =round 38$;

/2 38%; 38;

/3 38; =round

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/4 /..+E =round 38*;

05 =round =round

Mey notch for "#&capa'le card

0. =round =round

0- 38B; C10+;

3ddre1data 'u (lo5er half)

0, 38A; N$6$#

0/ N$6$# 38.;

00 38"; 38-;

01 38$; =round

02 =round 38%;

03 38; 38;

04 I2PWR I2PWR  

15 3CM.- R+H.- For .-&'it etenionO no connect for $%&'it device6

1. N"# N"#

1- N"# N"#

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.-&'it PCI etend thi 'y an additional $% contact on each ide 5hich provide 38.$:$%;,

C10+A:-;, the P3R.- parity ignal, and a num'er of po5er and ground pin6

"egend

6round pin ero volt reference

Po*er pin 4upplie po5er to the PCI card

7utput pin 8riven 'y the PCI card, received 'y the mother'oard

Initiator output 8riven 'y the mater1initator, received 'y the target

I87 signal /ay 'e driven 'y initator or target, depending on operation

'arget output 8riven 'y the target, received 'y the initator1mater 

Input 8riven 'y the mother'oard, received 'y the PCI card

7pen drain /ay 'e pulled lo5 and1or ened 'y multiple card

9eserved  Eot preently ued, do not connect

/ot line are connected to each lot in parallel6 !he eception are:

• +ach lot ha it o5n R+H output to, and =E! input from the mother'oard ar'iter6

• +ach lot ha it o5n I84+7 line, uually connected to a pecific 38 line6

• !82 i daiy&chained to the follo5ing lotD !8I6 Card 5ithout J!3= upport mut

connect !8I to !82 o a not to 'reak the chain6

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• PR4E! and PR4E!% for each lot have their o5n pull&up reitor on the

mother'oard6 !he mother'oard may ('ut doe not have to) ene thee pin to determine

the preence of PCI card and their po5er re@uirement6

• R+H.- and 3CM.- are individually pulled up on $%&'it only lot6

• !he interrupt line IE!3 through IE!8 are connected to all lot in different order6(IE!3 on one lot i IE!0 on the net and IE!C on the one after that6)

 Eote:

• I2PWR i N$6$# or N"#, depending on the 'ackplane6 !he lot alo have a ridge in one

of t5o place 5hich prevent inertion of card that do not have the correponding keynotch, indicating upport for that voltage tandard6 >niveral card have 'oth key notche

and ue I2PWR to determine their I12 ignal level6

• !he PCI 4I= trongly encourage $6$# PCI ignaling,"; re@uiring upport for it ince

tandard reviion %6$,-; 'ut mot PC mother'oard ue the "# variant6 !hu, 5hile many

currently availa'le PCI card upport 'oth, and have t5o key notche to indicate that,there are till a large num'er of "#&only card on the market6

• !he /..+E pin i an additional ground on "# PCI 'ue found in mot PC

mother'oard6 Card and mother'oard that do not upport .. /?< operation alo

ground thi pin6 If all participant upport .. /?< operation, a pull&up reitor on the

mother'oard raie thi ignal high and .. /?< operation i ena'led6

• 3t leat one of PR4E! and PR4E!% mut 'e grounded 'y the card6 !he com'ination

choen indicate the total po5er re@uirement of the card (%"W, "W, or A6"W)6

• 402 and 482E+ are ignal from a cache controller to the current target6 !hey are not

initiator output, 'ut are colored that 5ay 'ecaue they are target input6

$edit% ariants

$edit% Conventional

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.-&'it PCI&9 epanion lot inide a Po5er /ac =-

• PCI 6, 5hich 5a merely a component&level pecification, 5a releaed on June %%, 

**%6

• PCI %6, 5hich 5a the firt to eta'lih tandard for the connector and mother'oard

lot, 5a releaed on 3pril $, **$6

• PCI %6, releaed on June , **", allo5 for .. /?< ignalling at $6$ volt ignal voltage

(peak tranfer rate of "$$/01), 'ut at $$ /?< 'oth " volt and $6$ volt ignal voltageare till allo5ed6 It alo added tranaction latency limit to the pecification6A; 

• PCI %6% Po5er rail to provide $6$ volt suppl" voltage are no5 mandatory6B; 

• PCI %6$ permit ue of $6$ volt and univeral keying, 'ut doe not allo5 " volt keyed add

in card6

• PCI $6 i the final official tandard of the 'u, completely removing "&volt capa'ility6

• /ini PCI i a form factor of PCI %6% for ue mainly inide laptop

• Card0u i a PC card form factor for $%&'it, $$ /?< PCI

• CompactPCI ue +urocard&i<ed module plugged into a PCI 'ackplane6

• PC1-&Plu i an indutrial 'u that ue the PCI ignal line 5ith different connector6

• Peripheral Component Interconect6

$edit% PCI(;

 #ain article$ PCI%& 

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PCI&9 i a high&performance variant of .-&'it PCI deigned for erver6 PCI&9 adapter and lot

are 'ack5ard&compati'le 5ith $%&'it PCI lot and adapter6

• PCI&9 6 increaed the maimum ignaling fre@uency to $$ /?< (peak tranfer rate of 

.. /01) and revie the protocol6

•

PCI&9 %6 permit a %.. /?< rate (peak tranfer rate of %$$ /01) and alo "$$ /?<rate (-%.. /01 Q $% the original PCI 'u), epand the configuration pace to -*.

 'yte, add a .&'it 'u variant (allo5ing maller lot 5here pace i tight), and allo5for 6" volt ignaling

$edit% Physical card dimensions

$edit% <ull(si=e card

!he original Gfull&i<eG PCI card i pecified a a height of A mm (-6% inche) and a depth of

$% mm (%6%B$ inche)6 !he height include the edge card connector6 ?o5ever, mot modern

PCI card are half&length or maller (ee 'elo5) and many modern PC cannot fit a full i<e card6

$edit% Card bac+plate

In addition to thee dimenion the phyical i<e and location of a cardD 'ackplate are alo

tandardi<ed6 !he 'ackplate i the part that faten to the card cage to ta'ili<e the card and alocontain eternal connector, o it uually attache in a 5indo5 o it i accei'le from outide

the computer cae6

!he card itelf can 'e a maller i<e, 'ut the 'ackplate mut till 'e full&i<e and properly located

o that the card fit in any tandard PCI lot6

$edit% Half(length e!tension card >de(facto standard

!hi i in fact the practical tandard no5 Q the maority of modern PCI card fit inide thi

length6

• Width: 6. inche ("6%- mm)

• 8epth: .6* inche (A"6%. mm)

• ?eight: -6% inche (.6.B mm)

$edit% "o*(profile >half(height card

!he PCI organi<ation ha defined a tandard for Glo5&profileG card, 5hich 'aically fit in the

follo5ing range:

• ?eight: 6-% inche ($.6A mm) to %6"$. inche (.-6- mm)

• 8epth: -6A% inche (*6* mm) to .6. inche (.A6.- mm)

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!he 'racket i alo reduced in height, to a tandard $6B inche (A*6% mm)6 !he maller 'racket

5ill not fit a tandard PC cae, 'ut 5ill fit in a %> rack&mount cae6 /any manufacturer upply

 'oth type of 'racket ('racket are typically cre5ed to the card o changing them i notdifficult)6

!hee card may 'e kno5n 'y other name uch a GlimG6

• 7o5 Profile PCI F3H 

• 7o5 Profile PCI 4pecification 

$edit% )ini PCI

/ini PCI Wi&Fi card !ype III0

)ini PCI 5a added to PCI verion %6% for ue in laptop, it ue a $%&'it, $$&/?< 'u 5ith po5ered connection ($6$ # onlyO "# i limited to m3) and upport for 'u matering and

8/36 !he tandard i<e for /ini PCI card i approimately 1- of their full&i<ed counterpart6

3 there i limited eternal acce to the card compared to dektop PCI card, there are

limitation on the function they may perform6

/iniPCI&to&PCI converter !ype III

/iniPCI and /iniPCI +pre card in comparion

/any /ini PCI device 5ere developed uch a Wi&Fi, Fat +thernet, 0luetooth, modem (often

Winmodem), ound card, cryptographic accelerator, 4C4I, I8+13!3, 43!3 controller and

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+dge mm mm)

$edit% 7ther physical variations

!ypically conumer ytem pecify GE PCI lotG 5ithout pecifying actual dimenion of thepace availa'le6 In ome mall form&factor ytem, thi may not 'e ufficient to allo5 even

Ghalf&lengthG PCI card to fit6 8epite thi limitation, thee ytem are till ueful 'ecaue many

modern PCI card are conidera'ly maller than half&length6

$edit% PCI bus transactions

PCI 'u traffic i made of a erie of PCI 'u tranaction6 +ach tranacation i made up of an

address phase follo5ed 'y one or more data phases6 !he direction of the data phae may 'e

from initator to target (5rite tranaction) or vice&vera (read tranaction), 'ut all of the data phae mut 'e in the ame direction6 +ither party may paue or halt the data phae at any point6

(2ne common eample i a lo5&performance PCI device that doe not upport 'urt tranaction,

and al5ay halt a tranaction after the firt data phae6)

3ny PCI device may initiate a tranaction6 Firt, it mut re@uet permiion from a PCI 'uar'iter on the mother'oard6 !he ar'iter grant permiion to one of the re@ueting device6 !he

initiator 'egin the addre phae 'y 'roadcating a $%&'it addre plu a -&'it command code,

then 5ait for a target to repond6 3ll other device eamine thi addre and one of them

repond a fe5 cycle later6

.-&'it addreing i done uing a %&tage addre phae6 !he initiator 'roadcat the lo5 $%

addre 'it, accompanied 'y a pecial Gdual addre cycleG command code6 8evice 5hich do

not upport .-&'it addreing can imply not repond to that command code6 !he net cycle, theinitiator tranmit the high $% addre 'it, plu the real command code6 !he tranaction operate

identically from that point on6 !o enure compati'ility 5ith $%&'it PCI device, it i for'idden to

ue a dual addre cycle if not neceary, i6e6 if the high&order addre 'it are all <ero6

While the PCI 'u tranfer $% 'it per data phae, the initiator tranmit a -&'it 'yte makindicating 5hich B&'it 'yte are to 'e conidered ignificant6 In particular, a maked 5rite mut

affect only the deired 'yte in the target PCI device6

$edit% PCI address spaces

3 PCI addre phae may pecify one of three type of addre: a memory addre, an I12

addre, or a configuration pace addre6 /emory addree are the highet performanceO they

may 'e .- 'it long, and upport cacheing and a greater variety of 'urt tranaction6 I12addree are for compati'ility 5ith the B. architectureD I12 port ytem6 3lthough the PCI 'u

pecification allo5 'urt tranaction in any addre pace, mot device only upport it for

memory addree6

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Finally, PCI configuration pace provide acce to %". 'yte of pecial configuration regiter

 per PCI device or function6 +ach PCI lot get it o5n configuration pace, and the regiter

there are ued to (among other thing) tell device 5hich memory and I12 pace addree theyhould repond to6 When a computer i firt turned on, all PCI device repond only to

configuration pace accee, 'ut the 0I24 aign addree to them6

If an addre i not aigned to any device, the PCI addre phae 5ill time out 5ithout getting

any repone, and the initiator 5ill a'ort the operation6 In cae of read, it i cutomary to upplyall&one data (FFFFFFFF) in thi cae6 PCI device therefore generally attempt to avoid uing

the all&one value in important tatu regiter, o that uch an error can 'e eaily detected 'y

oft5are6

$edit% PCI command codes

!here are . poi'le -&'it command code, and % of them are aigned6 With the eception of

the uni@ue dual addre cycle, the leat ignificant 'it of the command code indicate 5hether the

follo5ing data phae are a read (data ent from target to initiator) or a 5rite (data ent from aninitiator to target)6 PCI target mut eamine the command code a 5ell a the addre and not

repond to addre phae 5hich pecify an unupported command code6

!he command that refer to cache line depend on the PCI configuration pace cache line i<eregiter 'eing et up properlyO they may not 'e ued until that ha 'een done6

: Interrupt 3ckno5ledge

!hi i a pecial form of read cycle implicitly addreed to the interrupt controller, 5hichreturn an interrupt vector6 !he $%&'it addre field i ignored6 2ne poi'le

implementation i to generate an interrupt ackno5ledge cycle on an I43 'u uing a

PCI1I43 'u 'ridge6 !hi command i for  I0/ PC compati'ilityO if there i no Intel&tyleinterrupt controller on the PCI 'u, thi cycle need never 'e ued6

: 4pecial Cycle

!hi cycle i a pecial 'roadcat 5rite of ytem event that PCI card may 'e intereted

in6 !he addre field of a pecial cycle i ignored, 'ut it i follo5ed 'y a data phaecontaining a payload meage6 !he currently defined meage announce that the

 proceor i topping for ome reaon (e6g6 to ave po5er)6 Eo device ever repond to

thi cycleO it i al5ay terminated 5ith a mater a'ort after leaving the data on the 'u forat leat - cycle6

: I12 Read

!hi perform a read from I12 pace6 3ll $% 'it of the read addre are provided, o that

a device can (for compati'ility reaon) implement le than - 'yte 5orth of I12regiter6 If the 'yte ena'le re@uet data not 5ithin the addre range upported 'y the

PCI device (e6g6 a -&'yte read from a device 5hich only upport % 'yte of I12 addre

pace), it mut 'e terminated 5ith a target a'ort6 /ultiple data cycle are permitted, uinglinear (imple incrementing) 'urt ordering6

!he PCI tandard i dicouraging the ue of I12 pace in ne5 device, preferring that a

much a poi'le 'e done through main memory mapping6: I12 Write

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!hi perform a 5rite to I12 pace6

 ': Reerved

3 PCI device mut not repond to an addre cycle 5ith thee command code6: /emory Read

!hi perform a read cycle from memory pace6 0ecaue the mallet memory pace a

PCI device i permitted to implement i . 'yte, the t5o leat ignificant 'it of theaddre are not neededO e@uivalent information 5ill arrive in the form of 'yte elect

ignal6 !hey intead pecify the order in 5hich 'urt data mut 'e returned6 If a device

doe not upport the re@ueted order, it mut provide the firt 5ord and then diconnect6If a memory pace i marked a Gprefetcha'leG, then the target device mut ignore the

 'yte elect ignal on a memory read and al5ay return $% valid 'it6

: /emory Write

!hi operate imilarly to a memory read6 !he 'yte elect ignal are more important in a5rite, a unelected 'yte mut not 'e 5ritten to memory6

=enerally, PCI 5rite are fater than PCI read, 'ecaue a device can 'uffer the incoming

5rite data and releae the 'u fater6 For a read, it mut delay the data phae until the data

ha 'een fetched6 ': Reerved

3 PCI device mut not repond to an addre cycle 5ith thee command code6: Configuration Read

!hi i imilar to an I12 read, 'ut read from PCI configuration pace6 3 device mut

repond only if the lo5 'it of the addre pecify a function and regiter that itimplement, and if the pecial I84+7 ignal i aerted6 It mut ignore the high % 'it6

0urt read (uing linear incrementing) are permitted in PCI configuration pace6

>nlike I12 pace, tandard PCI configuration regiter are defined o that read never

ditur' the tate of the device6 It i poi'le for a device to have configuration paceregiter 'eyond the tandard .- 'yte 5hich have read ide effect, 'ut thi i rare6*; 

Configuration pace accee often have a fe5 cycle of delay in order to allo5 the

I84+7 line to ta'ili<e, 5hich make them lo5er than other form of acce6 3lo, aconfiguration pace acce re@uire a multi&tep operation rather than a ingle machine

intruction6 !hu, it i 'et to avoid them during routine operation of a PCI device6

: Configuration Write!hi operate analagouly to a configuration read6

: /emory Read /ultiple

!hi command i identical to a generic memory read, 'ut include the hint that a long

read 'urt 5ill continue 'eyond the end of the current cache line, and the target houldinternally prefetch a large amount of data6 3 target i al5ay permitted to conider thi a

ynonym for a generic memory read6

: 8ual 3ddre CycleWhen acceing a memory addre that re@uire more than $% 'it to repreent, the

addre phae 'egin 5ith thi command and the lo5 $% 'it of the addre, follo5ed 'y a

econd cycle 5ith the actual command and the high $% 'it of the addre6 PCI targetthat do not upport .-&'it addreing can imply treat thi a another reerved command

code and not repond to it6 !hi command code can only 'e ued 5ith a non&<ero high&

order addre 5ordO it i for'idden to ue thi cycle if not neceary6

: /emory Read 7ine

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!hi command i identical to a generic memory read, 'ut include the hint that the read

5ill continue to the end of the cache line6 3 target i al5ay permitted to conider thi a

ynonym for a generic memory read6: /emory Write and Invalidate

!hi command i identical to a generic memory 5rite, 'ut come 5ith the guarantee that

one or more 5hole cache line 5ill 'e 5ritten, 5ith all 'yte elect ena'led6 !hi i anoptimi<ation for 5rite&'ack cache nooping the 'u6 Eormally, a 5rite&'ack cache

holding dirty data mut interrupt the 5rite operation long enough 5rite it o5n dirty data

firt6 If the 5rite i performed uing thi command, the data to 'e 5ritten 'ack iguaranteed to 'e irrelevant, and can imply 'e invalidated in the 5rite&'ack cache6

!hi optimi<ation only affect the nooping cache, and make no difference to the target,

5hich may treat thi a a ynonym for the memory 5rite command6

$edit% PCI bus signals

PCI 'u tranaction are controlled 'y " main control ignal, % driven 'y the initiator of a

tranaction (FR3/+ and IR8), and $ driven 'y the target (8+#4+7, !R8, and4!2P)6 !here are t5o additional ar'itration ignal (R+H and =E!) 5hich are ued to o'tain

 permiion to initiate a tranaction6 3ll are active&lo5, meaning that the active or asserted  tate ia lo5 voltage6 Pull&up reitor on the mother'oard enure they 5ill remain high (inactive or

deasserted ) if not driven 'y any device, 'ut the PCI 'u doe not depend on the reitor to

chane the ignal levelO all device drive the ignal high for one cycle 'efore ceaing to drive the ignal6

$edit% Signal timing

3ll PCI 'u ignal are ampled on the riing edge of the clock6 4ignal nominally change on the

falling edge of the clock, giving each PCI device approimately one half a clock cycle to decideho5 to repond to the ignal it o'erved on the riing edge, and one half a clock cycle to

tranmit it repone to the other device6

!he PCI 'u re@uire that every time the device driving a PCI 'u ignal change, oneturnaround c"cle mut elape 'et5een the time the one device top driving the ignal and the

other device tart6 Without thi, there might 'e a period 5hen 'oth device 5ere driving the

ignal, 5hich 5ould interfere 5ith 'u operation6

!he com'ination of thi turnaround cycle and the re@uirement to drive a control line high for one

cycle 'efore ceaing to drive it mean that each of the main control line mut 'e high for a

minimum of % cycle 5hen changing o5ner6 !he PCI 'u protocol i deigned o thi i rarely alimitationO only in a fe5 pecial cae (nota'ly fat 'ack&to&'ack tranaction) i it neceary toinert additional delay to meet thi re@uirement6

$edit% &rbitration

3ny device on a PCI 'u that i capa'le of acting a a 'u mater  may initiate a tranaction 5ithany other device6 !o enure that only one tranaction i initiated at a time, each mater mut firt

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5ait for a 'u grant ignal, =E!, from an ar'iter located on the mother'oard6 +ach device ha a

eparate re@uet line R+H that re@uet the 'u, 'ut the ar'iter may GparkG the 'u grant ignal

at any device if there are no current re@uet6

!he ar'iter may remove =E! at any time6 3 device 5hich loe =E! may complete it

current tranaction, 'ut may not tart one ('y aerting FR3/+) unle it o'erve =E!aerted the cycle 'efore it 'egin6

!he ar'iter may alo provide =E! at any time, including during another materD tranaction68uring a tranaction, either FR3/+ or IR8 or 'oth are aertedO 5hen 'oth are deaerted,

the 'u i idle6 3 device may initiate a tranaction at any time that =E! i aerted and the 'u

i idle6

$edit% &ddress phase

3 PCI 'u tranaction 'egin 5ith an address phase6 !he initiator, eeing that it ha =E! and

the 'u i idle, drive the target addre onto the 38$:; line, the aociated command (e6g6memory read, or I12 5rite) on the C10+$:; line, and pull FR3/+ lo56

+ach other device eamine the addre and command and decide 5hether to repond a the

target 'y aerting 8+#4+76 3 device mut repond 'y aerting 8+#4+7 5ithin $ cycle6

8evice 5hich promie to repond 5ithin or % cycle are aid to have Gfat 8+#4+7G orGmedium 8+#4+7G, repectively6 (3ctually, the time to repond i %6" cycle, ince PCI device

mut tranmit all ignal half a cycle early o that they can 'e received three cycle later6)

 Eote that a device mut latch the addre on the firt cycleO the initiator i re@uired to remove the

addre and command from the 'u on the follo5ing cycle, even 'efore receiving a 8+#4+7

repone6 !he additional time i availa'le only for interpreting the addre and command after iti captured6

2n the fifth cycle of the addre phae (or earlier if all other device have medium 8+#4+7 or

fater), a catch&all Gu'tractive decodingG i allo5ed for ome addre range6 !hi i commonlyued 'y an I43 'u 'ridge for addree 5ithin it range (%- 'it for memory and . 'it for I12)6

2n the ith cycle, if there ha 'een no repone, the initiator may a'ort the tranaction 'y

deaerting FR3/+6 !hi i kno5n a master abort termination and it i cutomary for PCI 'u

 'ridge to return all&one data (FFFFFFFF) in thi cae6 PCI device therefore are generallydeigned to avoid uing the all&one value in important tatu regiter, o that uch an error can

 'e eaily detected 'y oft5are6

$edit% &ddress phase timing

  _ 0_ 1_ 2_ 3_ 4_ 5_  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/  ___  GNT# \___/XXXXXXXXXXXXXXXXXXX (GNT# Irrelevant after cycle a!!tarte"

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  _______  $%&'# \___________________  ___  &)*31+0, -------.___--------------- (&""re!! only val" for 1 cycle  ___ _______________ C/*3+0,# -------.___X_______________ (Coan" ten fr!t "ata a!e 6yteena6le!  _______________________  )78L# \___\___\___\___  $a!t 'e" 8lo9 8:6tractve  _ _ _ _ _ _ _  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/  0 1 2 3 4 5

2n the riing edge of clock , the initiator o'erve FR3/+ and IR8 'oth high, and =E!

lo5, o it drive the addre, command, and aert FR3/+ in time for the riing edge of clock6 !arget latch the addre and 'egin decoding it6 !hey may repond 5ith 8+#4+7 in time for

clock % (fat 8+#4+7), $ (medium) or - (lo5)6 4u'tractive decode device, eeing no other

repone 'y clock -, may repond on clock "6 If the mater doe not ee a repone 'y clock ", it

5ill terminate the tranaction and remove FR3/+ on clock .6

!R8 and 4!2P are deaerted (high) during the addre phae6 !he initiator may aert

IR8 a oon a it i ready to tranfer data, 5hich could theoretically 'e a oon a clock %6

$edit% @ual(cycle address

!o allo5 .-&'it addreing, a mater 5ill preent the addre over % conecutive cycle6 Firt, it

end the lo5&order addre 'it 5ith a pecial Gdual&cycle addreG command on theC10+$:;6 2n the follo5ing cycle, it end the high&order addre 'it and the actual

command6 8ual&addre cycle are for'idden if the high&order addre 'it are <ero, o device

5hich do not upport .-&'it addreing can imply not repond to dual cycle command6

  _ 0_ 1_ 2_ 3_ 4_ 5_ ;_  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/  ___  GNT# \___/XXXXXXXXXXXXXXXXXXXXXXX  _______  $%&'# \_______________________  ___ ___  &)*31+0, -------.___X___--------------- (Lo9 ten < 6t!  ___ ___ _______________ C/*3+0,# -------.___X___X_______________ ()&C ten act:al coan"  ___________________________

  )78L# \___\___\___\___  $a!t 'e" 8lo9  _ _ _ _ _ _ _ _  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/  0 1 2 3 4 5 ;

$edit% Configuration access

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3ddree for PCI configuration pace acce are decoded pecially6 For thee, the lo5&order

addre line pecify the offet of the deired PCI configuration regiter, and the high&order

addre line are ignored6 Intead, an additional addre ignal, the I84+7 input, mut 'e high 'efore a device may aert 8+#4+76 +ach lot connect a different high&order addre line to

the I84+7 pin, and i elected uing one&hot encoding on the upper addre line6

$edit% @ata phases

3fter the addre phae (pecifically, 'eginning 5ith the cycle that 8+#4+7 goe lo5) come a

 'urt of one or more data phases6 In all cae, the initiator drive active&lo5 'yte elect ignal

on the C10+$:; line, 'ut the data on the 38$:; may 'e driven 'y the initiator (on cae of5rite) or target (in cae of read)6

8uring data phae, the C10+$:; line are interpreted a active&lo5 b"te enables6 In cae of a

5rite, the aerted ignal indicate 5hich of the four 'yte on the 38 'u are to 'e 5ritten to the

addreed location6 In the cae of a read, they indicate 5hich 'yte the initiator i intereted in6

For read, it i al5ay legal to ignore the 'yte ena'le ignal and imply return all $% 'itOcachea'le memory reource are re@uired to al5ay return $% valid 'it6 !he 'yte ena'le are

mainly ueful for I12 pace accee 5here read have ide effect6

3 data phae 5ith all four C10+ line deaerted i eplicitly permitted 'y the PCI tandard, andmut have no effect on the target (other than to advance the addre in the 'urt acce in

 progre)6

!he data phae continue until 'oth partie are ready to complete the tranfer and continue to thenet data phae6 !he initiator aert IR8 (initiator read") 5hen it no longer need to 5ait,

5hile the target aert !R8 (taret read")6 Whichever ide i providing the data mut drive it

on the 38 'u 'efore aerting it ready ignal6

2nce one of the participant aert it ready ignal, it may not 'ecome un&ready or other5iealter it control ignal until the end of the data phae6 !he data recipient mut latch the 38 'u

each cycle until it ee 'oth IR8 and !R8 aerted, 5hich mark the end of the current

data phae and indicate that the ut&latched data i the 5ord to 'e tranferred6

!o maintain full 'urt peed, the data ender then ha half a clock cycle after eeing 'oth IR8and !R8 aerted to drive the net 5ord onto the 38 'u6

  0_ 1_ 2_ 3_ 4_ 5_ ;_ =_ >_ ?_  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/

  ___ _______ ___ ___ ___&)*31+0, ---.___XXXXXXXXX_______XXXXX___X___X___ (If a 9rte

  ___ ___ _______ ___ ___  &)*31+0, ---.___@@@.XXXXXXXX___X_______X___X___ (If a rea"  ___ _______________ _______ ___ ___ C/*3+0,# ---.___X_______________X_______X___X___ (':!t al9ay! 6e val"  _______________ A ___ A A A  I%)B# \_______/ \___________

___________________ A A A A

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  T%)B# \______________________________ A A A A

  )78L# \___________________________  ___ A A A A  $%&'# \___________________________________  _ _ _ _ _ A_ _ A_ A_ A_  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/  0 1 2 3 4 5 ; = > ?

!hi continue the addre cycle illutrated a'ove, auming a ingle addre cycle 5ith medium

8+#4+7, o the target repond in time for clock $6 ?o5ever, at that time, neither ide i ready

to tranfer data6 For clock -, the initiator i ready, 'ut the target i not6 2n clock ", 'oth are

ready, and a data tranfer take place (a indicated 'y the vertical line)6 For clock ., the target iready to tranfer, 'ut the initator i not6 2n clock A, the initiator 'ecome ready, and data i

tranferred6 For clock B and *, 'oth ide remain ready to tranfer data, and data i tranferred at

the maimum poi'le rate ($% 'it per clock cycle)6

In cae of a read, clock % i reerved for turning around the 38 'u, o the target i not permitted

to drive data on the 'u even if it i capa'le of fat 8+#4+76

$edit% <ast @S"A on reads

3 target that upport fat 8+#4+7 could in theory 'egin reponding to a read the cycle after the

addre i preented6 !hi cycle i, ho5ever, reerved for 38 'u turnaround6 !hu, a target maynot drive the 38 'u (and thu may not aert !R8) on the econd cycle of a tranaction6

 Eote that mot target 5ill not 'e thi fat and 5ill not need any pecial logic to enforce thi

condition6

$edit% nding transactions

+ither ide may re@uet that a 'urt end after the current data phae6 4imple PCI device that do

not upport multi&5ord 'urt 5ill al5ay re@uet thi immediately6 +ven device that do upport 'urt 5ill have ome limit on the maimum length they can upport, uch a the end of their

addrea'le memory6

!he initiator can mark any data phae a the final one in a tranaction 'y deaerting FR3/+ at

the ame time a it aert IR86 !he cycle after the target aert !R8, the final datatranfer i complete, 'oth ide deaert their repective R8 ignal, and the 'u i idle again6

!he mater may not deaert FR3/+ 'efore aerting IR8, nor may it aert FR3/+

5hile 5aiting, 5ith IR8 aerted, for the target to aert !R86

!he only minor eception i a master abort termination, 5hen no target repond 5ith8+#4+76 2'viouly, it i pointle to 5ait for !R8 in uch a cae6 ?o5ever, even in thi

cae, the mater mut aert IR8 for at leat one cycle after deaerting FR3/+6

(Commonly, a mater 5ill aert IR8 'efore receiving 8+#4+7, o it mut imply holdIR8 aerted for one cycle longer6) !hi i to enure that 'u turnaround timing rule are

o'eyed on the FR3/+ line6

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!he target re@uet the initiator end a 'urt 'y aerting 4!2P6 !he initiator 5ill then end the

tranaction 'y deaerting FR3/+ at the net legal opportunity6 If it 5ihe to tranfer more

data, it 5ill continue in a eparate tranaction6 !here are everal 5ay to do thi:

8iconnect 5ith data

If the target aert 4!2P and !R8 at the ame time, thi indicate that the target5ihe thi to 'e the lat data phae6 For eample, a target that doe not upport 'urt

tranfer 5ill al5ay do thi to force ingle&5ord PCI tranaction6 !hi i the motefficient 5ay for a target to end a 'urt6

8iconnect 5ithout data

If the target aert 4!2P 5ithout aerting !R8, thi indicate that the target 5iheto top 5ithout tranferring data6 4!2P i conidered e@uivalent to !R8 for the

 purpoe of ending a data phae, 'ut no data i tranferred6

Retry3 8iconnect 5ithout data 'efore tranferring any data i a retr", and unlike other PCI

tranaction, PCI initiator are re@uired to paue lightly 'efore continuing the operation6

4ee the PCI pecification for detail6!arget a'ort

 Eormally, a target hold 8+#4+7 aerted through the lat data phae6 ?o5ever, if a

target deaert 8+#4+7 'efore diconnecting 5ithout data (aerting 4!2P), thi

indiate a taret abort , 5hich i a fatal error condition6 !he initiator may not retry, andtypically treat it a a 'u error 6 Eote that a target may not deaert 8+#4+7 5hile

5aiting 5ith !R8 or 4!2P lo5O it mut do thi at the 'eginning of a data phae6

3fter eeing 4!2P, the initiator 5ill terminate the tranaction at the net legal opportunity, 'ut

if it ha already ignaled it deire to continue a 'urt ('y aerting IR8 5ithout deaertingFR3/+), it i not permitted to deaert FR3/+ until the follo5ing data phae6 3 target that

re@uet a 'urt end ('y aerting 4!2P) may have to 5ait through another data phae (holding4!2P aerted 5ithout !R8) 'efore the tranaction can end6

$edit% #urst addressing

For memory pace accee, the 5ord in a 'urt may 'e acceed in everal order6 !he

unneceary lo5&order addre 'it 38:; are ued to convey the initiatorD re@ueted order6 3target 5hich doe not upport a particular order mut terminate the 'urt after the firt 5ord6

4ome of thee order depend on the cache line i<e, 5hich i configura'le on all PCI device6

PCI burst ordering

&$$.% &$5% #urst order >*ith .1(byte cache line

7inear incrementing (C, , -, B, C, 666)

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Cacheline toggle (C, B, -, , C, B, 666)

Cacheline 5rap (C, , -, B, C, , 666)

Reerved (diconnect after firt tranfer)

If the tarting offet 5ithin the cache line i <ero, all of thee mode reduce to the ame order6

Cacheline toggle and cacheline 5rap mode are t5o form of critical&5ord&firt cache line

fetching6 !oggle mode 92R the upplied addre 5ith an incrementing counter6 !hi i the

native order for Intel -B. and Pentium proceor6 It ha the advantage that it i not neceary tokno5 the cache line i<e to implement it6

PCI verion %6 o'oleted toggle mode and added the cacheline 5rap mode,; 5here fetching

 proceed linearly, 5rapping around at the end of each cache line6 When one cache line icompletely fetched, fetching ump to the tarting offet in the net cache line6

 Eote that mot PCI device only upport a limited range of typical cache line i<eO if the cache

line i<e i programmed to an unepected value, they force ingle&5ord acce6

PCI alo upport 'urt acce to I12 and configuration pace, 'ut only linear mode i upported6

(!hi i rarely ued, and may 'e 'uggy in ome deviceO they may not upport it, 'ut not properlyforce ingle&5ord acce either6)

$edit% 'ransaction e!amples

!hi i the highet&poi'le peed -&5ord 5rite 'urt, terminated 'y the mater:

  0_ 1_ 2_ 3_ 4_ 5_ ;_ =_CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \

  ___ ___ ___ ___ ___&)*31+0, ---.___X___X___X___X___---.___

  ___ ___ ___ ___ ___ C/*3+0,# ---.___X___X___X___X___---.___  A A A A ___

  I%)B# DDDDDDDD\______________/ DDDDDA A A A ___  T%)B# DDDDDDDD\______________/ DDDDD

A A A A ___  )78L# DDDDDDDD\______________/ DDDDD  ___ A A A ___  $%&'# \_______________/ A DDDD\____

_ _ A_ A_ A_ A_ _ _CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \

  0 1 2 3 4 5 ; =

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2n clock edge , the initiator tart a tranaction 'y driving an addre, command, and aerting

FR3/+ !he other ignal are idle (indicated 'y SSS), pulled high 'y the mother'oardD pull&up

reitor6 !hat might 'e their turnaround cycle6 2n cycle %, the target aer 'oth 8+#4+7 and!R86 3 the initiator i alo ready, a data tranfer occur6 !hi repeat for three more cycle,

 'ut 'efore the lat one (clock edge "), the mater deaert FR3/+, indicating that thi i the

end6 2n clock edge ., the 38 'u and FR3/+ are undriven (turnaround cycle) and the othercontrol line are driven high for cycle6 2n clock edge A, another initiator can tart a different

tranaction6 !hi i alo the turnaround cycle for the other control line6

!he e@uivalent read 'urt take one more cycle, 'ecaue the target mut 5ait cycle for the 38

 'u to turn around 'efore it may aert !R8:

  0_ 1_ 2_ 3_ 4_ 5_ ;_ =_ >_CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \

  ___ ___ ___ ___ ___&)*31+0, ---.___---.___X___X___X___---.___

  ___ _______ ___ ___ ___

 C/*3+0,# ---.___X_______X___X___X___---.___  ___ A A A A ___  I%)B# DDDD\___________________/ DDDDD

___ _____ A A A A ___  T%)B# DDDD \______________/ DDDDD

___ A A A A ___  )78L# DDDD\___________________/ DDDDD  ___ A A A ___  $%&'# \___________________/ A DDDD\____

_ _ _ A_ A_ A_ A_ _ _  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \  0 1 2 3 4 5 ; = >

3 high&peed 'urt terminated 'y the target 5ill have an etra cycle at the end:

  0_ 1_ 2_ 3_ 4_ 5_ ;_ =_ >_CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \

  ___ ___ ___ ___ ___&)*31+0, ---.___---.___X___X___X___XXXX----

  ___ _______ ___ ___ ___ ___ C/*3+0,# ---.___X_______X___X___X___X___----  A A A A ___  I%)B# DDDDDDD\_______________________/

_____ A A A A _______  T%)B# DDDDDDD \______________/

________________ A ___  8TEF# DDDDDDD A A A \_______/

A A A A ___  )78L# DDDDDDD\_______________________/

___ A A A A ___  $%&'# \_______________________/ DDDD

_ _ _ A_ A_ A_ A_ _ _  CLK _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \  0 1 2 3 4 5 ; = >

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2n clock edge ., the target indicate that it 5ant to top (5ith data), 'ut the initiator i already

holding IR8 lo5, o there i a fifth data phae (clock edge A), during 5hich no data i

tranferred6

$edit% Parity

!he PCI 'u detect parity error, 'ut doe not attempt to correct them 'y retrying operationO it

i purely a failure indication6 0ecaue of thi, there i no need to detect the parity error 'efore itha happened, and the PCI 'u actually detect it a fe5 cycle later6 8uring a data phae,

5hichever device i driving the 38$:; line compute even parity over them and the

C10+$:; line, and end that out the P3R line one cycle later6 3ll acce rule and turnaroundcycle for the 38 'u apply to the P3R line, ut one cycle later6 !he device litening on the 38

 'u check the received parity and aert the P+RR (parity error) line one cycle after that6 !hi

generally generate a proceor interrupt, and the proceor can earch the PCI 'u for the device5hich detected the error6

!he P+RR line i only ued during data phae, once a target ha 'een elected6 If a parity errori detected during an addre phae (or the data phae of a 4pecial Cycle), the device 5hich

o'erve it aert the 4+RR (4ytem error) line6

+ven 5hen ome 'yte are maked 'y the C10+ line and not in ue, they mut till have some defined value, and thi value mut 'e ued to compute the parity6

$edit% <ast bac+(to(bac+ transactions

8ue to the need for a turnaround cycle 'et5een different device driving PCI 'u ignal, in

general it i neceary to have an idle cycle 'et5een PCI 'u tranaction6 ?o5ever, in ome

circumtance it i permitted to kip thi idle cycle, going directly from the final cycle of onetranfer (IR8 aerted, FR3/+ deaerted) to the firt cycle of the net (FR3/+ aerted,IR8 deaerted)6

3n initiator may only perform 'ack&to&'ack tranaction 5hen:

• they are 'y the ame initiator (or there 5ould 'e no time to turn around the C10+ and

FR3/+ line),

• the firt tranaction 5a a 5rite (o there i no need to turn around the 38 'u), and

• the initiator till ha permiion (from it =E! input) to ue the PCI 'u6

3dditional timing contraint may come from the need to turn around are the target control line, particularly 8+#4+76 !he target deaert 8+#4+7, driving it high, in the cycle follo5ing

the final data phae, 5hich in the cae of 'ack&to&'ack tranaction i the firt cycle of the

addre phae6 !he econd cycle of the addre phae i then reerved for 8+#4+7 turnaround,

o if the target i different from the previou one, it mut not aert 8+#4+7 until the thirdcycle (medium 8+#4+7 peed)6

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2ne cae 5here thi pro'lem cannot arie i if the initiator kno5 omeho5 (preuma'ly 'ecaue

the addree hare ufficient high&order 'it) that the econd tranfer i addreed to the ame

target a the previou one6 In that cae, it may perform 'ack&to&'ack tranaction6 3ll PCI targetmut upport thi6

It i alo poi'le for the target keep track of the re@uirement6 If it never doe fat 8+#4+7,they are met trivially6 If it doe, it mut 5ait until medium 8+#4+7 time unle:

• the current tranaction 5a preceded 'y an idle cycle (i not 'ack&to&'ack), or

• the previou tranaction 5a to the ame target, or

• the current tranaction 'egan 5ith a dou'le addre cycle6

!arget 5hich have thi capa'ility indicate it 'y a pecial 'it in a PCI configuration regiter, andif all target on a 'u have it, all initiator may ue 'ack&to&'ack tranfer freely6

3 u'tractive decoding 'u 'ridge mut kno5 to epect thi etra delay in the event of 'ack&to&

 'ack cycle in order to advertie 'ack&to&'ack upport6

$edit% 1/(bit PCI

his section e'plains onl" basic *+%bit PCI, the full PCI%&  protocol e'tension is much more

e'tensive-

!he PCI pecification include optional .-&'it upport6 !hi i provided via an etended

connector 5hich provide the .-&'it 'u etenion 38.$:$%;, C10+A:-;, and P3R.-6 (It alo provide a num'er of additional po5er and ground pin6)

/emory tranaction 'et5een .-&'it device may ue all .- 'it to dou'le the data tranfer rate6

 Eon&memory tranaction (including configuration and I12 pace accee) may not ue the .-& 'it etenion6 8uring a .-&'it 'urt, 'urt addreing 5ork ut a in a $%&'it tranfer, 'ut the

addre i incremented t5ice per data phae6 !he tarting addre mut 'e .-&'it alignedO i6e6

38% mut 'e 6 !he data correponding to the intervening addree (5ith 38% K ) i carried on

the upper half of the 38 'u6

!o initiate a .-&'it tranaction, the initiator drive the tarting addre on the 38 'u and aert

R+H.- at the ame time a FR3/+6 If the elected target can upport a .-&'it tranfer for thi

tranaction, it replie 'y aerting 3CM.- at the ame time a 8+#4+76 Eote that a target

may decide on a per&tranaction 'ai 5hether to allo5 a .-&'it tranfer6

If R+H.- i aerted during the addre phae, the initiator alo drive the high $% 'it of the

addre and a copy of the 'u command on the high half of the 'u6 If the addre re@uire .-

 'it, a dual addre cycle i till re@uired, 'ut the high half of the 'u carrie the upper half of theaddre and the final command code during 'oth addre phae cycleO thi allo5 a .-&'it target

to ee the entire addre and 'egin reponding earlier6

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If the initiator ee 8+#4+7 aerted 5ithout 3CM.-, it perform $%&'it data phae6 !he data

5hich 5ould have 'een tranferred on the upper half of the 'u during the firt data phae i

intead tranferred during the econd data phae6 !ypically, the initiator drive all .- 'it of data 'efore eeing 8+#4+76 If 3CM.- i miing, it may ceae driving the upper half of the data

 'u6

!he R+H.- and 3CM.- line are held aerted for the entire tranaction ave the lat data

 phae, and deaerted at the ame time a FR3/+ and 8+#4+7, repectively6

!he P3R.- line operate ut like the P3R line, 'ut provide even parity over 38.$:$%; and

C10+A:-;6 It i only valid for addre phae if R+H.- i aerted6 P3R.- i only valid for

data phae if 'oth R+H.- and 3CM.- are aerted6

$edit% Cache snooping >obsolete

PCI originally included optional upport for 5rite&'ack  cache coherence6 !hi re@uired upport

 'y cachea'le memory target, 5hich 5ould liten to t5o pin from the cache on the 'u, 482E+(noop done) and 402 (noop 'ackoff)6;

0ecaue thi 5a rarely implemented in practice, it 5a deleted from reviion %6% of the PCI

pecification,;"; and the pin re&ued for 4/0u acce in reviion %6$6-;

!he cache 5ould 5atch all memory accee, 5ithout aerting 8+#4+76 If it noticed an

acce that might 'e cached, it 5ould drive 482E+ lo5 (noop not done)6 3 coherence&upporting target 5ould avoid completing a data phae (aerting !R8) until it o'erved

482E+ high6

In the cae of a 5rite to data that 5a clean in the cache, the cache 5ould only have to invalidateit copy, and 5ould aert 482E+ a oon a thi 5a eta'lihed6 ?o5ever, if the cachecontained dirty data, the cache 5ould have to 5rite it 'ack 'efore the acce could proceed6 o it

5ould aert 402 5hen raiing 482E+6 !hi 5ould ignal the active target to aert 4!2P

rather than !R8, cauing the initiator to diconnect and retry the operation later6 In themeantime, the cache 5ould ar'itrate for the 'u and 5rite it data 'ack to memory6

!arget upporting cache coherency are alo re@uired to terminate 'urt 'efore they cro cache

line6

$edit% See also

• 7it of device 'and5idth (3 ueful liting of device 'and5idth that include PCI)

• 3dvanced /icrocontroller 0u 3rchitecture 

• Indutry 4tandard 3rchitecture (I43)

• +tended Indutry 4tandard 3rchitecture (+I43)

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• /icro Channel architecture (/C3)

•  Eu0u 

• orro II and orro III 

• #+43 7ocal 0u (#70)

• 3ccelerated =raphic Port (3=P)

• PCI +pre (PCIe) & the ucceor of PCI from %- on5ard

• PCI&9 

• PCI Configuration 4pace 

• 7it of computer tandard 

$edit% 9eferences

6 B GPCI +dition 3/8 ?8 -$" =raphic Card from ?I4G6 http:115556hidigital6com1un1product%&

---6html6 Retrieved %*&A&%A6

%6 B #70 5a deigned for -B.&'aed ytem, yet even the more generic PCI 5a to gain

 prominence on that platform6

$6 B GPCI 7atency !imer ?o5toG6 Reric6E+! 'y +ric 4eppanen6 %-&&-6

http:115556reric6net1linu1pciTlatency6html 6 Retrieved %B&A&A6

-6 S a b c  PCI Local Bus Specification. revision /-0, PCI 4pecial Interet =roup, %%&$&%*,

http:115556math6uni65roc6pl1Up&5yk-1o1pci%$6pdf , retrieved %*&A&A

"6 S a b c  PCI Local Bus Specification. revision 0-1, PCI 4pecial Interet =roup, %%&B&%,

http:11fpga&fa@6narod6ru1PCITRevT$6pdf , retrieved %*&A&A

.6 B PCI Connector Pinout 

A6 B  2P%340 PCI Local Bus Specification 5evision /-6 vs- /-1, Intel, **A&$,

http:115556intel6com1deign1chipet1applnot1%A$6htm  

B6 B http:115556pciig6com1pecification1conventional1conventionalTpci1%T%um%"6pdf  PCI&4I=Change 'et5een PCI %6 and PCI %6%

*6 B Roudier, =Vrard (%&&%B)6 linu'%!ernel mailin list 6 http:11marc6info1lKlinu&

kernelXmK.*BBBB"$%6 

6 B  PCI Local Bus Specification. revision /-6, PCI 4pecial Interet =roup, **"&.&,

http:11mipa6p6lod<6pl1do5nload10a<aWied<y1komunikaca1pci%6pdf , retrieved %*&A&

6 B  PCI Local Bus Specification. revision /-/, PCI 4pecial Interet =roup, **B&%&*,

http:115556ece6mtu6edu1faculty1'tdavi1coure1mtuTee$A$Tf-1paper1PCIT%%6pdf , retrieved

%*&A&A

8/11/2019 Conventional PCI

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$edit% !ternal lin+s

• PCI 4I= 

• PCI #endor and 8evice 7it 

• http:11pciid6ourceforge6net PCI I86

• PCI and PCI$% utilitie, Craig ?artD free5are PCI 4oft5are uite and I8 8ata'ae

• 7inu 5ith miniPCI card 

• PCI card dimenion diagram 

• PCI 'u pin&out and ignal 

• =E>17inu PCI device driver check page 

• 0rief overvie5 of PCI po5er re@uirement and compati'ility 5ith a nice diagram6 

• =ood diagram and tet on ho5 to recogni<e the difference 'et5een " volt and $6$ volt

lot6 

• 8ecoding PCI data and lpci output on 7inu hot 

hide; v Y d Y e

Computer bus  interconnection standards >*ired

)ain articles

Front&ide 'u D 0ack&ide 'u D /ultidrop 'u D 8aiy

chain D Control 'u D 3ddre 'u D 0u contention D +lectrical 'u7it of 'u 'and5idth

Computer bus standards >des+top

4& 'uE D 4/0u D H&0u D I43E D orro IIE D orro

IIIE D C3/3CE D F34!0>4E D 7o5 Pin Count D ?PPreciion 0u D +I43E D #/+ D #9I D  Eu0uE D 

!>R02channelE D /C3E D 40uE D #70E D PCI D P9I D

?P =4C 'u D CoreConnect D Infini0and D >P3 D PCI&9 D 3=P D PCI +pre D HuickPath Interconnect D 

?yper!ranport D more666

Computer bus standards >portable PC Card D +preCard

Storage bus standards

4!&".E D +48IE D 4/8 D Parallel 3!3 D 8/3 D 443 D 

?IPPIE D >40 /4C D 4erial 3!3 D 4erial 3!3 % D 

e43!3 D 4C4I D 4erial 3ttached 4C4I D Fi'reChannel D i4C4I

8/11/2019 Conventional PCI

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Peripheral bus standards

3pple 8ektop 0uE D ?I7E D /I8I D R4&%$% (erial

 port) D 8/9"%&3 D ."" >3R! D >3R! D +I31R4&

-%% D I+++&%B- (parallel port) D &Wire D IZC D 4PI D +I31R4&-B" D >40 D FireWire ($*-) D Fi're

Channel D >40 $6 D Camera 7ink  D +ternal PCI

+pre .

ehicle buses7IE D JAB D J"BA D F/4 D J*$* D C3E D #3E D 

FleRay D /24!

[ !hee tandard are o'olete and rarely ued Note$ interfaces are listed in speed ascendin order (rouhl"). the interface at the end of each section should 

be the fastest