Copyright © 1997 Altera Corporation 11/21/2015 P.1 Compilation is too Long Danny Mok Altera HK FAE...

04/20/23 P.1

Copyright © 1997 Altera Corporation

Compilation is too Long

Danny Mok

Altera HK FAE

([email protected])

04/20/23 P.2


Compilation Time

04/20/23 P.3


If you were

If you were Altera Software Engineer, what shall you do ?

Graphic Entry Graphic Compiler

Fitting

VHDL Entry VHDL Compiler

Graphic processor

VHDL processor

AHDL Entry

EDIF Entry

AHDL Compiler

EDIF Compiler

AHDL processor

EDIF processor

Need different Processor for different Design Entry

04/20/23 P.4


The Other better solution

Graphic Entry Graphic Compiler

VHDL Entry VHDL Compiler

AHDL Entry

EDIF Entry

AHDL Compiler

EDIF Compiler

AlteraInternal

DatabaseStructure

Fitting

04/20/23 P.5


Altera Max+Plus II Compiler

Involveall differentkind of Compilere.g. AHDL,VHDL, GraphicEDIF…..

Convert toAltera InternalDataBaseStructure

LogicOptimizee.g. Hierarchy SynthesisOne-Hot State MachineCarry/Cascade ChainMulti-level Synthesis….

Partition yourwhole designinto couplechips

Fit your designwithin Alteradevicee.g. Pin lock,Implement in EABClique,Timing parameter

Get the devicetiming parameterfor Real timeSimulation

Generate theProgram Fileto program thedevicee.g. SOF, POF..

04/20/23 P.6


How many time spend on each Module

Most of the time spend onthis TWO MODULES

04/20/23 P.7


What you can do for Netlist/Database Part Smart/Total Compiler can help

– Smart Compiler• if this is first time compilation, save the database

result for future compilation• if this is second compilation without modify of the

design, this step will be skipped– Total Compiler

• no matter the design has been modified or not, the system will go through this step again

Turn on Smart Compiler – first time need longer than Total Compiler– need more harddisk space to store the database

information– subsequence will need LESS TIME than Total Compiler

04/20/23 P.8


What you can do for Logic Synthesiser Part

Only turn on the Option which is useful– turn on XOR Synthesis under FLEX is useless– turn on Parallel Expanders under FLEX is useless

If you design file is EDIF which is already Optimize by Synopsys– you can min. time spend on the Max+Plus II Logic

Synthesizer• Select the WYSIWYG

– don’t forget to turn on Cascade/Carry Chain for FLEX device

– don’t forget to turn on the Parallel Expanders for MAX device

– you can also let Max+Plus II does further Logic Optimize for you

04/20/23 P.9


EDIF file input with different Synthesis Style

04/20/23 P.10


What you can do for Partitioner Part

If your design does not need to partition to different chip, this only takes couple seconds

If your design need to partition to different chip,– Max+Plus II automatic partitioning will take

longer time– You can save this time by doing Manual

Partition by either• use Assign Device Option• Physically split your design to different

design file

04/20/23 P.11


What you can do for Fitter Part

Basically, you can not do much on this part because this is the most valuable part of Max+Plus II

Avoid to do something which is meaningless– Clique something together but actually not relate to each

other– Only a portion of design need to run at high speed but tell

Max+Plus II that whole chip needs to run at that high speed– Lock some pin actually the PCB does not care when the I/O

pin is located

For 10K device– manually assign the module to EAB is much faster than turn

on Automatic Implement in EAB• because Max+Plus II will try all the module one by one

04/20/23 P.12


What you can do for Timing SNF Part

If you don’t need to do Real time Simulation, you can TURN OFF the Timing SNF Extractor

You can Select the Function SNF Extractor if you just need to do functional test of your design– there will be no POF or SOF… file generate if

this option selected

Optimize Timing SNF– if you find out that the Real Time Simulation is

too slow, you can turn this on (no big affect)

Linked SNF Extractor – use for Board Level Simulation support both

Real Time and Functional

04/20/23 P.13


What you can do for Assembler Part

You can do nothing on this part, but this part only take couple seconds

No big Due!!!!!!

04/20/23 P.14


More you can do

Max+Plus II is very CPU and RAM demand Software Increase you CPU speed definitely can help Increase you Local RAM (64Mbytes or 128Mbytes) will good for

100K gates design Bigger the Harddisk and faster Harddisk access time will be

bettter – Win95 will use Harddisk as the swap space (virtual RAM)– Bigger Usable Harddisk => bigger virtual RAM– Faster Harddisk access time => shorter virtual RAM access time

RAM is more important than CPU speed– 128Mbyte RAM+133Mhz CPU faster than 16Mbyte RAM+200Mhz CPU

04/20/23 P.15


OK --- But

OK, I know how to save some compilation time But, when I go to the Floorplan Editor and make placement modification, Max+Plus II need to re-compile again, it take

s……..o……… l……o……..n…….g time to do it Yes, you are right. Everytime you make an placement modification, Max+Plus II nee to go through

– Compiler Netlist Extractor

– Database Builder

– Logic Synthesiser

– Partitioner

– Fitter

– Timing SNF Extractor

– Assember

04/20/23 P.16


Something you can do/Something no choice What we can do ?

– Compiler Netlist Extractor

– Database Builder

– Logic Synthesizer

– Partitioner

– Fitter

– Timing SNF Extractor

– Assembler

04/20/23 P.17


Logic Synthesizer

If you just need to control the placement, there is no point to do the Logic Synthesis again

Can you turn off the Logic Synthesis ?– No. Because if you turn off the Logic Synthesis, you will get total different

compilation output -- don’t forget that Max+Plus II go through the whole compilation step (including Logic Synthesis)

If, there is something like……..

DesignFile

OptimizeLogic

SynthesisResult

Save theOptimize

LogicSynthesis

Result

Controlthe

LogicCell

Placement

Re-compilewiththe

OptimizeLogic

SynthesisResult

04/20/23 P.18


Smart Re-compiler can do this

04/20/23 P.19


If I change

If I do not modify my design but only change the speed grade– Do I need to wait for S…..O……. Long again

No !– The only thing you need to do is Turn On the Smart Recompile Option

– and Turn On the Maintain Current Synthesis Regardless of Device or Speed Grade Changes Option

04/20/23 P.20


Conclusion

Altera Max+Plus II is a smart tool If you know what you want, you may say some of

your compilation time– Turn On Smart Recompile Option

– Turn the Synthesis Style to WYSIWYG

– Turn On the Maintain Current Synthesis Regardless of Device or Speed Grades Changes

– Turn Off the SNF Timing Extractor if you do not need Timing Simulation

04/20/23 P.21


cont...

Altera Max+Plus II is the fastest FPGA/CPLD tools in the market now

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No TDC 10MHz 20MHz 30MHz 50MHz 60MHz 100MHz

Constraint (Fmax)

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MAX+PLUS II 8.0

M1420 LCELLS

04/20/23 P.22


cont..

3500 LCELLS

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No TDC 10MHz 20MHz 30MHz 50MHz 60MHz 100MHz

Constraint (Fmax)

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MAX+PLUS II 8.0

M1

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Copyright © 1997 Altera Corporation 11/21/2015 P.1 Compilation is too Long Danny Mok Altera HK FAE...

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