Copyright © 2005-2009 Silistix, all rights reserved

Glitch Sensitivity and Defense of

QDI NoC Links

Sean Salisbury

18 May 2009

18 May 2009 2

Outline

• Problem Causes

• Hazard Susceptibility

• Hazard Impact Analysis

• Various Defense Techniques

• Open Issues

• Questions

Copyright © 2005-2009 Silistix, all rights reserved

3

Problem Causes

• Smaller Vth:Supply margin due to reducing feature sizes and power supplies

• Crosstalk susceptibility increase as wires become taller, thinner and more densely packed

• Reflected in ITRS as decreasing wire length before significant induced voltage

Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

1-of-4 signaling example

• Handshake enters at left and flows through pipeline

C

C

C

C

C

C

C

C

C

0

0

0

0

0

0

0

0

00

0

0

0

0 00

111

C C C

0

11

1

1

1

0

1

1

1

00

11

0101

5Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

1-of-4 hazard example

• Data Corruption

• Data Loss

C

C

C

C

C

C

C

C

C

0

0

0

0

0

0

0

0

00

0

0

0

0 00

111

C C C

0

11

1

1

1

0

1

1

1

00

11

010

11

6Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

Hazard Analysis

7Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• 1-of-3 Pipeline

Hazard Analysis

8Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• positive input data glitch• Additional

symbol

• Symbol corruption

idata

Hazard Analysis

9Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• positive output data glitch• Temporary

lockout through iack

odata

Hazard Analysis

10Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• positive output acknowledge glitch• Temporary

lockout

oack

Hazard Analysis

11Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• positive input data glitch• Additional

symbol

• Symbol corruption

idata

Hazard Analysis

12Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• positive output ack glitch• Symbol lossoack

Hazard Analysis

13Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• negative output data glitch• Temporary

lockout

• Symbol corruption

• Symbol loss

odata

1-of-4 Hazard Impacts

Glitch Location Expected next activity Effect possible

+ ack New 1-of-n code Temporary lockout

+ ack Ack assertion Symbol loss (race through)

+ code-wire New 1-of-n code (same wire) Additional symbol

+ code-wire New 1-of-n code (different wire) Additional symbolIllegal symbol

+ code-wire Ack assertion Illegal symbol (2-of-n)

+ code-wire Ack deassertion Additional symbolIllegal symbol

- ack code rtz Temporary lockout

- ack Ack rtz Illegal symbol (race through)

- code-wire code rtz (0-of-n) Additional symbol

- code-wire Ack assertion No effect

- code-wire Ack deassertion Additional symbol

14Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

15

M-of-N

Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Reduce probability of glitch affect through– Fewer wires in communication

channel

– Increased probability hazard wire will be in transmitted code group

• Require multiple signal transitions for progression

Normally Closed Latch

16Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Early positive glitches in m-of-n codes ignored• Increased latency and area

17

Output Buffers

Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Eliminates all output data related glitch effects

• Effectively comes for free– Pipelines used on long

connections requiring additional drive

Pulse Filtered Inputs

18Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Glitch widths less than delay element filtered– Runtime changes possible with tunable delay elements

• Increased latency and area

Complementary Signaling

19Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Increases common mode rejection ratio

• Minimal impact on latency− Single gate delay

Normally Closed with Validity

20Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Same benefits of normally closed latch− Lower latency impact

Upstream Sensitivity Windowing

21Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Lockout additional input changes when data stored− Small timing window remains through completion detector

• Minimal area and latency impact

Downstream Sensitivity Windowing

22Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

• Lockout output acknowledge until data stored− Prevents deadlock if state-holding element used in

downstream completion detector

• Minimal area and latency impact

Results

• 11 different strategies– Area and performance initial focus (90nm)– 4 strong contenders

23Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

Open Issues

• Automated Hazard robustness calculation– Varying pulse voltage level– Varying pulse width/duration– Varying physical location on wire of pulse

• Defense technique overlay analysis– Determine best combination of techniques for

maximum protection at minimum cost

• Repeat all analysis at 65 and 40 nm nodes

24Copyright © 2005-2009 Silistix, all rights reserved18 May 2009

Questions

25Copyright © 2005-2009 Silistix, all rights reserved18 May 2009