Copyright Agrawal & Srivath Copyright Agrawal & Srivath s, 2007 s, 2007 Low-Power Design and Test, Lecture Low-Power Design and Test, Lecture 1 1 Low-Power Design and Low-Power Design and Test Test Introduction Introduction Vishwani D. Vishwani D. Agrawal Agrawal Auburn University, Auburn University, USA USA [email protected][email protected]Srivaths Ravi Srivaths Ravi Texas Instruments Texas Instruments India India [email protected][email protected]Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html
AcknowledgmentsAcknowledgments The lecturers wish to thank Synopsys (India) The lecturers wish to thank Synopsys (India)
and Sequence Design (India) for their help in and Sequence Design (India) for their help in preparation of demos for this course. Special preparation of demos for this course. Special thanks tothanks to
Low-power is a current need in VLSI design.Low-power is a current need in VLSI design. Learn basic ideas, concepts and methods.Learn basic ideas, concepts and methods. Gain experience with CAD tools.Gain experience with CAD tools.
ISSCC, Feb. 2001, KeynoteISSCC, Feb. 2001, Keynote“Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now.
“Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .”
Patrick P. Gelsinger Senior Vice PresidentGeneral ManagerDigital Enterprise Group INTEL CORP.
Low-Power DesignLow-Power Design Design practices that reduce Design practices that reduce
power consumption at least by one power consumption at least by one order of magnitude; in practice order of magnitude; in practice 50% reduction is often acceptable.50% reduction is often acceptable.
Low-power design methods:Low-power design methods: Algorithms and architecturesAlgorithms and architectures High-level and software techniquesHigh-level and software techniques Gate and circuit-level methodsGate and circuit-level methods Test powerTest power
State Encoding for a State Encoding for a CounterCounter Two-bit binary counter:Two-bit binary counter:
State sequence, 00 → 01 → 10 → 11 → 00State sequence, 00 → 01 → 10 → 11 → 00 Six bit transitions in four clock cyclesSix bit transitions in four clock cycles 6/4 = 1.5 transitions per clock6/4 = 1.5 transitions per clock
Two-bit Gray-code counterTwo-bit Gray-code counter State sequence, 00 → 01 → 11 → 10 → 00State sequence, 00 → 01 → 11 → 10 → 00 Four bit transitions in four clock cyclesFour bit transitions in four clock cycles 4/4 = 1.0 transition per clock4/4 = 1.0 transition per clock
Gray-code counter is more power Gray-code counter is more power efficient.efficient.
G. K. Yeap, Practical Low Power Digital VLSI Design, Boston:Kluwer Academic Publishers (now Springer), 1998.
FSM: Clock-GatingFSM: Clock-Gating Moore machine: Outputs depend only on Moore machine: Outputs depend only on
the state variables.the state variables. If a state has a self-loop in the state If a state has a self-loop in the state
transition graph (STG), then clock can be transition graph (STG), then clock can be stopped whenever a self-loop is to be stopped whenever a self-loop is to be executed.executed.
Sj
SiSk
Xi/Zk
Xk/Zk
Xj/Zk
Clock can be stopped when (Xk, Sk) combination occurs.
Bus Encoding for Reduced Bus Encoding for Reduced PowerPower Example: Four bit busExample: Four bit bus
0000 → 1110 has three transitions.0000 → 1110 has three transitions. If bits of second pattern are inverted, then 0000 → If bits of second pattern are inverted, then 0000 →
0001 will have only one transition.0001 will have only one transition.
Bit-inversion encoding for N-bit bus:Bit-inversion encoding for N-bit bus:
Power Consumption of Shift Power Consumption of Shift RegisterRegister
P = C’VDD2f/n
Degree of parallelism, n1 2 4
No
rma
lize
d p
ow
er
1.0
0.5
0.25
0.0
Deg. Of Deg. Of parallelisparallelis
mm
Freq Freq (MHz)(MHz)
Power Power ((μμW)W)
11 33.033.0 15351535
22 16.516.5 887887
44 8.258.25 738738
16-bit shift register, 2μ CMOS
C. Piguet, “Circuit and Logic LevelDesign,” pages 103-133 in W. Nebeland J. Mermet (ed.), Low PowerDesign in Deep SubmicronElectronics, Springer, 1997.
Books on Low-Power Design (1) Books on Low-Power Design (1) L. Benini and G. De Micheli, L. Benini and G. De Micheli, Dynamic Power Management Design Dynamic Power Management Design
Techniques and CAD ToolsTechniques and CAD Tools, Boston: Springer, 1998., Boston: Springer, 1998. T. D. Burd and R. A. Brodersen, T. D. Burd and R. A. Brodersen, Energy Efficient Microprocessor DesignEnergy Efficient Microprocessor Design, ,
Boston: Springer, 2002.Boston: Springer, 2002. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power Digital CMOS DesignLow-Power Digital CMOS Design, Boston: , Boston:
Springer, 1995.Springer, 1995. A. Chandrakasan and R. Brodersen, A. Chandrakasan and R. Brodersen, Low-Power CMOS DesignLow-Power CMOS Design, New York: IEEE , New York: IEEE
Press, 1998.Press, 1998. J.-M. Chang and M. Pedram, J.-M. Chang and M. Pedram, Power Optimization and Synthesis at Power Optimization and Synthesis at
Behavioral and System Levels using Formal MethodsBehavioral and System Levels using Formal Methods, Boston: Springer, , Boston: Springer, 1999.1999.
M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, M. S. Elrabaa, I. S. Abu-Khater and M. I. Elmasry, Advanced Low-Power Digital Advanced Low-Power Digital Circuit TechniquesCircuit Techniques, Boston: Springer, 1997., Boston: Springer, 1997.
R. Graybill and R. Melhem, R. Graybill and R. Melhem, Power Aware ComputingPower Aware Computing, New York: Plenum , New York: Plenum Publishers, 2002.Publishers, 2002.
S. Iman and M. Pedram, S. Iman and M. Pedram, Logic Synthesis for Low Power VLSI DesignsLogic Synthesis for Low Power VLSI Designs, , Boston: Springer, 1998.Boston: Springer, 1998.
J. B. Kuo and J.-H. Lou, J. B. Kuo and J.-H. Lou, Low-Voltage CMOS VLSI CircuitsLow-Voltage CMOS VLSI Circuits, New York: Wiley-, New York: Wiley-Interscience, 1999.Interscience, 1999.
J. Monteiro and S. Devadas, J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Computer-Aided Design Techniques for Low Power Sequential Logic CircuitsPower Sequential Logic Circuits, Boston: Springer, 1997., Boston: Springer, 1997.
S. G. Narendra and A. Chandrakasan, S. G. Narendra and A. Chandrakasan, Leakage in Nanometer CMOS Leakage in Nanometer CMOS TechnologiesTechnologies, Boston: Springer, 2005., Boston: Springer, 2005.
W. Nebel and J. Mermet, W. Nebel and J. Mermet, Low Power Design in Deep Submicron ElectronicsLow Power Design in Deep Submicron Electronics, , Boston: Springer, 1997.Boston: Springer, 1997.
Books on Low-Power Design Books on Low-Power Design (2)(2) N. Nicolici and B. M. Al-Hashimi, N. Nicolici and B. M. Al-Hashimi, Power-Constrained Testing of VLSI CircuitsPower-Constrained Testing of VLSI Circuits, ,
Boston: Springer, 2003.Boston: Springer, 2003. V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic and N. Nedovic, Digital Digital
System Clocking: High Performance and Low-Power AspectsSystem Clocking: High Performance and Low-Power Aspects, Wiley-IEEE, , Wiley-IEEE, 2005.2005.
M. Pedram and J. M. Rabaey, M. Pedram and J. M. Rabaey, Power Aware Design MethodologiesPower Aware Design Methodologies, Boston: , Boston: Springer, 2002.Springer, 2002.
J. M. Rabaey and M. Pedram, J. M. Rabaey and M. Pedram, Low Power Design MethodologiesLow Power Design Methodologies, Boston: , Boston: Springer, 1996.Springer, 1996.
S. Roudy, P. K. Wright and J. M. Rabaey, S. Roudy, P. K. Wright and J. M. Rabaey, Energy Scavenging for Wireless Energy Scavenging for Wireless Sensor NetworksSensor Networks, Boston: Springer, 2003., Boston: Springer, 2003.
K. Roy and S. C. Prasad, K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit DesignLow-Power CMOS VLSI Circuit Design, New York: , New York: Wiley-Interscience, 2000.Wiley-Interscience, 2000.
E. Sánchez-Sinencio and A. G. Andreaou, E. Sánchez-Sinencio and A. G. Andreaou, Low-Voltage/Low-Power Integrated Low-Voltage/Low-Power Integrated Circuits and Systems – Low-Voltage Mixed-Signal CircuitsCircuits and Systems – Low-Voltage Mixed-Signal Circuits, New York: IEEE , New York: IEEE Press, 1999.Press, 1999.
W. A. Serdijn, W. A. Serdijn, Low-Voltage Low-Power Analog Integrated CircuitsLow-Voltage Low-Power Analog Integrated Circuits, , Boston:Springer, 1995.Boston:Springer, 1995.
S. Sheng and R. W. Brodersen, S. Sheng and R. W. Brodersen, Low-Power Wireless Communications: A Low-Power Wireless Communications: A Wideband CDMA System DesignWideband CDMA System Design, Boston: Springer, 1998., Boston: Springer, 1998.
G. Verghese and J. M. Rabaey, G. Verghese and J. M. Rabaey, Low-Energy FPGAsLow-Energy FPGAs, Boston: springer, 2001., Boston: springer, 2001. G. K. Yeap, G. K. Yeap, Practical Low Power Digital VLSI DesignPractical Low Power Digital VLSI Design, Boston:Springer, 1998., Boston:Springer, 1998. K.-S. Yeo and K. Roy, K.-S. Yeo and K. Roy, Low-Voltage Low-Power SubsystemsLow-Voltage Low-Power Subsystems, McGraw Hill, , McGraw Hill,
Other Books Useful inOther Books Useful inLow-Power Design Low-Power Design
A. Chandrakasan, W. J. Bowhill and F. Fox, A. Chandrakasan, W. J. Bowhill and F. Fox, Design of High-Design of High-Performance Microprocessor Circuits, Performance Microprocessor Circuits, New York: IEEE New York: IEEE Press, 2001.Press, 2001.
N. H. E. Weste and D. Harris, N. H. E. Weste and D. Harris, CMOS VLSI Design, Third CMOS VLSI Design, Third EditionEdition, Reading, Massachusetts, Addison-Wesley, 2005., Reading, Massachusetts, Addison-Wesley, 2005.
S. M. Kang and Y. Leblebici, S. M. Kang and Y. Leblebici, CMOS Digital Integrated CMOS Digital Integrated CircuitsCircuits, New York: McGraw-Hill, 1996., New York: McGraw-Hill, 1996.
E. Larsson, E. Larsson, Introduction to Advanced System-on-Chip Introduction to Advanced System-on-Chip Test Design and OptimizationTest Design and Optimization, Springer, 2005., Springer, 2005.
J. M. Rabaey, A. Chandrakasan and B. Nikolić, J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Digital Integrated Circuits, Second EditionIntegrated Circuits, Second Edition, Upper Saddle , Upper Saddle River, New Jersey: Prentice-Hall, 2003.River, New Jersey: Prentice-Hall, 2003.
J. Segura and C. F. Hawkins, J. Segura and C. F. Hawkins, CMOS Electronics, How It CMOS Electronics, How It Works, How It FailsWorks, How It Fails, New York: IEEE Press, 2004. , New York: IEEE Press, 2004.
A 1-hot encoding is to be used for reducing the capacitive power consumption of an n-bit data bus. All n bits are assumed to be independent and random. Derive a formula for the ratio of power consumptions on the encoded and the un-coded buses. Show that n ≥ 4 is essential for the 1-hot encoding to be beneficial.
Reference: A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Boston: Kluwer Academic Publishers, 1995, pp. 224-225. [Hint: You should be able to solve this problem without the help of the reference.]
Solution: Bus EncodingSolution: Bus EncodingUn-coded bus: Two consecutive bits can be 00, 01, 10 and 11, each with a probability 0.25. Considering only the 01 transition, which draws energy from the supply, the probability of a data pattern consuming CV 2 energy on a wire is ¼. Therefore, the average per pattern energy for all n wires of the bus is CV 2n/4.
Encoded bus: Encoded bus contains 2n wires. The 1-hot encoding ensures that whenever there is a change in the data pattern, exactly one wire will have a 01 transition, charging its capacitance and consuming CV 2 energy. There can be 2n possible data patterns and exactly one of these will match the previous pattern and consume no energy. Thus, the per pattern energy consumption of the bus is 0 with probability 2–n, and CV 2 with probability 1 – 2–n. The average per pattern energy for the 1-hot encoded bus isCV 2(1 – 2–n).
Solution: Bus Encoding Solution: Bus Encoding (Cont.)(Cont.)
Power ratio = Encoded bus power / un-coded bus power
= 4(1 – 2–n)/n → 4/n for large nFor the encoding to be beneficial, the above power ratio should be less than 1. That is, 4(1 – 2–n)/n ≤ 1, or 1 – 2–n ≤ n/4, or n/4 ≥ 1 (approximately) → n ≥ 4.The following table shows 1-hot encoded bus power ratio as a function of bus width:n 4(1 – 2–n)/n n 4(1 – 2–n)/n
