Copyright Agrawal & Srivath Copyright Agrawal & Srivath s, 2007 s, 2007 Low-Power Design and Test, Lecture Low-Power Design and Test, Lecture 3 1 Test Test Logic-Level Power Logic-Level Power Estimation Estimation Vishwani D. Vishwani D. Agrawal Agrawal Auburn University, Auburn University, USA USA [email protected][email protected]Srivaths Ravi Srivaths Ravi Texas Instruments Texas Instruments India India [email protected][email protected]Hyderabad, July 30-31, 2007 http://www.eng.auburn.edu/~vagrawal/hyd.html
Circuit modeled as network of transistors, capacitors, Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources.resistors and voltage/current sources.
Node current equations using Kirchhoff’s current law.Node current equations using Kirchhoff’s current law. Average and instantaneous power computed from supply Average and instantaneous power computed from supply
voltage and device current.voltage and device current.
Analysis is accurate but expensiveAnalysis is accurate but expensive Used to characterize parts of a larger circuit.Used to characterize parts of a larger circuit.
Original references:Original references: L. W. Nagel and D. O. Pederson, “SPICE – Simulation L. W. Nagel and D. O. Pederson, “SPICE – Simulation
Program With Integrated Circuit Emphasis,” Memo ERL-Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. M382, EECS Dept., University of California, Berkeley, Apr. 1973.1973.
L. W. Nagel, L. W. Nagel, SPICE 2, A Computer program to Simulate SPICE 2, A Computer program to Simulate Semiconductor CircuitsSemiconductor Circuits, PhD Dissertation, University of , PhD Dissertation, University of California, Berkeley, May 1975.California, Berkeley, May 1975.
Switch-Level PartitioningSwitch-Level Partitioning Circuit partitioned into channel-connected Circuit partitioned into channel-connected
components for Spice characterization.components for Spice characterization. Reference: R. E. Bryant, “A Switch-Level Model and Reference: R. E. Bryant, “A Switch-Level Model and
Simulator for MOS Digital Systems,” Simulator for MOS Digital Systems,” IEEE Trans. IEEE Trans. ComputersComputers, vol. C-33, no. 2, pp. 160-177, Feb. 1984., vol. C-33, no. 2, pp. 160-177, Feb. 1984.
G1
G2
G3
Internal switching nodes not seen by logic simulator
Gate-Level Power AnalysisGate-Level Power Analysis Pre-simulation analysis:Pre-simulation analysis:
Partition circuit into channel connected Partition circuit into channel connected gate components.gate components.
Determine node capacitances from layout Determine node capacitances from layout analysis (accurate) or from wire-load analysis (accurate) or from wire-load model* (approximate).model* (approximate).
Determine dynamic and static power from Determine dynamic and static power from Spice for each gate.Spice for each gate.
Determine gate delays using Spice or Determine gate delays using Spice or Elmore delay model.Elmore delay model.
* Wire-load model estimates capacitance of a net by its pin-count. See Yeap, p. 39.
Elmore Delay ModelElmore Delay Model W. Elmore, “The Transient Response of Damped Linear W. Elmore, “The Transient Response of Damped Linear
Networks with Particular Regard to Wideband Amplifiers,” Networks with Particular Regard to Wideband Amplifiers,” J. J. Appl. PhysAppl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.., vol. 19, no.1, pp. 55-63, Jan. 1948.
Gate-Level Power Analysis Gate-Level Power Analysis (Cont.)(Cont.)
Run discrete-event (event-driven) logic Run discrete-event (event-driven) logic simulation with a set of input vectors.simulation with a set of input vectors.
Monitor the toggle count of each net and Monitor the toggle count of each net and obtain capacitive power dissipation:obtain capacitive power dissipation:
PPcapcap == ΣΣ CCk k V V 22 ff all nodes all nodes kk
Where:Where: CCkk is the total node capacitance being switched, as is the total node capacitance being switched, as
determined by the simulator.determined by the simulator. VV is the supply voltage. is the supply voltage. ff is the clock frequency, i.e., the number of vectors is the clock frequency, i.e., the number of vectors
Gate-Level Power Analysis Gate-Level Power Analysis (Cont.)(Cont.)
Monitor dynamic energy events at the Monitor dynamic energy events at the input of each gate and obtain internal input of each gate and obtain internal switching power dissipation:switching power dissipation:
PPintint = = ΣΣ ΣΣ E(g,e) E(g,e) F(g,e)F(g,e)
gates gates g g events events ee WhereWhere
E(g,e) = E(g,e) = energy of event energy of event ee of gate of gate gg, pre-, pre-computed from Spice.computed from Spice.
F(g,e) = F(g,e) = occurrence frequency of the eventoccurrence frequency of the event e e at gateat gate g, g, observed by logic simulationobserved by logic simulation..
Gate-Level Power Analysis Gate-Level Power Analysis (Cont.)(Cont.)
Monitor the static power dissipation state of Monitor the static power dissipation state of each gate and obtain the static power each gate and obtain the static power dissipation:dissipation:
PPstatstat = = ΣΣ ΣΣ P(g,s) T(g,s)/ TP(g,s) T(g,s)/ T gates gates gg states states ss
WhereWhere P(g,s) = P(g,s) = static power dissipation of gatestatic power dissipation of gate g g for statefor state s, s,
obtained from Spiceobtained from Spice.. T(g,s) = T(g,s) = duration of stateduration of state s s at gateat gate g, g, obtained from logic obtained from logic
simulationsimulation.. T = T = vector periodvector period..
Gate-Level Power AnalysisGate-Level Power Analysis Sum up all three components of power:Sum up all three components of power:
P = PP = Pcap cap + P+ Pintint + P + Pstatstat
References:References: A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. Proc.
International Workshop Low Power DesignInternational Workshop Low Power Design, 1994., 1994. J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan,
“Simulation Algorithms, Power Estimation and Diagnostics “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” in PowerMill,” Proc. PATMOSProc. PATMOS, 1995., 1995.
C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Design and Implementation of PowerMill,” Proc. Proc. International Symp. Low Power DesignInternational Symp. Low Power Design, 1995, pp. 105-109., 1995, pp. 105-109.
Static Signal ProbabilitiesStatic Signal Probabilities
Observe signal for interval Observe signal for interval t t 0 + 0 + t t 11 Signal is 1 for duration Signal is 1 for duration t t 11 Signal is 0 for duration Signal is 0 for duration t t 00 Signal probabilities:Signal probabilities:
p p 1 = 1 = t t 1/(1/(t t 0 + 0 + t t 1)1) p p 0 = 0 = t t 0/(0/(t t 0 + 0 + t t 1) = 1 – 1) = 1 – p p 11
Transition probabilities:Transition probabilities: T T 01 = 01 = p p 0 Prob{signal is 1 | signal was 0} = 0 Prob{signal is 1 | signal was 0} = p p 0 0 pp11 T T 10 = 10 = p p 1 Prob{signal is 0 | signal was 1} = 1 Prob{signal is 0 | signal was 1} = p p 1 1 p p
00 TT = = T T 01 + 01 + T T 10 = 2 10 = 2 p p 0 0 p p 1 = 2 1 = 2 p p 1 (1 – 1 (1 – p p 1)1)
Transition density: Transition density: TT = 2 = 2 p p 1 (1 – 1 (1 – p p 1)1)
Cause for Error and Cause for Error and CorrectionCorrection
Probability of transition is not independent Probability of transition is not independent of the present state of the signal.of the present state of the signal.
Determine probability Determine probability p p 01 of a 0→1 01 of a 0→1 transition.transition.
Recognize Recognize p p 01 ≠ 01 ≠ p p 0 × 0 × p p 11 We obtain We obtain p p 1 = (1 – 1 = (1 – p p 1)1)p p 01 + 01 + p p 1 1 p p 1111
Since Since p p 11 + 11 + p p 10 = 1, i.e., given that the 10 = 1, i.e., given that the signal was previously 1, its present value signal was previously 1, its present value can be either 1 or 0.can be either 1 or 0.
Therefore,Therefore, p p 0101
p p 1 = ──────1 = ────── p p 10 + 10 + p p 0101
This uniquely gives signal probability as a This uniquely gives signal probability as a function of transition probabilities.function of transition probabilities.
Power can be estimated if transition Power can be estimated if transition density is known for all signals.density is known for all signals.
Calculation of transition density Calculation of transition density requiresrequires Signal probabilitiesSignal probabilities Transition densities for primary inputs; Transition densities for primary inputs;
computed from vector statisticscomputed from vector statistics
Ref: K. P. Parker and E. J. McCluskey,“Probabilistic Treatment of General Combinational Networks,” IEEE Trans. on Computers, vol. C-24, no. 6, pp. 668-670, June 1975.
Numerical computation of signal Numerical computation of signal probabilities is accurate for fanout-probabilities is accurate for fanout-free circuits.free circuits.
C. E. Shannon, “A Symbolic Analysis of Relay C. E. Shannon, “A Symbolic Analysis of Relay and Switching Circuits,” and Switching Circuits,” Trans. AIEETrans. AIEE, vol. 57, , vol. 57, pp. 713-723, 1938.pp. 713-723, 1938.
When the output function is expanded When the output function is expanded about all reconverging input variables,about all reconverging input variables,
All cofactors correspond to fanout-free circuits.All cofactors correspond to fanout-free circuits. Signal probabilities for cofactor outputs can be Signal probabilities for cofactor outputs can be
calculated without error.calculated without error. A weighted sum of cofactor probabilities gives the A weighted sum of cofactor probabilities gives the
correct probability of the output.correct probability of the output.
For two reconverging inputs:For two reconverging inputs:f = xixj f(Xi=1, Xj=1) + xi(1-xj) f(Xi=1, Xj=0)f = xixj f(Xi=1, Xj=1) + xi(1-xj) f(Xi=1, Xj=0)
Signal probability for supergate output = 0.5 Prob{rec. signal = 1} + 1.0 Prob{rec. signal = 0} = 0.5 × 0.5 + 1.0 × 0.5 = 0.75
0.375
Reconv. signal
S. C. Seth and V. D. Agrawal, “A New Model for Computation ofProbabilistic Testability in Combinational Circuits,” Integration, the VLSI Journal, vol. 7, no. 1, pp. 49-75, April 1989.
Probability Calculation AlgorithmProbability Calculation Algorithm
Partition circuit into supergates.Partition circuit into supergates. Definition: A supergate is a circuit partition with a single Definition: A supergate is a circuit partition with a single
output such that all fanouts that reconverge at the output output such that all fanouts that reconverge at the output are contained within the supergate. are contained within the supergate.
Identify reconverging and non-reconverging Identify reconverging and non-reconverging inputs of each supergate.inputs of each supergate.
Compute signal probabilities from PI to PO:Compute signal probabilities from PI to PO: For a supergate whose input probabilities are knownFor a supergate whose input probabilities are known
Enumerate reconverging input statesEnumerate reconverging input states For each input state do gate by gate probability For each input state do gate by gate probability
computationcomputation Sum up corresponding signal probabilities, weighted by Sum up corresponding signal probabilities, weighted by
Boolean diff(Y, Xi) = 1 means that a path is sensitized from Boolean diff(Y, Xi) = 1 means that a path is sensitized from input Xi to output Y.input Xi to output Y.
Prob(Boolean diff(Y, Xi) = 1) is the probability of Prob(Boolean diff(Y, Xi) = 1) is the probability of transmitting a toggle from Xi to Y.transmitting a toggle from Xi to Y.
Probability of Boolean difference is determined from the Probability of Boolean difference is determined from the probabilities of cofactors of Y with respect to Xi. probabilities of cofactors of Y with respect to Xi.
∂YBoolean diff(Y, Xi) = ── = Y(Xi=1) ⊕ Y(Xi=0)
∂Xi
F. F. Sellers, M. Y. Hsiao and L. W. Bearnson, “Analyzing Errors with the Boolean Difference,” IEEE Trans. on Computers, vol. C-17, no. 7, pp. 676-683, July 1968.
Power ComputationPower Computation For each primary input, determine signal For each primary input, determine signal
probability and transition density for given vectors.probability and transition density for given vectors. For each internal node and primary output Y, find For each internal node and primary output Y, find
the transition density T(Y), using supergate the transition density T(Y), using supergate partitioning and the Boolean difference formula.partitioning and the Boolean difference formula.
Compute power,Compute power,
P =P = ΣΣ 0.5C0.5CYY V V22 T(Y) T(Y)
all Yall Y
where Cwhere CYY is the capacitance of node Y and V is is the capacitance of node Y and V is supply voltage.supply voltage.
Probability Waveform Probability Waveform MethodsMethods
F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A F. Najm, R. Burch, P. Yang and I. Hajj, “CREST – A Current Estimator for CMOS Circuits,” Current Estimator for CMOS Circuits,” Proc. IEEE Int. Proc. IEEE Int. Conf. on CADConf. on CAD, Nov. 1988, pp. 204-207., Nov. 1988, pp. 204-207.
C.-S. Ding, C.-S. Ding, et alet al., “Gate-Level Power Estimation using ., “Gate-Level Power Estimation using Tagged Probabilistic Simulation,” Tagged Probabilistic Simulation,” IEEE Trans. on CADIEEE Trans. on CAD, , vol. 17, no. 11, pp. 1099-1107, Nov. 1998.vol. 17, no. 11, pp. 1099-1107, Nov. 1998.
F. Hu and V. D. Agrawal, “Dual-Transition Glitch F. Hu and V. D. Agrawal, “Dual-Transition Glitch Filtering in Probabilistic Waveform Power Estimation,” Filtering in Probabilistic Waveform Power Estimation,” Proc. IEEE Great Lakes Symp. VLSIProc. IEEE Great Lakes Symp. VLSI, Apr. 2005, pp. , Apr. 2005, pp. 357-360.357-360.
F. Hu and V. D. Agrawal,F. Hu and V. D. Agrawal, “ “Enhanced Dual-Transition Enhanced Dual-Transition Probabilistic Power Estimation with Selective Probabilistic Power Estimation with Selective Supergate Analysis,” Supergate Analysis,” Proc. IEEE Int. Conf. Computer Proc. IEEE Int. Conf. Computer DesignDesign, Oct. 2005. pp. 366-369., Oct. 2005. pp. 366-369.
Problem 1Problem 1For equiprobable inputs analyze the 0→1 transition probabilities of all gates in the two implementations of a four-input AND gate shown below. Assuming that the gates have zero delays, which implementation will consume less average dynamic power?
Problem 1 SolutionProblem 1 SolutionGiven the primary input probabilities, P(A) = P(B) = P(C) = P(D) = 0.5, signal and transition (0→1) probabilities are as follows:
Signalname
Chain Tree
Prob(sig.= 1)
Prob(0→1)
Prob(sig.=1)
Prob(0→1)
E 0.2500 0.1875 0.2500 0.1875
F 0.1250 0.1094 0.2500 0.1875
G 0.0625 0.0586 0.0625 0.0586
Total transitions/vector
0.3555 0.4336
The tree implementation consumes 100×(0.4336 – 0.3555)/0.3555 = 22% more average dynamic power. This advantage of the chain structure may be somewhat reduced because of glitches caused by unbalanced path delays.
Problem 2Problem 2Assume that the two-input AND gates in Problem 1 each has one unit of delay. Find input vector pairs for each implementation that will consume the peak dynamic power. Which implementation consumes less peak dynamic power?
Problem 2 SolutionProblem 2 SolutionFor the chain structure, a vector pair {A B C D} = {1110},{1011} will produce four gate transitions as shown below.
Problem 2 Solution (Cont.)Problem 2 Solution (Cont.)The tree structure has balanced delay paths. So it cannot make more than 3 gate transitions. A vector pair {ABCD} = {1111},{1010} will produce three transitions as shown below.
A
B
C
D
E
F
G
A=11
B=10
E=10
C=11
D=10
F=10
G=10Time units
0 1 2 3
Therefore, just counting the gate transitions, we find that the chain consumes 100(4 – 3)/3 = 33% higher peak power than the tree.
