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PAGE 1 Coupled inductors on silicon for PwrSoC in the frame of PowerSwipe project Santosh Kulkarni*, Bruno Allard** *Microsystems Centre, Tyndall National Institute, University College Cork, Ireland **Ampere lab, INSA Lyon, France
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Page 1: Coupled inductors on silicon for PwrSoC in the frame of ...pwrsocevents.com/wp-content/.../2016-presentations/...PAGE 5 Summary of presentation Powerswipe’ integrated coupled inductors

PAGE 1

Coupled inductors on silicon for PwrSoC in the frame of

PowerSwipe project

Santosh Kulkarni*, Bruno Allard**

*Microsystems Centre, Tyndall National Institute, University College Cork, Ireland**Ampere lab, INSA Lyon, France

Page 2: Coupled inductors on silicon for PwrSoC in the frame of ...pwrsocevents.com/wp-content/.../2016-presentations/...PAGE 5 Summary of presentation Powerswipe’ integrated coupled inductors

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PowerSwipe Concept

2

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PowerSwipe Consortium Partners

3

First EU Funded programme on PwrSoC/PwrSiP

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Powerswipe-Demonstrators

Demo 1- Low Frequency dc-dc for Automotive

Demo 2- High Frequency dc-dc for multi-phase IVR applications

Passive LC

PCB Motherboard

SOC + LV-PMICPassive Interposer

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Summary of presentation

● Powerswipe’ integrated coupled inductors

● Design, Fabrication & Small Signal testing of ‘Loosely’ coupled inductor device

● Large Signal characterization of integrated coupled inductors

● Large signal Inductance, resistance, BH loop

● Impact of dc bias on magnetic material under test

● Summary

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HF DC-DC converter-Specs

●Achieve miniaturisation of power passives: ● Increased switching frequency of switched-mode DC-DC converter

(10-200 MHz)● Power passives footprint comparable to DC-DC converter IC (1 to 2 mm2)

PowerSwipe Motivation/Objectives

Design 1: Coupled inductor

Inductordesign

Freq. (MHz)

L (nH)

Coupling factor

Efficiency (magnetics)

Efficiency(IC)

Total efficiency

Coupled 100 45 ~0.4 90% 90,4% 81%

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L (nH) Core Length

Core Thickness

Copper width

Copper Thickness

DCR(Ohm)

Device Footprint

45 Coupled 0.95 mm 2 μm 40 μm 15 μm 0.282 1.25 mm2

45nH Coupled

PowerSwipe coupled inductor – Design & Fabrication

Device Cross-section

Coupled inductor prototype

Device Schematic

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Powerswipe coupled inductor – Small signal Characterization

Small signal testing: LCR meter & 4-probe Kelvin setup- INSA Lyon

ü Good frequency & current response

20% drop

Isat=650mA

Small signal testing: L vs DC bias-Tyndall

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Powerswipe coupled inductor – Coupling Measurement

• Two port VNA test for coupling

kmeasured= 0.38; kdesign= 0.4

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Large Signal Characterization Set-up

• Signal generator- Agilent E8257D• Power amplifier- Applied Research 25A250A• Current probe- Pearson current 2877• Voltage probe- Tap 1500

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Test circuit for coupled inductor measurement

Key issues with large signal testing set-up- Noise

- Use 4 wire measurement for the DUT- Error in amplitude & phase measurement

- Attenuation & time delay from current & voltage probes- Accurate compensation system to correct this skew

- Compensation is done through a measurement on a capacitor of known impedance

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Voltage & Current waveforms for Capacitor-Compensation

• Time lag @ 40MHz- 0.671 ns• Current attenuation- 0.895

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Inductance & DC resistance measurements

• Inductance (Self/Mutual) stays constant upto 60MHz• Resistance measurement shows a dramatic increase after 60MHz• This behaviour not consistent with small signal test data• Possible explanation- Voltage probes damaged

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DC bias measurements

• Voltage & Current waveforms including compensated current loops• Iac- 20mA; Ferquency- 60MHz• DC saturation current- 700 mA (consistent with small signal measurement)

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Large signal testing to plot BH loops @ different bias currents

- B value estimated using Faraday’s law- H value estimated using Ampere’s law

10 Hz

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Final circuit testing of Powerswipe coupled inductors

Inductor Passive Interposer

Switch

• Initial test on single phase discrete inductor with Interposer completed• Circuit testing of coupled inductor with VR ongoing at INSA, Lyon- Result

will be presented at future conferences

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Benchmarking Powerswipe VR performance

50

55

60

65

70

75

80

85

90

0 0.1 0.2 0.3 0.4

Effic

ienc

y (V

)

Load current (A)

110MHz, board

0 0.1 0.2 0.3 0.4Load current (A)

110MHz, interposer

1.2V 1.8V 2.4V

55

60

65

70

75

80

85

90

95

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Effic

ienc

y (%

)

VOUT/VIN

State of the art100 MHz cascode

100 MHz standard 10

20

40

100

200

500

Freq

uenc

y (M

Hz)

Active dieInterposer

16 nF

60 nH

11 nF11 nF

33 nF

11 nF

Ä Efficiency– Globally better on interposer– Slightly increased on-board for

low load current

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Summary• First EU funded project on PwrSoC/PwrSiP

• Target applications- Automotive & IVR

• Developed multiphase coupled inductors for IVR

• Racetrack coupled inductors designed using CAD tool• Fabricated using Tyndall’s Double Metal Layer process

• Small signal measurement in good agreement with design data• Developed large signal characterization system for measuring coupled

inductor performance

• Circuit level testing of VR’s ongoing

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Acknowledgements

Tyndall National Institute- Prof. Cian O’Mathuna, Dr. Paul McCloskey, Dr. Ningning Wang, Dr. Zoran Pavolvic, Ricky Anthony, Nicolas Cordero, Margaret Hegarty, Joe O’Brien, Declan Casey, James Rohan, Anne-Marie Kelleher, Graeme Maxwell

Lab Ampere, INSA, Lyon- Florian Neveu, Dr. Christian Martin

Funding- European Union for funding the work through FP7 (Project: PowerSwipe) under Grant 318529.

Universidad Carlos III de Madrid- Dr. Cristina Fernandez Herrero


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