Cours Nios Altera (1)

Designing with Nios II and SOPC Builder

A-MNL-NIOSII-04 1

Copyright 2005 Altera Corporation

Designing with Nios II and SOPC BuilderDesigning with Nios II and SOPC Builder

2 Copyright 2005 Altera Corporation

ObjectivesObjectives

Students will be able to: Describe the Nios II softcore processor Use the SOPC Builder tool to create complex systems Create and debug software for Nios II Program the development board Perform an RTL Simulation in ModelSim Tie in custom peripherals to the Avalon Switch Fabric

and utilize its multi-mastering capabilities Append a custom instruction to the Nios II instruction set


AgendaAgenda

Nios II Hardware Development Nios II Software Development Nios II Software Debug RTL Simulation Avalon Switch Fabric

Custom Peripherals Custom Instructions Multi-Masters and Direct Memory Access (DMA) Configuring the Development Board


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Intellectual Property (IP) Signal Processing Communications Embedded Processors

z Nios, Nios II

Devices (continued) Mercury Devices ACEX Devices FLEX Devices MAX Devices

Tools Quartus II Software Quartus II Web Edition SOPC Builder DSP Builder Nios II IDE

Devices Stratix II Stratix Stratix GX Cyclone II Cyclone MAX II

The Programmable Solutions CompanyThe Programmable Solutions Company


Nios II Hardware DevelopmentNios II Hardware Development


What is Nios II?What is Nios II? Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor

Developed Internally By Altera Harvard Architecture Royalty-Free

FPGA

- Nios II Plus All Peripherals Written In HDL- Can Be Targeted For All Altera FPGAs- Synthesis Using Quartus II Integrated Synthesis

Ava

lon

Switc

h Fa

bric UART

GPIO

Timer

SPI

SDRAMController

On-ChipROM

On-ChipRAM

Nios IICPUDebug C

ache


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Problem: Reduce Cost, Complexity & PowerProblem: Reduce Cost, Complexity & Power

Flash

SDRAM

CPU

DSP

I/O

I/O

I/O FPGA

I/O I/O I/O

CPU DSP

Solution: Replace External Devices with Programmable Logic

FPGA


Problem: Reduce Cost, Complexity & PowerProblem: Reduce Cost, Complexity & Power

Flash

SDRAM

Solution: Replace External Devices with Programmable Logic

CPU is a Critical Control Function Required for System-Level Integration

System On A Programmable Chip (SOPC)System On A Programmable Chip (SOPC)

FPGA


Synthesis- Translate Design into Device Specific Primitives- Optimization to Meet Required Area & Performance Constraints- Spectrum, Synplify, Quartus II

Design Specification

Place & Route- Map Primitives to Specific Locations Inside

Target Technology with Reference to Area &Performance Constraints

- Specify Routing Resources to Be Used

Design Entry/RTL Coding- Behavioral or Structural Description of Design

RTL Simulation- Functional Simulation (Modelsim,

Quartus II)- Verify Logic Model & Data Flow

(No Timing Delays)

LE M512

M4K I/O

FPGA Hardware Design FlowFPGA Hardware Design Flow

SOPC BuilderSOPC BuilderFunctional Simulation (Modelsim, Quartus II)Verify Logic Model & Data Flow (No Timing Delays)


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Timing Analysis- Verify Performance Specifications Were Met- Static Timing Analysis

Gate Level Simulation- Timing Simulation- Verify Design Will Work in Target Technology

tclk

FPGA Hardware Design FlowFPGA Hardware Design Flow

Test FPGA on PC Board- Program & Test Device on Board- Use SignalTap II for Debugging


Development Kits, Stratix & Cyclone EditionDevelopment Kits, Stratix & Cyclone Edition

8 MB Flash

Configuration Controller (MAX 7128AE)

10/100 Ethernet MAC/PHY & RJ-45 Connector

Compact Flash(Connector Mounted on Back)

16 MB SDRAM

Power Connector

Download /JTAG Debug ConnectorSerial RS-232

Connectors

1MB SRAM

Buttons LEDs 7 Segment

Expansion Prototype Connectors(40 I/O pins each)

Configuration Control

CPU Reset


32-BitNios II

ProcessorROM

(with Monitor)

On-Chip Off-Chip

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalon Sw

itch Fabric

Nios II Processor

Standard Design Block DiagramStandard Design Block Diagram

Tri-StateBridge

Leve

l Shi

fter

16MB Compact FLASH

SDRAMController

8MB FLASH

1MB SRAM

Ethernet MAC/PHY

32MB SDRAM

Tri-StateBridge

Compact Flash PIOs

Button PIO7-SegmentLED PIOLCD PIOLED PIO

General Purpose

Timer

Periodic Timer

UART

8 LEDsExpansion

Header J12

2 Digit Display

4 Momentary

buttons

ReconfigPIO


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User-DefinedInterface

MemoryInterface

On-ChipDebug Core

Off-ChipSoftware Trace

Memory

UART n

Timer n

SPI n

GPIO n

DMA n

Avalon Switch Fabric

Instr.

Data

AddressDecoder

InterruptController

Wait StateGeneration

Data inMultiplexer

DynamicBus Sizing

AvalonMaster/SlavePort

Interfaces

MasterArbitration

Nios II System ArchitectureNios II System ArchitectureUART 0

Timer 0

SPI 0

GPIO 0

DMA 0

MemoryInterface

User-DefinedInterface

Nios IICPU


Nios II Block DiagramNios II Block Diagram

ProgramController

&Address

Generation Instruction

Cache

clockreset

irq[31..0]Control

Registersctl0 to ctl4

ArithmeticLogic Unit

Hardware-Assisted

Debug Module

InterruptController

JTAG interfaceto Software

Debugger

Custom Instruction

Logic

ExceptionController

InstructionMasterPort

DataCache

DataMasterPort

GeneralPurpose

Registersr0 to r31

CustomI/O Signals

Nios II Processor Core


Nios II Processor ArchitectureNios II Processor Architecture

Classic Pipelined RISC Machine 32 General Purpose Registers 3 Instruction Formats 32-Bit Instructions 32-Bit Data Path Flat Register File Separate Instruction and Data Cache (configurable sizes) Branch Prediction 32 Prioritized Interrupts Custom Instructions JTAG-Based Hardware Debug Unit


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Nios II VersionsNios II VersionsNios II Processor Comes In Three ISA Compatible

Versions

Software Code is Binary Compatible

z No Changes Required When CPU is Changed

FAST: Optimized for Speed

STANDARD: Balanced for Speed and Size

ECONOMY: Optimized for Size


Binary Compatibility / Flexible PerformanceBinary Compatibility / Flexible Performance

600 7001200 14001400 - 1800Logic Usage (Logic Elements)

NoneNoneConfigurableData Cache

CustomInstructions

Instruction Cache

Branch Prediction

H/W Multiplier & Barrel Shifter

Pipeline

NoneConfigurableConfigurable

Up to 256

Dynamic

1 Cycle

6 Stage

Nios II /fFast

NoneStatic

EmulatedIn Software3 Cycle

None5 Stage

Nios II /eEconomy

Nios II /sStandard


Hardware Multiplier AccelerationHardware Multiplier Acceleration Nios II Economy version - No Multiply Hardware

Uses GNUPro Math Library to Implement Multiplier Nios II Standard - Full Hardware Multiplier

32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software only multiplier

Nios II Fast - Full Hardware Multiplier 32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software

only multiplier

3StandardMUL in Stratix

1FastMUL in Stratix

250None

Clock Cycles(32 x 32 32)

AccelerationHardware


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Hardware Multiplier SupportHardware Multiplier Support Stratix and Stratix II DSP Blocks Cyclone II Multiplier Blocks

Multiplication using 18 x 18 Multiplier Block Optional LE Implementation

Enables HW multiplier support for Cyclone Device Family Can also use in Stratix and Stratix II instead of DSP Blocks Mul, Shift, Rotate (~ 8 Clocks Per Mul) Eliminates need for DSP blocks for Nios II MUL


LicensingLicensing Nios II Delivered As Encrypted Megacore

Licensed Via Feature Line In Existing Quartus II License File Consistent With General Altera Megacore Delivery Mechanism Enables Detection Of Nios II In Customer Designs (Talkback)

No Nios II Feature Line (OpenCore Plus Mode) System Runs If Tethered To Host PC System Times Out If Disconnected from PC After ~ 1 hr

Nios II Feature Line (Active Subscriber) Subscription and New Dev Kit Customers Obtain Licenses From

www.altera.com Nios II CPU RTL Remains Encrypted

Nios II Source License Available Upon Request On Case-By-Case Basis Included With Purchase Of Nios II ASIC License


Requirements for Nios II DesignsRequirements for Nios II Designs

Quartus II 4.0 SP1 or higher Note: Quartus II now 4.2 available

Required for Nios II 1.1 No spaces in Quartus II project pathname Nios II license or a programming cable

tethered to PC to run the OpenCore Plus version of Nios II


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0

50

100

150

200

250

0 500 1000 1500 2000CPU Core Size

(Logic Elements)

Perf

orm

ance

(DM

IPS)

Nios II: Faster & SmallerNios II: Faster & Smaller

Results Based on Stratix II FPGA

Economy

Fast

Standard

50% Smaller

Over 2X Faster10% Smaller

4X Faster


Variation with FPGA DeviceVariation with FPGA Device

0

50

100

150

200

250

0 500 1000 1500 2000Logic Elements

DM

IPS

Stratix II Stratix Cyclone HC-Stratix

Fast

Economy

Standard


0

50

100

150

200

250

300

$0.00 $1.00 $2.00 $3.00 $4.00 $5.00Cost of CPU Logic

Perf

orm

ance

(DM

IPS)

Processor Cost vs. PerformanceProcessor Cost vs. Performance

Stratix

Cyclone

Stratix II

e

s

f

e

s

f

e

s

f

e

s

f

Cyclone II


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Nios II: Hard NumbersNios II: Hard NumbersNios II/f Nios II/s Nios II/e

Stratix II 200 DMIPS @ 175MHz1180 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 2S10-C5

90 DMIPS @ 175MHz800 LEs

4K Icache, No DcacheStratix 2S10-C5


No Icache, No DcacheStratix 2S10-C5

Stratix 150 DMIPS @ 135MHz1800 LEs1 of 8 DSP4K Icache, 2K DcacheStratix 1S10-C5


4K Icache, No DcacheStratix 1S10-C5


No Icache, No DcacheStratix 1S10-C5

Cyclone 100 DMIPS @ 125MHz1800 LEs

4K Icache, 1K DcacheCyclone 1C4-C6


2K Icache, No DcacheCyclone 1C4-C6


No Icache, No DcacheCyclone 1C4-C6

* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f 1.15 DMIPS / MHz)


SOPC BuilderSOPC Builder

Altera, Partner & User Cores Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic

(ie. custom peripherals) Web-Based IP Deployment

Over 60 Cores Available

Today

System Contents Page


Clock-Domain CrossingClock-Domain Crossing

Auto-Insertion of Clock-Domain Crossing Logic FIFO Where Posted-Reads Are Supported Simple Metastability-Hardening Otherwise

Unlimited Number of Clock Domains Added, Named & Managed Through GUI

New in4.2


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Nios II ExceptionsNios II Exceptions

All exceptions processed by code at exception location Provided by HAL system library

Supported Exception TypeszSoftware Exceptions

Software Traps (currently, not implemented) Unimplemented instructions

Maintains compatibility between Nios II coreszHardware Interrupts

32 Level-sensitive interrupts are supported.zMore exceptions will be supported as features are

added.


Hardware designer selects which Nios II version to use when creating system

Nios II CPU Configured in SOPC BuilderNios II CPU Configured in SOPC Builder


Selecting JTAG Debug CoreSelecting JTAG Debug Core Configuration is chosen when hardware designer selects

appropriate Nios II processor core


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SOPC BuilderSOPC Builder More cpu Settings Page


SOPC Builder System Generation PageSOPC Builder System Generation Page


SOPC Builder Produces a .PTF FileSOPC Builder Produces a .PTF File

Text file that records SOPC Builder edits Describes Nios II System Used by software development tools


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Integrate SOPC Builder O/P in Quartus IIIntegrate SOPC Builder O/P in Quartus II Integrate SOPC Builder block symbol to Quartus II schematic

(as shown below) and compile design Or, instantiate top module into your HDL design and compile


Memory Interfaces EPCS Serial Flash

Controller On-Chip

z RAM, ROM Off-Chip

z SRAMz CFI Flash

LCD Display

New Peripherals for Nios II New Peripherals for Nios II System ID Peripheral

Used to Ensure Hardware/ Software Version Synchronization

Simple 2 read-only register peripheral containing hardware ID tags.z Register 1 contains random

numberz Register 2 contains time and date

when system was generated in SOPC Builder

Can be checked at runtime to ensure that the software to be downloaded matches the hardware image


JTAG UART Single JTAG

Connection For:z Device Configurationz Flash Programmingz Code Download z Debugz Target STDIO (printing)

New Peripherals for Nios II New Peripherals for Nios II Compact Flash Interface

Mass Storage Supportz True IDE Modez Compact Flash Mode

Software Supportsz Low-Level APIz MicroC/OS-II File System

Supportz CLinux File System

Support

Supported through www.niosforum.com


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Project DirectoriesProject Directories Hardware

HDL Source & Netlist db - Quartus project

database

Software Application source code Library files

Simulation Testbench Automatically generated

test memory and vectors


Exercise 1A Basic Nios II DesignExercise 1A Basic Nios II Design

35 mins35 mins


Nios II Software DevelopmentNios II Software Development


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SOPC Builder FlowSOPC Builder FlowSOPC Builder GUI

Connect Blocks

Processor Library Custom Instructions

Peripheral Library Select & Configure Peripherals, IP

IP Modules

Configure Processor

C Header files

Custom Library

Peripheral Drivers

Compiler, Linker, Debugger

Software Development

User Code

Libraries

RTOS

GNU Tools

Generate

HDL Source Files

Testbench

Synthesis &Fitter

User Design

Other IP Blocks

Hardware Development

Quartus II

On-ChipDebug

Software TraceHard Breakpoints

SignalTap II

AlteraPLD

JTAG,Serial, orEthernet

ExecutableCode

HardwareConfiguration

File Verification& Debug

NiosNios II IDEII IDE


Nios II IDE (Integrated Development Environment)*Nios II IDE (Integrated Development Environment)*

Leading Edge Software Development Tool

Target Connections Hardware (JTAG) Instruction Set Simulator ModelSim-Altera Software

Advanced Hardware Debug Features Software and Hardware

Break Points, Data Triggers, Trace

Flash Memory Programming Support

* Based on Eclipse Project


Opening the Nios II IDEOpening the Nios II IDELaunch the Launch the NiosNios II IDE from II IDE from the SOPC Builder or from the SOPC Builder or from the Windows Start menuthe Windows Start menu


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Nios II IDENios II IDE

List of Open Projects

Terminal window

File Viewer Window

(for C code, C++, and assembly*)

Note: C++ files must have extension .cppIn-line assembly code offset by asm();


Nios II IDE C/C++ Projects/NavigatorNios II IDE C/C++ Projects/Navigator

Lists all open projects

Displays source files associated with project

List all open and closed projects

Allows you to drag and drop new files into existing projects


Creating a C/C++ ApplicationCreating a C/C++ ApplicationFile > New > Project


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Creating a C/C++ ApplicationCreating a C/C++ Application

Link to a System Library- Select a pre-existing library- Or create a new library


This Creates Two Software Projects- Application and System Library ProjectThis Creates Two Software Projects- Application and System Library Project

System Library Project- contains system

header file, etc.

Application Project- contains application source code

Drivers Directory- contains all device drivers DO NOT DELETE !


Application and System Library ProjectsApplication and System Library Projects

Application Projects build executables System Library Projects contain interface to the

hardware Nios II device drivers (Hardware Abstraction

Layer) Optional RTOS (MicroC/OS-II) Optional software components (Lightweight

TCP/IP stack, Read Only Zip File System)


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Other New Project OptionsOther New Project Options System Library

Only creates system library project Build C applications upon this later

Advanced C/C++ Project Disable automatic tool features like

makefile and linker script generation User defines own instead

Managed Library Project Facilitates software library

development Enables you to associate pre-

compiled code into an Application Project

Tool writes makefile for included files


Importing Projects into the IDEImporting Projects into the IDE


Project Properties Project Properties Both Application and System Library have

Properties pages


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System Library OptionsSystem Library OptionsSelect RTOSSpecify stdio devicesPartition the memory map


Software CompilationSoftware Compilation

To compile a software application, highlight your project and select Build Project from the Projects menu


Directory Structure After CompilationDirectory Structure After Compilation

Application Project System Library Project


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Nios II Host Platform SupportNios II Host Platform Support

Windows XP Linux Host Support (RedHat 7.3, 8.0,

Enterprise 3) Nios II GNU Toolchain (Compiler, Binary Utilities) Nios II Instruction Set Simulator Nios II Debugger Nios II IDE USB Blaster Linux driver


Hardware Abstraction LayerHardware Abstraction Layer A lightweight runtime environment for Nios II software

Provides a level of abstraction between application code and low level hardware

HAL libraries are generated by Nios II IDE A HAL contains:

device drivers initialization software file system stdio, stderr


Hardware Abstraction LayerHardware Abstraction Layer Provides generic device models for classes of

peripherals common in embedded systems eg. timers, I/O peripherals, etc.

Gives a consistent POSIX-like API, regardless of underlying hardware

Make programming as familiar as possible to software engineers who may not be familiar with the specific peripheral architectures

z ANSI C (through the Newlib library)z UNIX style interface (i.e. POSIX like)z Altera extensions where standards dont exist or were

inappropriate (watch for the alt_* extension)


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Hardware Abstraction LayerHardware Abstraction Layer Key features of the HAL

Uses standard interfaces where appropriate Close integration with the Newlib ANSI C library

z http://sources.redhat.com/newlib/ Device drivers automatically configured to match the PTF Drivers initialised before main() Scalable (i.e. packs down small) Clear distinction between system and application software


Nios II Processor System Hardware

DeviceDriver

DeviceDriver

DeviceDriver

Nios II HAL: Runtime LibraryNios II HAL: Runtime Library

_exit()close()closedir()fstat()getpid()gettimeofday()ioctl()isatty()kill()lseek()

open()opendirread()readdir()rewinddir()sbrk()settimeofday()stat()usleep()wait()write()

HAL API

HAL API

C Standard LibraryC Standard Library

User Program

The HAL UNIX Style Functions are the glue between the C library and the device drivers


HAL File SystemHAL File System

/

/dev /mnt

/dev/jtag_uart0 /dev/lcd0 /mnt/rozipfs

/mnt/rozipfs/myfile1

/mnt/rozips/myfile21 Device names match those set in SOPC builder. Can only access nodes, not directories. All paths must be absolute (no current directory)


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Familiar File/Device AccessFamiliar File/Device Access

ANSI C:fp = fopen (/dev/lcd0, w); fprintf (fp, %s, msg);

UNIX Style:fd = open (/dev/lcd0, O_WRONLY); write (fd, msg, strlen(msg));

Newlib also supports C++ streams:ofstream ofp(/dev/lcd0, ios::out); ofp


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system.h - examplesystem.h - example

.

.

./** button_pio configuration**/

#define BUTTON_PIO_NAME "/dev/button_pio"#define BUTTON_PIO_TYPE "altera_avalon_pio"#define BUTTON_PIO_BASE 0x00920830#define BUTTON_PIO_IRQ 2#define BUTTON_PIO_HAS_TRI 0#define BUTTON_PIO_HAS_OUT 0#define BUTTON_PIO_HAS_IN 1#define BUTTON_PIO_CAPTURE 1#define BUTTON_PIO_EDGE_TYPE "ANY"#define BUTTON_PIO_IRQ_TYPE "EDGE"#define BUTTON_PIO_FREQ 50000000

/** system configuration**/

#define ALT_SYSTEM_NAME "std_1s10ES"#define ALT_CPU_NAME "cpu"#define ALT_CPU_ARCHITECTURE "altera_nios2"#define ALT_DEVICE_FAMILY "STRATIX"#define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES#define ALT_STDIN "/dev/jtag_uart"#define ALT_STDOUT "/dev/jtag_uart"#define ALT_STDERR "/dev/jtag_uart"#define ALT_CPU_FREQ 50000000#define ALT_CPP_CONSTRUCTORS#define ALT_IRQ_BASE NULL

.

.

.

Defines system settings and peripheral configurations: Replaces excalibur.h (from Nios)


HAL ReferencesHAL References Each HAL project references library routines and drivers for the

components included in your Nios II system


Reading/Writing Hardware in NiosReading/Writing Hardware in Nios

Nios Classic used volatile pointers to access hardware e.g. volatile *my_led_pointer = (int *) LED_BASE;

Volatiles will no longer provide access to hardware registers in Nios II They are still used to tell the compiler not to

optimize code No longer disable cache access


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Reading/Writing Hardware in Nios IIReading/Writing Hardware in Nios II

Instead use I/O macros to access hardware I/O macros bypass the cache for hardware accesses They set bit 31 of address bus high (ie. control bit) IORD(BASE, REGNUM)

zReads value at register REGNUM offset from base address BASE

IOWR(BASE,REGNUM,DATA)zWrites DATA to register

REGNUM offset from base address BASE

REGNUM = 0REGNUM = 0REGNUM = 1REGNUM = 1REGNUM = 2REGNUM = 2REGNUM = 3REGNUM = 3REGNUM = 4REGNUM = 4

BASE+2BASE+2

BASEBASE

BASE+4BASE+4


Header Files for Nios II PeripheralsHeader Files for Nios II Peripherals

Each Nios II peripheral has specific read/write macros for each register Example: UART (altera_avalon_uart_regs.h)

#define IORD_ALTERA_AVALON_UART_RXDATA(base) IORD(base, 0) #define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IOWR(base, 0, data)

#define IORD_ALTERA_AVALON_UART_TXDATA(base) IORD(base, 1)#define IOWR_ALTERA_AVALON_UART_TXDATA(base, data) IOWR(base, 1, data)

#define IORD_ALTERA_AVALON_UART_STATUS(base) IORD(base, 2) #define IOWR_ALTERA_AVALON_UART_STATUS(base, data) IOWR(base, 2, data)


Data CacheData Cache

Memory space is mirrored (e.g. 2GB addressable space) Upper half is uncacheable Lower half is cacheable

All data variables are cached by default This can cause memory coherency issues if

you are using a DMA controller in your design.


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Data CacheData Cache

To bypass the cache and maintain coherency Flush before any DMA transfers using

alt_dcache_flush() Allocate uncacheable regions on the heap

using alt_uncached_malloc() Remap an existing area of memory using

alt_remap_uncached() Use ldio or stio instructions in assembly


InterruptsInterrupts

HAL API for ISRs - Functions alt_irq_register()

z Associates interrupt with your ISR function. alt_irq_disable_all()

z Disables all IRQs alt_irq_enable_all()

z Enables all IRQs alt_irq_interruptible()

z Used in ISR function body. Allows ISR to be interrupted by higher priority IRQs.

alt_irq_non_interruptible()z Used to make ISRs uninterruptible (default behavior).


Write your ISR(Follow prototype)

Register your ISRUsing alt_irq_register()

alt_irq_register ( alt_u32 id, void* context,

void (*irq_handler) (void*, alt_u32));

Sample Usage:alt_irq_register ( 3, &some_data, sample_isr);

sample_isr ( void* context, alt_u32 id);

id == irq number (0 to 31)context == void pointer to data produced by or consumed by ISR.

HAL API for ISRs - Useful InfoHAL API for ISRs - Useful Info


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HAL API for ISRs - Useful InfoHAL API for ISRs - Useful Info Creating interruptible code blocks in ISR

Use alt_irq_interruptible() & alt_irq_non_interruptible() Do not use standard C library or RTOS software functions inside

ISR that may pend for any reason Eg. printf()

Keep it simple. Use ISR to trigger execution of slow processing tasks outside of

interrupt context Do NOT perform these tasks within ISR

References: Exception Handling Chapter in Nios II Software Developers

Handbook


Nios II OS / RTOS SupportNios II OS / RTOS Support

Extensive drivers and middlewear,

inc USB, IPSec, etc.

Many, inc. FAT and

JFFS2

Incl.YesOpen Source (GPL)

CLinux

GUI, SNMPRMON, SPAN

Opt.Opt.OSEKITRON

YesATI/Mentor** Nucleus Plus

C/OS-II Support

Sockets APIIP, ICMP, UDP, TCP

YesOpen Source* Lightweight IPTCP/IP Stack

KROSTechnologies

Micrium

Provider

POSIX

RTCA/DO-178B

Standards

GUIFlash

Other

Opt.

Opt.

File System

Yes

Yes

SourceCode

Opt.

Opt.

TCP/IPStack

KROS

* MicroC/OS-II

Product

* Included in Nios II Development Kits** Evaluation Version Included in Nios II Development Kits


Nios II OS / RTOS Support (cont)Nios II OS / RTOS Support (cont)

PPP, SNMP, HTTP

Opt.Opt.ITRONYesMiSPONORTi

USB, MailHTTP

Opt.Opt.ITRONYeseSOLPrKERNELv4

USBOpt.Opt.YesExpress LogicThreadX

Extensive drivers and middleware, inc. USB, IPSec, etc.

FAT, JFFS2,

ROMFS, RAMFS

Incl.POSIZ, uITRON, EL/IX

YesOpen Source (GPL with excpetion)

eCos

Provider Standards OtherFile System

SourceCode

TCP/IPStack

Product



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Nios II MicroC/OS-II Nios II MicroC/OS-II

Single-seat developers license included for free with Nios II kits

Licensing fee reqd when you productize your system Full source code included Preemptive operating system Small footprint

Code Size (min 5KB, max 20KB) Data Space (min 1KB, max 5KB)

Supports Semaphores, and Mailboxes for task synchronization


Nios II MicroC/OS-II Nios II MicroC/OS-II


Lightweight IP for MicroC/OS-IILightweight IP for MicroC/OS-II Plugs is being replaced with the

Lightweight IP TCP/IP stack in Nios II Open source TCP/IP Stack

Supports TCP, UDP, IP, DHCP and ARP Optimised for size (Very simple web server < 500k) LWIP supports IPv4 and IPv6, but we support IPv4 ONLY Based on version 0.6.3

Integrated into Nios II IDE Used in conjunction with uC/OS-II Sockets API available Free Licensing

Modified BSD License, must keep the copyright notice and display it in the product documentation


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LWIP - InstantiationLWIP - Instantiation

Available as a Software Component


LWIP ConfigurationLWIP Configuration


Nios to Nios II ConversionNios to Nios II Conversion

Hardware Must be Ported Add Nios II processor and connections in

SOPC Builder

Software can be Used in Legacy SDK Mode or Ported to HAL

See AN350 for full details


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Legacy Software Support Minimal if any Code Changes Required No Access to Nios II IDE Only supported for Standard and Economy

cores New peripherals (CFI flash, sysid, etc) not

supported New software components (uC/OSII, LWIP)

not supported



Full Port from Nios to Nios II Requires C code changes No GERMS support Provides access HAL, uC/OSII, LWIP



Porting Process: Replace header files

z Example: system.h for excalibur.h Change API calls from SDK to HAL syntax

z Example: nr_delay() is replaced with usleep() Replace data types (int, char, etc..) with Nios II data

types (alt_u32, alt_u8, etc) Replace hardware access pointers with macros

z Example: my_pio->data = 1 is replaced with IOWR_ALTERA_AVALON_PIO_DATA(PIO_BASE,1)

Take into account that *volatile pointers no longer prevent data from being cached


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Software Run & DebugSoftware Run & Debug


Software Run and DebugSoftware Run and Debug

Nios II Run Nios II IDE JTAG Debugger Nios II ISS Nios II Console Third Party tools


Running Code On A TargetRunning Code On A Target Nios II IDE can be used to download code to target board


A-MNL-NIOSII-04 30


Running Code On A TargetRunning Code On A Target Download messages, stdout and stdin appear in console

window


Nios II IDE Run OptionsNios II IDE Run Options

Nios II IDE > Run > Run


System ID Peripheral RevisitedSystem ID Peripheral Revisited When downloading code to a target, Nios II IDE computes

expected System ID peripheral values from PTF file If computed ID values do not match System ID variables stored on

the target board then an error is flagged Generally, to fix this you should recompile your hardware


A-MNL-NIOSII-04 31


Nios II IDE JTAG DebuggerNios II IDE JTAG Debugger

Requirements Must have JTAG

Debug Core enabled in CPU


Nios II IDE Debug PerspectiveNios II IDE Debug Perspective

DoubleDouble--click to click to add breakpointsadd breakpoints

Basic Debug Run Controls

Stack View

Active Debug Sessions

Variables

Registers

Signals

Memory View


Nios II IDE DebuggerNios II IDE Debugger

Step ReturnStep ReturnStep OverStep OverStep IntoStep IntoStep with FiltersStep with Filters

DisconnectDisconnectTerminateTerminateSuspendSuspend

ResumeResume

Run last ConfigurationRun last ConfigurationDebug last ConfigurationDebug last Configuration


A-MNL-NIOSII-04 32


Nios II IDE DebuggerNios II IDE Debugger

Standard debug windows memory registers Variables breakpoints expressions signals


Nios II IDE Multi-Processor LaunchNios II IDE Multi-Processor Launch Mechanism to Quickly Launch Multiple Debuggers and

Connect Them to Multiple Nios II Processors Run > Debug > Nios II Multiprocessor Collection

Accelerates Debug Cycle for Multi-Processor Systems


Nios II IDE: DebuggerNios II IDE: Debugger Debug each CPU by selecting its program thread


A-MNL-NIOSII-04 33


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Instruction Set Simulators are software models of an Instruction Set Architecture Generally used to debug code if a target board

is unavailable. Provides limited models of a few hardware

peripherals.z TimerzUARTzMemory (flash, SDRAM, on-chip, etc)


Nios II Instruction Set SimulatorNios II Instruction Set Simulator

Launch an ISS Debug session from the Run Menu


Nios II Instruction Set SimulatorNios II Instruction Set Simulator Targets .elf file to ISS and opens debugger

Application can then be debugged as normal


A-MNL-NIOSII-04 34


Customizing Views in the IDE GUICustomizing Views in the IDE GUI

You can turn windows on or off in either the Run or Debug Perspective


Nios II SDK ShellNios II SDK Shell

SDK shell is still provided with Nios II Used to support legacy SDK flow (eg.. n2b, n2c) as

well as other general commands Can launch terminal to interface to JTAG UARTs

nios2-terminal And compile code

nios2-elf-gcc


Nios II / FS2 ConsoleNios II / FS2 Console

Command line debugger


A-MNL-NIOSII-04 35


Nios II Console LaunchNios II Console Launch

FS2 Console Launches then minimizes


Nios II ConsoleNios II Console Allows for hardware

breakpoints and trace data 2 HWBPs and 16 Frames of On-

Chip Trace Included

Displays C Source, Assembly, Mixed


Nios II Debug SolutionsNios II Debug Solutions

Supports FS2 ISA-Nios/TDebuggerSophia Systems

Watchpoint

JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace , FS2 Trace Probe

IDE / DebuggerATI Mentor** code|lab

ISA-Nios/T

* Nios II IDE

Product

External Trace Capture, Timestamp, Complex Data Triggers

JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe

Features

JTAG Trace Probe

IDE / Debugger

Description

First Silicon Solution (FS2)

Altera

Provider



A-MNL-NIOSII-04 36


Upgrades from FS2Upgrades from FS2(see www.fs2.com for details)

YesNoNoTrace (Timestamp)FS2 Black Box(USB, Ethernet)

AlteraUSB/B Blaster

AlteraUSB/B Blaster

Target Connection

YesYesNoTrace (Load / Store)

See FS2See FS2IncludedCost

On-Chip128 Frames

4

4

FS2 S/W Upgrade

Trace (PC)

Data Triggers

Hardware Execution Breakpoints

Feature

Off-Chip128K Frames

On-Chip16 Frames

42

42

FS2 H/W Upgrade

Nios II IDE


FS2 System Analyzer UpgradeFS2 System Analyzer Upgrade ISA-Nios II System Analyzer

10-pin JTAG Target Connection Unlimited Software Breakpoints 2 Hardware Breakpoints (upgradable to 4) Supports On-Chip Trace (upgrades available for

deeper trace)

ISA-Nios II/T System Analyzer 38-pin Mictor Connection Blackbox probe Supports 128k frames Off-Chip Trace

in addition to Unlimited On-Chip Trace


Lab 2Software FlowLab 2Software Flow

45 mins45 mins


A-MNL-NIOSII-04 37


RTL SimulationRTL Simulation


RTL SimulationRTL Simulation

Nios II SOPC Builder Automatically Creates Simulation Models Plus: ModelSim Project Testbench Simulation Scripts

Set Simulation Option


SDRAMDev boardSRAMDev board

FLASH

32-BitNios II

ProcessorOn Chip

ROM)

Clock Reset

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalon Sw

itch Fabric

Nios II Processor

Simulation TestBenchSimulation TestBench

Tri-StateBridge

Use

r Dev

ice

Compact FLASH

SDRAMController

Ethernet MAC/PHY

Tri-StateBridge

Compact Flash PIOs

User Defined Interface

User Defined

Peripheral

On Chip RAM

Custom Instruction

UART

User Device User PeripheralIncluded

Not Included


A-MNL-NIOSII-04 38


User Additions to Nios II TestBenchUser Additions to Nios II TestBench

SOPC Builder creates testbench embedded in top level file eg NiosII.v

Sections within this file are reserved to add user files and code

These sections are preserved if the SOPC builder is used to re-generate the Nios II system


Running an RTL SimulationRunning an RTL Simulation Modify Nios II IDE System Library For Simulation:

Specify Program Memory Set Up As Simulation Only


Running an RTL SimulationRunning an RTL Simulation

Checking the ModelSim only, no hardware supportbutton: Leaves caches uninitialized Does not initialize the .bss section

As a result simulation speeds are increased

You can still simulate with this button unchecked but simulation time will be much longer


A-MNL-NIOSII-04 39


Running an RTL SimulationRunning an RTL Simulation Launch ModelSim from Nios II IDE:

Highlight Software Project In C/C++ Projects panel Right click Run As Nios II ModelSim


Running an RTL SimulationRunning an RTL Simulation


Simulation ScriptsSimulation Scripts When ModelSim is started from the Nios II IDE a set-up

script is run automatically which creates aliases for simulation scripts

The set up script can also be run independently as follows: do setup_sim.do

Simulation Scripts s Compiles HDL source code and loads design c Rebuilds memory contents based on software code

z Includes changes since Nios II generation

w Opens Wave window with useful signals l Opens List window with useful signals h Displays help message describing scripts


A-MNL-NIOSII-04 40


Memory Device Simulation ModelsMemory Device Simulation Models

Applies To The Following Nios II Memories On Chip Memory (ROM or RAM) SRAM Flash Memory and now SDRAM

Include SDRAM Model for Simulation


Memory Device Simulation ModelsMemory Device Simulation Models

You can no longer initialize memories in the SOPC Builder. Memory init file are created by the Nios II IDE.

ext_ram will be initialized for simulation with the ext_ram.dat file

You must compile your software in the Nios II IDE to generate this file

Onchip memories are initialized with .hex

Onchip memory init files can be created by an editor or by the Nios II IDE


UART SimulationUART Simulation Text is transmitted to

UART during simulation Creates and saves txt file

containing UART txstream

Creates window to input text at simulation run time

Note: ModelSim Options are mutually exclusive


A-MNL-NIOSII-04 41


UART SimulationUART Simulation Input is interactive or predefined Output is shown and saved independently for

multiple UARTs


JTAG_UART Simulation JTAG_UART Simulation Text is transmitted to the

new JTAG_UART peripheral during simulation

Creates and saves txt file containing UART txstream

Creates window to input text at simulation run time

Note: ModelSim Options are mutually exclusive

New


Wave WindowWave Window Adds UART and CPU signals by default


A-MNL-NIOSII-04 42


Capture the state of internal nodesIn-system, at full system speeds

SignalTap II Logic AnalyzerSignalTap II Logic Analyzer Up to 200 MHz Multi-Analyzer Support 1,024 Channels 128K Samples 10 Trigger Levels No Probes! Can be used

simultaneously with the Nios II IDE debugger and the FS2 console!


SignalTap II Logic AnalyzerSignalTap II Logic Analyzer


Lab 3RTL SimulationLab 3RTL Simulation

30 mins30 mins


A-MNL-NIOSII-04 43


Avalon Switch FabricAvalon Switch Fabric


Avalon Switch FabricAvalon Switch Fabric Proprietary interconnect specification used with Nios II

Principal design goals Low resource utilization for

bus logic Simplicity Synchronous operation

Transfer Types Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers

32-BitNios II

Processor

Switch PIO

LED PIO

7-SegmentLED PIO

PIO-32

User-Defined Interface

ROM(with Monitor) UART Timer

Address (32)

Read

Write

Data In (32)

Data Out (32)

IRQ

IRQ #(6)

Avalon Sw

itch Fabric

Nios II Processor


Custom-Generated for Peripherals Contingencies are on a Per-Peripheral Basis System is Not Burdened by Bus Complexity

SOPC Builder Automatically Generates Arbitration Address Decoding Data Path Multiplexing Bus Sizing Wait-State Generation Interrupts

Avalon Switch FabricAvalon Switch Fabric


A-MNL-NIOSII-04 44


Avalon Master PortsAvalon Master Ports

Initiate Transfers with Avalon Switch Fabric Transfer Types

Fundamental Read Fundamental Write

All Avalon Masters Must Honor a waitrequestsignal

Transfer Properties Latency Streaming Burst


Avalon Slave PortsAvalon Slave Ports

Respond to Transfer Requests from Avalon Switch Fabric

Transfer Types Fundamental Read Fundamental Write

Transfer Properties Wait States Latency Streaming Burst


Slave Read TransferSlave Read Transfer

0 Setup Cycles

0 Wait Cycles

clk

address,be_n

readn

chipselect

readdata

address, be_n

readdata

A C D EB


A-MNL-NIOSII-04 45


clk

address,be_n

chipselect

readn

readdata

address, be_n

readdata

Tsu

A B C D E F G H

Slave Read Transfer with Wait StatesSlave Read Transfer with Wait States

1 Setup Cycle 1 Wait Cycle


clk

address,be_n

writedata

writen

chipselect

address, be_n

writedata

A B C D

Slave Write TransferSlave Write Transfer

0 Setup Cycles

0 Wait Cycles 0 Hold Cycles


clk

address,be_n

writedata

writen

chipselect

address, be_n

writedata

B C D E FA G

Slave Write Transfer with Wait StatesSlave Write Transfer with Wait States

1 Setup Cycle 0 Wait Cycles 1 Hold Cycle


A-MNL-NIOSII-04 46


Multiple Clock Domains SupportedMultiple Clock Domains Supported

CDX = Clock Domain Crossing Logic (inserted automatically by SOPC Builder)

MasterClock Domain 1

Slave Clock Domain 2


CDXCDX


CDXCDX


ArbiterArbiter










Multi-Clock Domain SupportMulti-Clock Domain Support

CDX = Clock Domain Crossing Logic

MasterClock

Domain 1



MasterClock

Domain 2

CDXCDX


ArbiterArbiter

CDXCDX

MasterClock

Domain 1

SlaveClock Domain 2

SlaveClock Domain 2

MasterClock

Domain 1


CDXCDX

ArbiterArbiter


User-Defined Custom PeripheralsUser-Defined Custom Peripherals What if I need to add a peripheral not included with the

Nios II system? user wants to add own peripheral to perform some kind of

proprietary function or perhaps a standard function that is not yet included as part of the Nios kit

Expand or accelerate system capabilities

We are now going learn how to connect our own design directly to the Nios II system via Avalon As many peripherals contain registers we could also have

chosen to connect to a PIO rather than directly to the bus


A-MNL-NIOSII-04 47


No Need to Worry about Bus Interface Implement Only Signals Needed Peripherals Adapted to by

Avalon Switch Fabric Timing Handled Automatically Fabric Created for You Arbiters Generated for You

Creating Avalon SlaveCreating Avalon Slave

Concentrate Effort onPeripheral Functionality!

User Logic


Register File


New Component EditorNew Component Editor


Creates InterfaceCreates Interface Connect to Existing HDL or board component Map into Nios II Memory Space Can be Inside or Outside Nios II System

Nios IICPU

Ava

lon

Interfaceto UserLogic

Nios II SystemModule

External User

Peripheral

I/O

I/O

I/O

I/O

Nios IICPU

Ava

lon

InternalUser

PeripheralNios II System

Module

I/O

I/O

I/O

I/O


A-MNL-NIOSII-04 48


Create External Component InterfaceCreate External Component Interface

To communicate with off-chip peripherals

Base interface type on data sheet

AMD29LV065AD CFI Flash Chip


Or Add HDL FilesOr Add HDL Files For peripheral that has been encoded for FPGA


Tri-State PeripheralsTri-State Peripherals Require Tri-State Bridge

Available as an SOPC Builder component

Tri-State peripheral is defined by the presence of a bi-direction data port

Off-chip peripherals do not have to be tri-state

Nios IIProcessor

Aval

on

Tri-S

tate

Br

idge

Inte

rface

to

Use

r Log

ic Off Chip Off Chip PeripheralPeripheral

FPGA


A-MNL-NIOSII-04 49


Define Component SignalsDefine Component Signals

Automatically populates port table from design files

Enter port type here

Can also define ports manually


Define Interface for Each Signal TypeDefine Interface for Each Signal Type

Choose interface type Register Slave uses native alignment, Memory Slave uses dynamic alignment

Control Read and Write Timing Add wait and hold states View waveforms


Address Alignment Narrow SlaveAddress Alignment Narrow Slave

Dynamic Address Alignment (set as Memory Slave) LD from Base + 0x0: dd cc bb aa LD from Base + 0x4: uu uu uu ee

Native Address Alignment (set as Avalon Register Slave) LD from Base + 0x0: uu uu uu aa LD from Base + 0x4: uu uu uu bb LD from Base + 0x8: uu uu uu cc

32-BitNios II

Processor

8 Bit Peripheral

Avalon

32

8

Peripheral Registers

Base

Base + 0x1

Base + 0x2

Base + 0x3

Base + 0x4

aa

bb

cc

dd

ee


A-MNL-NIOSII-04 50


Address Alignment Narrow MasterAddress Alignment Narrow Master

Dynamic Address Alignment LD from Base + 0x0: 33 22 11 00 LD from Base + 0x4: 77 66 55 44 LD from Base + 0x8: bb aa 99 88

Native Address Alignment LD from Base + 0x0: 33 22 11 00 LD from Base + 0x4: bb aa 99 88 LD from Base + 0x8: ?? ?? ?? ?? High bytes are unobtainable warning issued

64 Bit Memory

Avalon

32

64

Memory Contents

Base

Base + 0x8

Base + 0x16

77 66 55 44 33 22 11 00

ff ee dd cc bb aa 99 88

?? ?? ?? ?? ?? ?? ?? ??

32-BitNios II

Processor


Add Software FilesAdd Software Files

ie. Header files and drivers


Add Software FilesAdd Software Files Header file and drivers can also be added directly to

Application Project


A-MNL-NIOSII-04 51


Fill in fields Add component to

SOPC Builder portfolio Can add parameterizing

capability to component

Create Component WizardCreate Component Wizard Publish and create a wizard for your component


Add Component to SOPC SystemAdd Component to SOPC System

Default location is the User Logic folder


Eg. Add User-Defined PWM to SystemEg. Add User-Defined PWM to System

HDL for PWM already exists with standard micro-processor type interface

This will be added to our Nios II system in the next Lab

Avalon

Nios II System


A-MNL-NIOSII-04 52


PWM Memory MapPWM Memory Map

Pre-scale factor divides Nios II clock to produce PWM operating frequency

On Period should be less than or equal to Pre-scale

PWM Pre-scale

PWM On Period

031

+ 0x04

Base AddrPWM Duty Cycle =

On Period

Pre-scale


Lab 4Adding A User PeripheralLab 4Adding A User Peripheral

30 mins30 mins


Custom InstructionsCustom Instructions


A-MNL-NIOSII-04 53



Add custom functionality to the Nios II design To take full advantage of the flexibility of FPGA

Dramatically Boost Processing Performance With no Increase in fMAX required

Application Examples Data Stream Processing (eg. Network Applications) Application Specific Processing (eg. MP3 Audio Decode) Software Inner Loop Optimization



Augment Nios II Instruction Set Mux User Logic Into ALU Path of Processor Pipeline


Several Levels of CustomizationSeveral Levels of CustomizationOptional Interface to FIFO, Memory, Other Logic

Internal Register File

a

5

b 5

5

c

readra

readrb

writerc

n

8Extended

clk

clk_enresetstart

Multi-Cycle done

dataa

32datab

32

Combinatorial result

32


A-MNL-NIOSII-04 54



Integrated Into Nios II Development Tools SOPC Builder design tool handles op-code assignment Generates C and assembly-language macros

Similar to Nios Custom Instructions Except Up to 256 different custom instructions possible Multi-cycle instructions can have variable duration Parameterization of custom instructions has changed


Custom Instructions TabCustom Instructions Tab Enabled from the Custom Instructions tab in the

Nios II CPU settings in SOPC Builder


Custom Instructions TabCustom Instructions Tab Import logic for the custom instruction Custom Instruction module can be of following

formats: VHDL Verilog HDL EDIF Quartus Block Diagram (.bdf)


A-MNL-NIOSII-04 55


Combinatorial Custom InstructionsCombinatorial Custom Instructions

Port list All Custom Instruction Modules need these ports

z Port names must match exactly


Multi-Cycle Custom InstructionsMulti-Cycle Custom Instructions

Port list for Multi-Cycle Custom Instructions Must have all of these ports with exact names


Extended Custom InstructionsExtended Custom Instructions Uses n[7..0] port to select an operation to perform.


A-MNL-NIOSII-04 56


Register File Custom InstructionsRegister File Custom Instructions

CustomLogic

dataa[31..0]

reada

a[4..0]

result[31..0]

writec

c[4..0]

Custom instructions can select inputs from internal registers or dataa, datab ports

Custom instructions can write results to an internal register file


Software Interface - CSoftware Interface - C NIOS II IDE generates macros automatically during build process

Macros defined in system.h file#define ALT_CI_(instruction arguments)

Example of user C-code that references Bitswap custom instruction:#include "system.h"int main (void){

int a = 0x12345678;int a_swap = 0;

a_swap = ALT_CI_BSWAP(a);return 0;

}


Assembly Language Interface Assembly Language Interface Assembler syntax for the custom instruction:

custom N, rC, rA, rB

Two Examples:custom 0, r6, r7, r8custom 3, c1, r2, c4

Custom Custom instruction instruction

opcodeopcodenumbernumber

Destination Destination register register

for resultfor result

Operand 1Operand 1 Operand 2Operand 2

r = r = NiosNios II processor II processor registerregister

c = Custom instruction c = Custom instruction internal registerinternal register


A-MNL-NIOSII-04 57


Why Custom Instruction?Why Custom Instruction? Reduce Complex Sequence of Instructions to One Instruction Example: Floating Point Multiply

Typical Flow Profile Code Identify Critical Inner Loop Create Custom Instruction Logic

z Replace One or All Instructions in Inner Loop Import Custom Instruction Logic into Design Call Custom Instruction from C or Assembly

float a, b, result_slow, result_fast;

result_slow = a * b; /* Takes 266 clock cycles */result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/

Significantly Faster!

float a, b, result_slow, result_fast;

result_slow = a * b; /* Takes 266 clock cycles */result_fast = ALT_CI_fpmult(a,b); /* Takes 6 clock cycles*/

Significantly Faster!


Custom Instruction vs PeripheralCustom Instruction vs Peripheral

Custom Instruction can execute in a single cycle No overhead for call to custom Hardware

Access to same hardware as peripheral takes multiple cycles Write DataA, then write DataB, and finally read Result

ResultDataBDataA0x400

0x4040x408

Custom Custom InstructionInstructionL1

L0 L0

Custom Custom PeripheralPeripheralL1

L0 L0

Peripheral memory map


Multi-Cycle Custom InstructionsMulti-Cycle Custom Instructions

Processor stalls while awaiting result Clock cycles = 3

DataA DataB

REGREG

REGREG

Result

Cus

tom

Inst

ruct

ion

custom

---

---

Next InstrNio

s C

lock

Cyc

les


A-MNL-NIOSII-04 58


Result not always needed for each input Clock Cycles = 1 Route start sig to reg clk_en

Pipelined Custom InstructionsPipelined Custom Instructions

DataA DataB

REGREG

REGREG

Result

Cus

tom

Inst

ruct

ion

custom

Next Instr

Nio

s C

lock

Cyc

les

custom

custom

custom

custom


Accelerating CRCAccelerating CRC

Implementing the shift and XOR for each bit takes many clock cycles ~50

Software algorithms tend to use look up tables to pre-compute each byte

Parallel Hardware is fastest

reg

xor/s

hift

xor/s

hift

xor/s

hift

in(15) in(14) in(0)


CRC Custom InstructionCRC Custom Instruction

CRC16-CCITT needs to be preset to 0xFFFF at the start of each computation

Can use the Data B input to select between run and load Use of prefix would waste a clock cycle

CRCCustom Instruction

DataA(31-0)

DataB(0)

// reset crcALT_CI_CRC(0xFFFF,1);

// run crcALT_CI_CRC(word,0);

// reset crcALT_CI_CRC(0xFFFF,1);

// run crcALT_CI_CRC(word,0);

Data in

Init / nRun

CRC Reg Result(15-0)

Control


A-MNL-NIOSII-04 59


Multi-Masters and Direct Memory Access (DMA)Multi-Masters and Direct Memory Access (DMA)


Direct Memory Access (DMA) Processor Waits For Bus During DMA

System CPU(Master 1)

DMA Arbitor

100Base-T(Master 2)

System Bus

I/O1

I/O2 DataMemory

DMA Bus ArbiterDMA Bus Arbiter Arbiter Determines Which Master Has Access To Shared

Bus

ProgramMemory

Masters

Slaves

Traditional Multi-MastersTraditional Multi-Masters

Control direction

SystemBottleneck

SystemBottleneck


Has Benefits of a Switch Fabric and Slave-Side Arbitration Shared Bus & Share Arbiter are No Longer the Bottleneck Multiple Master Transactions Can Operate Simultaneously

z As long as they dont access the same slave in the same bus bycle I/O Devices Can be Grouped Based on Bandwidth Requirement

Trade-Off Hardware Resource Usage Increases

DisplayControlDisplayControl

CPU 0CPU 0 DMADMA

Program Memory 0Program Memory 0 I/OI/O

CustomFunctionCustomFunction

Data Memory 1

Data Memory 1

System Switch Fabric

Program Memory 1Program Memory 1

Data Memory 0

Data Memory 0

ArbiterArbiter

Masters

Slaves

Uses Fairness Arbitration

Avalon Simultaneous Multi-Mastering BusAvalon Simultaneous Multi-Mastering Bus

automatically automatically generated by generated by SOPC BuilderSOPC Builder

CPU 1CPU 1

ArbiterArbiter


A-MNL-NIOSII-04 60


Provides Bus Master Capability to Any Nios II Peripheral FIFO Depth = 2

DMA Peripheral

Control Port

Direction

Master Port1

Start Addr

# Bytes

Addr Incr

Master Port2

Start Addr

# Bytes

Addr Incr

FIFO

DMA PeripheralDMA Peripheral


Master 1(Nios II CPU)

I/O1Program

Memory

Arbiter

DataMemory

1

SPI

I D

I/O2

Avalon Avalon

Master 2DMA

Data Flow with DMA PeripheralData Flow with DMA Peripheral


Use custom hardware peripheral with DMA Processor & Accelerator Run Concurrently More Work Per Clock Lower fMAX, Power, Cost

Accelerate Software ExecutionAccelerate Software Execution

ProgramMemory

Processor

DataMemory

ArbiterArbiter

DataMemory

ArbiterArbiterAvalonSwitch Fabric

DM

AD

MA

DM

AD

MAAccelerator


A-MNL-NIOSII-04 61


Example: CRC Algorithm (64 Kbytes)

HardwareAccelerator

0

5,000,000

10,000,000

15,000,000

20,000,000

25,000,000

Clo

ck C

ycle

s

Software Only CustomInstruction

530 TimesFaster

27 TimesFaster

Accelerate Software ExecutionAccelerate Software Execution


Custom Streaming Slave PeripheralsCustom Streaming Slave Peripherals

For using DMA with other slow peripherals Example: UART

Adds up to three outputs to Avalon Slave dataavailable readyfordata endofpacket

Aval

on

Custom Custom StreamingStreaming

Slave Slave PeripheralPeripheral

readdata

writedata

control

adress

endofpacket

Readyfordata

dataavailable


Streaming Slave Peripheral SignalsStreaming Slave Peripheral Signals

dataavailable Indicates that the peripheral has data available to be read

by DMA or other master ie, there is data in the rx buffer or register

readyfordata Indicates that the peripheral is able to receive data written

by DMA or other master Ie. the tx buffer or register is not full

endofpacket Usage not defined DMA can be optionally set to end transfer


A-MNL-NIOSII-04 62


Custom Master PeripheralsCustom Master Peripherals

Can integrate DMA function Eg. VGA that takes data from memory directly

Simpler than Slave peripherals Assert outputs until waitrequest is low

Transaction are between Master and Avalon, not Slave

Aval

onCustom Custom Master Master

PeripheralPeripheralwaitrequest

readdata

writedata

control

address


Master Read TransferMaster Read Transfer

Assert addr, be, readWait for waitrequest = 0 Read in Data End of transfer


Master Write TransferMaster Write Transfer

Assert addr, be, read Assert Write DataWait for waitrequest = 0 End of transfer


A-MNL-NIOSII-04 63


Avalon Burst SupportAvalon Burst Support

New Signals for Bursting Masters, Slaves Burstcount, beginbursttransfer

Several Bursting Styles Exist Wrapping, Off-Boundary, Interleaved Maximum Burst Size

Tool Automatically Reconciles: Data Width, Burst Size, Bursting-to-non-bursting Transfers


Avalon Master-Slave ConnectionsAvalon Master-Slave Connections

View => Show Master Connections Observe and configure Avalon connections


Master Arbitration SchemeMaster Arbitration Scheme Nios II Multi-Master Avalon Switch Fabric Utilises

Fairness Arbitration Scheme Each Master/Slave pair is assign an integer shares Upon conflict Master with most shares takes bus until all

shares are used Master with least shares then takes bus until all shares are

used Assuming all Masters continuously request the bus, they will

each be granted the bus for a percentage of time equal to the percentage of total master shares that they own

PCI DMA 2 shares

SPI DMA 1 share

CPU 7 Shares


A-MNL-NIOSII-04 64


Set Arbitration PrioritySet Arbitration Priority View => Show Arbitration Priorities


Avalon Arbitration BehaviorAvalon Arbitration Behavior

Master A Shares = 4

Master B Shares = 2

Arbiter (continuous accesses)

Master A Master B

Arbiter

Slave

Master B

Master A


Lab 5Custom Instruction and (optional) DMA Controller

Lab 5Custom Instruction and (optional) DMA Controller45 mins45 mins


A-MNL-NIOSII-04 65


Working with the Development BoardWorking with the Development Board


Ensure Unused I/O are Tri-StateEnsure Unused I/O are Tri-State The FPGA may connect to components on the board not

used by your design There is a connection between FPGA and MAX device to

force reconfiguration Active low, pulled high

Assignments -> Device For Stratix devices, be sure to set Dual Purpose pins to

Use as Regular IO


Clock DistributionClock Distribution

PLL required to meet SDRAM I/O timing Introduces -60 phase shift relative to Nios II

CLK in is socket crystal or external input Resistor changes required for external

See board schematic and ref design

FPGA NiosNios IIII

PLLPLL

Zero

Ske

w

Buffe

r

SDRAMSDRAM

Zero

Ske

w

Buffe

r

CLK in (50 MHz)


A-MNL-NIOSII-04 66


Flash Configuration Two FPGA images

z Safe Imagez User Image

MAX EPM7128 Configures FPGA from Flash Upon power up or press of Reset Config

z MAX Device Loads User Image into FPGAz If This Fails MAX Device Loads Safe Image

Failure includes no user image present Upon press of Safe Config

z MAX Device Loads Safe Image into FPGA

Hardware Configuration ProcessHardware Configuration Process

MAX

Data

Address

8 MB Flash

Stratix

Safe FPGA Safe FPGA ImageImage

User FPGA Image

0x600000

0x700000


SRAM

Data

Address

8 MB Flash

Stratix

Flash Memory ConfigurationFlash Memory Configuration

Safe FPGA Safe FPGA Image & S/WImage & S/W

User FPGA Image

0x000000

0x100000

0x200000

0x300000

0x400000

0x500000

0x600000

0x700000

User User SoftwareSoftware


Use Flash for Program StorageRunning from Flash is slow

Nios II IDE Automatically Prepends Boot Copier to Program Code if Reset Address is in Flash and

Program Memory is in RAM

For Custom Boards:(see again Nios II Flash Programmer User Guide) Must create your own flash

programmer design to transport data to the flash on your board

my_sw.elf

Boot Copier

SRAM

Data

Address

8 MB Flash

Stratix User Software

Boot CopierBoot Copier

my_sw.flash


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Nios II Flash ProgrammerNios II Flash Programmer

Downloads flash content to CFI flash device Communication is over JTAG interface Can also download to any Altera EPCS Serial Configuration

Device connected to FPGA

Two-step process: Send Flash Programmer Design Send Flash Content

Flash ContentFlash Content


Nios II Flash ProgrammerNios II Flash Programmer

Flash Programmer Design contains Nios II CPU JTAG UART Active serial memory interface Tri-state bridge CFI-compatible flash interface System ID peripheral on-chip memory for firmware and buffers

Flash Content can include: FPGA hardware configuration image Software content Arbitrary content


Nios II Flash ProgrammerNios II Flash Programmer Can program Flash from Nios II IDE or command line

Nios II IDE is recommended method


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Nios II Flash ProgrammerNios II Flash Programmer Command Line Utilities

elf2flash

sof2flash

bin2flash

nios2-flash-programmer

(see Nios II Flash Programmer User Guide for details)


Instantiating Flash in Target SystemInstantiating Flash in Target System Must set target board to appropriate development kit

Need CFI (Common Flash Interface) Flash Memory EPCS Serial Flash Controller reqd if booting from EPCS device


Flash Programmer DesignFlash Programmer Design

What if I Have a Custom Board? Import board settings into the SOPC Builder using

mk_target_board scriptz Specify flash devices and designator numbersz Clock frequency z Device family

Create flash programming design in SOPC Builder based on .PTF generated from above script

Generate .SOF file for flash design See Nios II Flash Programmer User Guide for details


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What If Safe Flash Image Overwritten?What If Safe Flash Image Overwritten? Open Nios II SDK Shell

Start > Programs > Altera > Nios II Development Kit > Nios II SDKShell

Change to factory-recovery directory for your development kit cd examples/factory_recovery/niosII_cyclone_1c20

Run flash-restoration script ./restore_my_flash

Follow the scripts instructions


Diverse Portfolio of Nios Development KitsDiverse Portfolio of Nios Development Kits

eg. Stratix and Cyclone Altera Microtronix

Daughter Cards Microtronix: VGA / PS2 SLS: USB 2.0 El Camino GmbH: RF A/D D/A EasyFPGA: USB 2.0

The List Keeps Growing


Lab 6The Flash ProgrammerLab 6The Flash Programmer

10 mins10 mins


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SummarySummary


Nios II - Leads The IndustryNios II - Leads The IndustryHighest

PerformanceHighest

Performance Multi-Processor Hardware Acceleration Custom Instructions

Concept to System in Minutes FPGA > HardCopy Structured

ASIC

GreatestFlexibilityGreatestFlexibility

Most Powerful Design Tools

Most Powerful Design Tools

Fastest Timeto Market

Fastest Timeto Market

Processors Peripherals Optimized Interconnect

SOPC Builder Nios II IDE On-Chip Processor Debug SignalTap II Logic Analyzer


Altera Technical Support Reference Quartus II On-Line Help Consult Altera Applications (Factory Applications Engineers)

MySupport: http://www.altera.com/mysupport Hotline: (800) 800-EPLD (7:00 a.m. - 5:00 p.m. PST)

World-Wide Web: http://www.altera.com Use Solutions to Search for Answers to Technical Problems View Design Examples

Field Applications Engineers: Contact Your Local Altera Sales Office Receive Literature by Mail: (888) 3-ALTERA FTP: ftp.altera.com


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Instructor-Led Training

With Altera's instructor-led training courses, you can:

Listen to a lecture from an Altera technical training engineer (instructor)

Complete hands-on exercises with guidance from an Altera instructor

Ask questions and receive real-time answers from an Altera instructor

Each instructor-led class is one day in length (8 working hours).

Learn More Through Technical Training

On-Line Training

With Altera's on-line training courses, you can:

Take a course at any time that is convenient for you

Take a course from the comfort of your home or office (no need to travel as with instructor-led courses)

Each on-line course will take approximately 2-3 hours to complete.

www.altera.com/trainingView Training Class Schedule & Register for a Class


Thank YouThank You


AppendixAppendix


A-MNL-NIOSII-04 72


Introduction to Altera DevicesIntroduction to Altera Devices Programmable Logic Families

High & Medium Density FPGAsz Stratix II, Stratix, APEX II,

APEX 20K, & FLEX 10K Low-Cost FPGAs

z Cyclone II, Cyclone & ACEX 1K FPGAs with Clock Data Recovery

z Stratix GX & Mercury CPLDs

z MAX II, MAX 7000 & MAX 3000 Embedded Processor Solutions

z Nios, Nios II Configuration Devices

z EPC


Software & Development Tools: Quartus II

zStratix II, Stratix GX, Cyclone II, HardCopy Stratix, MAX II, APEX 20K/E/C, Excalibur, & Mercury DeviceszFLEX 10K/A/E, ACEX 1K, FLEX 6000, MAX 3000A,

MAX 7000S/AE/B Devices

Quartus II Web EditionzFree version zNot all features & devices included

MAX+PLUS IIzAll FLEX, ACEX, & MAX Devices

Introduction to Altera Design SoftwareIntroduction to Altera Design Software


Pipelined RISC Architecture 16-Bit Instructions Windowed Register File 16-bit or 32-Bit Data Path 64 Prioritized Interrupts Optional Instruction & Data Cache Custom Instructions

Nios II vs NiosNios II vs Nios

Pipelined RISC Architecture 32-Bit Instructions Flat Register File 32-Bit Data Path 32 Prioritized Interrupts Optional Instruction & Data Cache Custom Instructions Branch Prediction

NiosNiosNiosNios IIII


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Pipelined RISC Architecture 32-Bit Instruction and Data Paths 6 Stage Pipeline 32 General Purpose Registers 32 External Interrupt Sources Configurable Size Instruction Cache Dynamic Branch Prediction Hardware Multiply Barrel Shifter Custom Instructions Configurable Size Data Cache Hardware Breakpoints Optional Hardware Divide

Nios II/f Fast versionNios II/f Fast version 135MHz 1.2 DMIPS/MHz


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Clock Domain Crossing - Clock Adapters Clock Domain Crossing - Clock Adapters

D1 D2 D3

CLK 1

CLK 2

D4

CLK 1

CLK 2

D2

D3

D4

D4 is synchronized and valid

CLK2 samples D2while it is changing


Note: Can Compile Code Right Into Quartus II .sof FileNote: Can Compile Code Right Into Quartus II .sof File

Smart Compilation must have been on in first Quartus II compile to incrementally include .hex file into .sof

Target on-chip memory => .hex file containing Nios II program


What is Trace Data?What is Trace Data?

Collection of instructions executed by CPU JTAG Console will display it as load/store

operations or in disassembled instructions (eg. Nios II CPU instructions)

15.28: 008032BC 0xe0809d17 ldw r2, 628(fp)15.28: 008032C0 0xe1809d17 ldw r6, 628(fp)15.28: 008032C4 0x10800017 ldw r2, 0(r2)15.28: 008032C8 0x31800104 addi r6, r6, 415.28: 008032CC 0xe1809d15 stw r6, 628(fp)15.28: 008032D0 0x003fde06 br 0x80324c15.30: 0080324C 0x11000015 stw r4, 0(r2)15.30: 00803250 0x003fe006 br 0x8031d4


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What is a Software Breakpoint?What is a Software Breakpoint?

Implemented by inserting an interrupt into the code (TRAP instruction)

Program memory must be writable (not ROM) Flash wont work either due to write sequence

Used to break at a line of code


What is a Hardware Breakpoint?What is a Hardware Breakpoint?

Implemented by triggering a dedicated hardware interrupt

Used to break on hardware conditions: Specified data address and/or data value Can also break on instruction (similar to software

breakpoint) for code stored in ROM Option to halt the processor, gather trace data or

trigger out Doesnt matter whether program memory is

writable since it doesnt touch the code, so you can debug code stored in ROM or Flash


Micrium uC/OS-II Licensing:Micrium uC/OS-II Licensing:

There are actually three licenses available for MicroC/OS-II:

1. A developers license - Included with every copy of MicroC/OS-II shipped with an Altera development kit. This enables customers to develop applications using the RTOS which are targeted for the Altera development board.

2. Annual MicroC/OS-II subscription . Customers writing application code for their own board (or any board other than Altera development boards) must purchase an annual subscription from which entitles them to the following:

License for 3 developers to create as many designs as they wish for 1 year using MicroC/OS-II Perpetual license to support designs created during the subscription period (i.e. fix bugs, minor

modifications). Additional subscription license seats may be purchased per developer.

3. Project License . Customers who require licenses for more than 10 developers should purchase a Project license which enables an unlimited number of designers to develop for that project using MicroC/OS-II.


A-MNL-NIOSII-04 76


Arbitration with MURL Length Set to 3Arbitration with MURL Length Set to 3

Master A Shares = 4

Master B Shares = 2

Arbiter (continuous accesses)

Master A Master B

Arbiter

Slave

Master B

Master A

Slave MURL = 3

Minimum unMinimum un--interrupted run lengthinterrupted run length(hidden feature that is set in .PTF file)(hidden feature that is set in .PTF file)

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