Course: CSC--- Digital Logic Design - Muhammadiyahmnk.muhammadiyah.info/Lab Manuals/ver...

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Course: CSC--- Digital Logic Design

Department of Computer Science

Learning Procedure

1) StageJ(Journey inside-out the concept)

2) Stagea1(Apply the learned)

3) Stagev(Verify the accuracy)

4) Stagea2(Assess your work)

Table of Contents

Lab # Topics Covered Page #

Lab # 01 To verify the operation OR, NOT, AND GatesLab # 02 Verify the working of NAND , NOR GatesLab # 03 Design AND, OR, NOT operations using Universal Gates NAND,

NOR.Lab # 04 Verify the working of XOR, XNOR GatesLab # 05 Design Half Adder CircuitLab # 06 Design Half Subtractor CircuitLab # 07 Design Full Adder CircuitLab # 08 Design Full Subtractor CircuitLab # 09 Verify the working of MultiplexerLab # 10 Verify the working of DeMuxLab # 11 Verify the working of DecoderLab # 12 Design Decoder using MultiplexerLab # 13 Verify the working of RS Flip Flop(FF)Lab # 14 Verify the working of D Flip Flop(FF)Lab # 15 Verify the working of J-K Flip Flop(FF)Lab # 16 Verify the working of Master slave J-K Flip Flop(FF)Lab # 17 Design parallel shift registerLab # 18 Design two stage binary ripple counterLab # 19 Design three stage binary ripple counter

Terminal Examination

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Statement Purpose:This lab will give you the introduction of three basic logic gates

Activity-1

Activity Outcomes:To understand Boolean logic of OR gate

1) StageJ(Journey)In this experiment we use IC 74LS32N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded and pin number 1 should be connected to a certain voltage(logic 1). It has two input and one output which is based on the logic.

Equipment Component:

1. 74LS32N x 1.2. LED x 1.3. SPST x 2.

Tools:

1. Digital Trainer2. Single core wire3. Cutter

Symbolic Diagram:

Truth Table:

A B Y0 0 00 1 11 0 11 1 1

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LAB # 1

2) Stage a1 (apply)

Procedure:

1. Take an IC 74LS32N and place it in the trainer.2. Now take two SPST switch and connect them to the 5V +VCC, and the other terminal

to the 1st and 2nd pin of the IC.3. We connect pin number 3 of the IC to a LED positive terminal and connect the other

terminal of the LED to the ground.4. We use LED as an indicator note down the result by changing the input manually

In case of trouble:

1. Check the wire connections.2. Check the pin 7 and pin 14 that they are connected perfectly or not.3. Check the pin configuration of the IC.

MultiSim Work:

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3) Stage v (verify)

Give some exercise for home work

4) Stage a2 (assess)

Assignment:

For this student will submit Lab Assignment before the deadline.

Activity-2

Activity Outcomes:To understand Boolean logic of AND gate

1) StageJ(Journey)We will perform the operation on AND Gate IC. The IC we will use is 14 pin named as 74LS08N. We will take +5V positive VCC on pin no 14 and ground on pin number 7. Formula for the AND Gate is as follow:

Y = A x B


1- IC-74LS08N2- Wires 3- LED4- Trainer Kit

Tools:


Symbolic Diagram:

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Truth Table:

A B Y0 0 00 1 01 0 01 1 1

2) Stage a1 (apply)

Procedure:

1. Take an IC 74LS08N and place it in the trainer.2. Now take two SPST switch and connect them to the 5V +VCC, and the other terminal

to the 1st and 2nd pin of the IC.3. We connect pin number 3 of the IC to a LED positive terminal and connect the other

terminal of the LED to the ground.4. We use LED as an indicator note down the result by changing the input manually

In case of trouble:


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MultiSim Work:

3) Stage v (verify)



Assignment:


Activity-3

Activity Outcomes:To understand Boolean logic of NOT gate

1) StageJ(Journey)

In this experiment we use IC 74LS04N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded and pin number 1 should be connected to a certain voltage(logic 1). It has one input and one output which is based on the logic.


5- IC-74LS04N6- Wires 7- LED8- Trainer Kit

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Tools:


Symbolic Diagram:

Truth Table:

A Y0 10 0

2) Stage a1 (apply)

Procedure:

1. Take an IC 74LS04N and place it in the trainer.2. Now take SPST switch and connect it to the 5V +VCC, and the other terminal to the

1st pin of the IC.3. We connect pin number 2 of the IC to a LED positive terminal and connect the other

terminal of the LED to the ground.4. We use LED as an indicator note down the result by changing the input manually.

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In case of trouble:


MultiSim Work:

3) Stage v (verify)Give some exercise for home work


Assignment:


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Statement Purpose:This lab will give you the introduction of two universal logic gates

Activity-1

Activity Outcomes:To understand Boolean logic of NOR gate

1) StageJ(Journey)

In this experiment we used the IC 74LS02 to check the operation of NOR gate and I also used the two switches to prove that the ic is working.I conected the the switch a with 1a pin of ic and switch b with the 1b of ic and I provided the 5v vcc to the switches .Then I connected the 1y pin of IC with LED.

Equipment Component:1. 74LS02 N x 1.2. LED x 1.3. SPST x 1.

Tools:1. Digital Trainer2. Single core wire3. Cutter

Symbolic Diagram:

Truth Table:

A B Y0 0 10 1 01 0 01 1 0

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LAB # 2

2) Stage a1 (apply)

Procedure:

1. Connect the EES-2001 trainer to the 220V AC power supply.2. Turn on the trainer to verify the voltage of power using multimeter.3. Install the IC74LS02 on the trainers braced board.4. Wire the circuit according to the diagram.5. Use and of the two switches S2 and S1 for inputs.6. For output indication use any of the LEDs from L0 – L15.7. Supply the VCC=+5V and GND to the pins 141 and 7 of the IC.8. Test all the possible combinations of inputs and verify the output according to the

truth table.

In case of trouble:

1. Check the power supply.2. Check the VCC and GND at pins 14 and 7 of the IC.3. Check all the wire connectors.4. Check the circuit wiring and remove the breaks.5. Check the IC using truth table.

MultiSim Work:

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3) Stage v (verify)



Assignment:


Activity-2

Activity Outcomes:To understand Boolean logic of NAND gate

1) StageJ(Journey)

In this experiment we will perform the operation on NAND Gate IC. The IC we will use is 14 pin named as 74LS00N. We will take +5V positive VCC on pin no 14 and ground on pin number 7. Formula for the NAND Gate is as follow,

Y = (A x B)’


1. IC-74LS00N2. Wires 3. LED4. Trainer Kit


Symbolic Diagram:

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Truth Table:

A B Q0 0 10 1 11 0 11 1 0

2) Stage a1 (apply)

Procedure:

1. Connect the EES-2001 trainer to the 220V AC power supply.2. Turn on the trainer to verify the voltage of power using multimeter.3. Install the IC74LS00 on the trainers braced board.4. Wire the circuit according to the diagram.5. Use and of the two switches S2 and S1 for inputs.6. For output indication use any of the LEDs from L0 – L15.7. Supply the VCC=+5V and GND to the pins 141 and 7 of the IC.8. Test all the possible combinations of inputs and verify the output according to

the truth table.

In case of trouble:


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MultiSim Work:

3) Stage v (verify)



Assignment:


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Statement Purpose:Designing three basic logic gates using universal gates

Activity-1

Activity Outcomes:To understand Boolean logic of OR gate by designing OR gate using NAND gates

1) StageJ(Journey)

In this experiment we use IC 74LS00N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded. NAND pin number 1 and 2 should be connected to input A and its output pin 3 to 10 pin, whereas, another input B connected to pin 4 and 5 and its output pin 6 to input 9 pin. The final output pin 8 should attached to LED.

Equipment Component:1. 74LS00N x 1.2. LED x 1.3. SPST x 2.


Symbolic Diagram:

Truth Table:

A B Y0 0 00 1 11 0 11 1 1

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LAB #3

2) Stage a1 (apply)

Procedure:


truth table.

In case of trouble:


MultiSim Work:

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3) Stage v (verify)



Assignment:


Activity-2

Activity Outcomes:To understand Boolean logic of AND gate by designing AND gate using NAND gates

1) StageJ(Journey)

In this experiment we use IC 74LS00N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded and 14 to VCC. NAND pin number 1 should be connected to input A whereas, another input B connected to pin 2. And its output pin 3 to input pin 4 and pin 5. The final output pin 6 should attached to LED.


1. 74LS00N x 1.2. LED x 1.3. SPST x 2.


Symbolic Diagram:

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Truth Table:

A B Q0 0 00 1 01 0 01 1 1

2) Stage a1 (apply)

Procedure:

1. Connect the EES-2001 trainer to the 220V AC power supply.2. Turn on the trainer to verify the voltage of power using multimeter.3. Install the IC74LS00 on the trainers braced board.4. Wire the circuit according to the diagram.5. Use and of the two switches S2 and S1 for inputs.6. For output indication use any of the LEDs from L0 – L15.7. Supply the VCC=+5V and GND to the pins 141 and 7 of the IC.8. Test all the possible combinations of inputs and verify the output according to

the truth table.

In case of trouble:


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MultiSim Work:

9. Stage v (verify)


10. Stage a2 (assess)

Assignment:


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Statement Purpose:Verify the working of XOR, XNOR Gates

Activity-1

Activity Outcomes:To understand Boolean logic of XOR gate

1) StageJ(Journey)

In this experiment we use IC 74LS00N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded. NAND pin number 1 and 2 should be connected to input A and its output pin 3 to 10 pin, whereas, another input B connected to pin 4 and 5 and its output pin 6 to input 9 pin. The final output pin 8 should attached to LED.

Equipment Component:1. 74LS00N x 1.2. LED x 1.3. SPST x 2.


Symbolic Diagram:

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LAB #4

Truth Table:

A B Y0 0 00 1 11 0 11 1 0

2) Stage a1 (apply)

Procedure:

1. Connect the EES-2001 trainer to the 220V AC power supply.2. Turn on the trainer to verify the voltage of power using multimeter.3. Install the IC74LS00 on the trainers braced board.4. Wire the circuit according to the diagram.5. Use and of the two switches S2 and S1 for inputs.6. For output indication use any of the LED,s from L0 – L15.7. Supply the VCC=+5V and GND to the pins 141 and 7 of the IC.8. Test all the possible combinations of inputs and verify the output according to

the truth table.

In case of trouble:


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MultiSim Work:

1. Stage v (verify)



Assignment:


Activity-2

Activity Outcomes:To understand Boolean logic of XNOR

1) StageJ(Journey)In this experiment we use IC 74LS00N, which is 14 pinned IC, which has an ordered universal pined configuration, the pin number 7 has to be grounded. NAND pin number 1 and 2 should be connected to input A and its output pin 3 to 10 pin, whereas, another input B connected to pin 4 and 5 and its output pin 6 to input 9 pin. The final output pin 8 should attached to LED.

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4. 74LS00N x 1.5. LED x 1.6. SPST x 2.


Symbolic Diagram:

Truth Table:

A B Q0 0 00 1 01 0 01 1 1

3. Stage a1 (apply)

Procedure:


truth table.

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In case of trouble:


MultiSim Work:

9. Stage v (verify)


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Assignment:


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Statement Purpose:Designing half adder using XOR logic gates

Activity Outcomes:To understand Boolean logic of half adder using XOR gates

1) StageJ(Journey)

Adder: Digital computer perform a variety of information processing tasks, among the basics function encountered are the various arithematic operations, the most basic arithematic operation no doubt is the additionb of two binary digits, this simple addition consists of four possible elementary operations which namely as

0+0=0

0+1=1

1+0=1

1+1=10

Half Adder: A combinational circuits that performs the addition of two bits is called the half adder one that performs the addition of three bits(two significant bits and a previous carry) is called a full adder.

I used the IC 74LS08 and IC 74LS86 to check the operation of half adder and I also used the two switches to prove that the ic is working.I conected the the switch a with 1a pin of ic and switch b with the 1b of ic and I provided the 5v vcc to the switches .Then I connected the 1y pin of IC with LED.

As the IC is working with the operation so when the both inputs are 1 than the sum is 0 and the carry is 1 where as when both inputs are 0 then the sum and carry are 0.The above logic operation of the half gate can be summarized with the help of truth table

Equipment Component:1. LED x 1.2. SPST x 2.3. 74LS084. 74LS86

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LAB #5


Symbolic Diagram:

Truth Table:

A B S C0 0 0 00 1 1 01 0 1 01 1 0 1

2) Stage a1 (apply)

Procedure:

1. Connect the EES-2001 trainer to the 220V AC power supply.2. Connect the EES-2001 trainer to the 220V AC power supply.3. Turn on the trainer to verify the voltage of power using multimeter.4. Install the IC74LS08 and IC74LS86 on the trainers braced board.5. Wire the circuit according to the diagram.6. Use and of the two switches S2 and S1 for inputs.7. For output indication use any of the LED,s from L0 – L15.8. Supply the VCC=+5V and GND to the pins 141 and 7 of the IC.

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9. Test all the possible combinations of inputs and verify the output according to the truth table.

In case of trouble:


MultiSim Work:

3) Stage v (verify)



Assignment:


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Statement Purpose:Designing Full adder using XOR logic gates

Activity Outcomes:To understand Boolean logic of full adder using XOR gates

1) StageJ(Journey)

The half-adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing the full-adder are:

Equipment Component:1. LED x 1.2. SPST x 33. 74LS084. 74LS86


Symbolic Diagram:

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LAB #6

2) Stage a1 (apply)

1) Check the components for their working. 2) Insert the appropriate IC into the IC base.3) Make connections as shown in the circuit diagram. 4) Verify the Truth Table and observe the outputs.

A B Cin S C0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

In case of trouble:


3) Stage v (verify)


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Statement Purpose:Designing half subtractor using XOR logic gates

Activity Outcomes:To understand Boolean logic of half subtractor using XOR gates

1) StageJ(Journey)

Subtracting a single-bit binary value B from another A (i.e. A -B ) produces a difference bit D and a borrow out bit Br. This operation is called half subtraction and the circuit to realize it is called a half subtractor. The Boolean functions describing the half Subtractor are:



Symbolic Diagram:

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LAB #7

Truth Table:

A B S C0 0 0 00 1 1 11 0 1 01 1 0 0

2) Stage a1 (apply)

1. Check the components for their working. 2. Insert the appropriate IC into the IC base.3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.

In case of trouble:


Multisim:

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3) Stage v (verify)


RESULT: The truth table of the above circuits is verified.

VIVA QUESTIONS: 1) What is a half adder? 2) What is a full adder?3) What are the applications of adders?4) What is a half subtractor?

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Statement Purpose:Designing full subtractor using XOR logic gates

Activity Outcomes:To understand Boolean logic of full subtractor

1) StageJ(Journey)

Journey:

Subtracting two single-bit binary values, B, C in from a single-bit value A produces a difference bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing the full-subtractor are:



Symbolic Diagram:

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LAB #8

Truth Table:

A B Bin D Bot0 0 0 0 00 0 1 1 10 1 0 1 10 1 1 0 11 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1

2) Stage a1 (apply)


Multisim:

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3) Stage v (verify)



Assignment:


RESULT: The truth table of the above circuits is verified.

Viva Questions:

1) What is a full subtractor? 2) What are the applications of subtractors? 3) Obtain the minimal expression for above circuits. 4) Realize a full adder using two half adders. 5) Realize a full subtractors using two half subtractors.

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Statement Purpose:Designing 4:1 multiplexer using logic gates

Activity Outcomes:To understand Boolean logic of 4:1 multiplexer

1) StageJ(Journey)

Multiplexers are very useful components in digital systems. They transfer a large number of information units over a smaller number of channels, (usually one channel) under the control of selection signals. Multiplexer means many to one. A multiplexer is a circuit with manyinputs but only one output. By using control signals (select lines) we can select any input to the output. Multiplexer is also called as data selector because the output bit depends on the input data bit that is selected. The general multiplexer circuit has 2n input signals, ncontrol/select signals and 1 output signal.

Output : Y= E’S1’S0’I0 + E’S1’S0I1 + E’S1S0’I2 + E’S1S0I3

Equipment Component:1. LED x 1.2. SPST x 2.3. 74LS004. 74LS105. 74LS1536. 74LS139

Tools:7. Digital Trainer8. Single core wire

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LAB #9

9. Cutter

Symbolic Diagram:

Multisim

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Multisim

VERIFY IC 74153 MUX (DUAL 4:1 MULTIPLEXER)

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Truth Table:

2) Stage a1 (apply)


In case of trouble:


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MultiSim Work:

3) Stage v (verify)



Assignment:


5)VIVA QUESTIONS: 1) What is a multiplexer? 2) What are the applications of multiplexer 3) Derive the Boolean expression for multiplexer. 4) How do you realize a given function using multiplexer 5) In 2n to 1 multiplexer how many selection lines are there? 6) How to get higher order multiplexers?7) Implement an 8:1 mux using 4:1 muxes?

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Statement Purpose:Designing 1:4 Demultiplexer using logic gates

Activity Outcomes:To understand Boolean logic of Demultiplexer using XOR gates

1) StageJ(Journey)

De-multiplexers perform the opposite function of multiplexers. They transfer a small numberof information units (usually one unit) over a larger number of channels under the control ofselection signals. The general de-multiplexer circuit has 1 input signal, n control/selectsignals and 2n output signals. De-multiplexer circuit can also be realized using a decodercircuit with enable.

COMPONENTS REQUIRED: 1. IC 74002. IC 74103. IC 74204. IC 74045. IC 741536. IC 74139

Circuit Diagram: ( Demux Circuit using NAND Gates)

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LAB #10

Truth Table:

VERIFICATION OF IC 74139 (DEMUX)

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2) Stage a1 (apply)

Procedure


In case of trouble:


Truth Table for IC 74149(DEMUX):

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6) Stage v (verify)

1. What is a de-multiplexer? 2. What are the applications of de-multiplexer?


Assignment:

1. Derive the Boolean expression for de-multiplexer. 2. What is the difference between multiplexer & demultiplexer?

Statement Purpose:Designing one and two bit comparator and study of 7485 magnitude comparator

Activity Outcomes:To understand Boolean logic of one and two bit comparator and study of 7485 magnitude comparator

1) StageJ(Journey)

To realize One & Two Bit Comparator and study of 7485 magnitude comparator.

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LAB #11

Journey:Magnitude Comparator is a logical circuit, which compares two signals A and B andgenerates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a highspeed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B Inputmust be held high for proper compare operation.

Components Required1. IC 7400,2. IC 74103. IC 74204. IC 74325. IC 74866. IC 74027. IC 74088. IC 74049. IC 7485

1 Bit Magnitude Comparator:

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Truth Table:

2 Bit Magnitude Comparator:

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Circuit Diagram of 2 Bit Magnitude Comparator:

Truth Table:

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TO COMPARE THE GIVEN DATA USING 7485 IC:

2) Stage a1 (apply)1. Check the components for their working. 2. Insert the appropriate IC into the IC base.3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.5. RESULT: One bit, two bit and four bit comparators are verified using basic gates and

magnitude comparator IC7485

3) Stage v (verify)

1. What is a comparator? 2. What are the applications of comparator? 3. Derive the Boolean expressions of one bit comparator and two bit

comparators. 4. How do you realize a higher magnitude comparator using lower bit

comparator 4) Stage a2 (assess)

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1. Design a 2 bit comparator using a single Logic gates?2. Design an 8 bit comparator using a two numbers of IC 7485?

Statement Purpose:Designing 2:4 decoder using logic gates

Activity Outcomes:To understand Boolean logic of Designing 2:4 decoder using logic gates

1) StageJ(Journey)

A decoder is a combinational circuit that connects the binary information from ‘n’ input linesto a maximum of 2n unique output lines. Decoder is also called a min-term generator/maxterm generator. A min-term generator is constructed using AND and NOT gates. The appropriate output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND gates. The appropriate output is indicated by logic 0 (Negative logic). The IC 74139 accepts two binary inputs and when enable provides 4 individual active low outputs. The device has 2 enable inputs (Two active low).

Circuit Diagram (2 to 4 Line Decoder):

Truth Table:

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LAB #12

Boolean Expression:

2) Stage a1 (apply)

Procedure1. Make the connections as per the circuit diagram.2. Change the values of A, B, and C, using switches. 3. Observe status of Y0, to Y3 on LED’s. 4. Verify the truth table.

3) Stage v (verify)

What are the applications of decoder? 2. What is the difference between decoder & encoder? 3. For n- 2n decoder how many i/p lines & how many o/p lines? 4. What are the different codes & their applications? 5. What are code converters?


Assignment:

1. Using 3:8 decoder and associated logic, implement a full adder?2. What is the difference between decoder and de-mux?

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Statement Purpose:To set up and test a 7-segment static display system todisplay numbers 0 to 9

Activity Outcomes:To understand Boolean logic of universal logic gates

1) StageJ(Journey)The Light Emitting Diode (LED) finds its place in many applications in these modern electronic fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven Segment LED arrangement. The Light Emitting Diode (LED), finds its place in many applications in this modern electronic fields. One of them is the Seven Segment Display. Seven-segment displays contains the arrangement of the LEDs in “Eight” (8) passion, and a Dot (.) with a common electrode, lead (Anode or Cathode). The purpose of arranging it in that passion is that we can make any number out of that by switching ON and OFF the particular LED's. Here is the block diagram of the Seven Segment LED arrangement.

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LAB # 13

2) Stage a1 (apply)

Procedure:1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.

3) Stage v (verify)

1. What are the different types of LEDs?

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1. Draw the internal circuit diagram of an LED. 2. What are the applications of LEDs?

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Statement Purpose:To set up a circuit of Decimal-to-BCD Encoder using IC 74147.

Activity Outcomes:To learn about various applications of Encoders

1) StageJ(Journey)

An encoder performs a function that is the opposite of decoder. It receives one or more signals in an encoded format and output a code that can be processed by another logic circuit. One of the advantages of encoding data, or more often data addresses in computers, is that it reduces the number of required bits to represent data oraddresses. For example, if a memory has 16 different locations, in order to access these 16 different locations, 16 lines (bits) are required if the addressing signals are in 1 out of n format. However, if we code the 16 different addresses into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed of information processing in digital systems.


1. IC 741472. IC 741483. IC 741574. Patch chords & IC Trainer Kit

Tools:


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LAB # 14

2) Stage a1 (apply)

1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.

3) Stage v (verify)

1. What is a priority encoder? 2. What is the role of an encoder in communication?


Assignment:

1. What is the advantage of using an encoder? 2. What are the uses of validating outputs?

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Statement Purpose:

Truth Table verification of 1) RS Flip Flop 2) T type Flip Flop. 3) D type Flip Flop. 4) JK Flip Flop. 5) JK Master Slave Flip Flop.

Activity Outcomes:

To learn about various Flip-Flops To learn and understand the working of Master slave FF To learn about applications of FFs Conversion of one type of Flip flop to another

1) StageJ(Journey)COMPONENTS REQUIRED:IC 7408, IC 7404, IC 7402, IC 7400, Patch Cords & IC Trainer Kit.

Logic circuits that incorporate memory cells are called sequential logic circuits; their output depends not only upon the present value of the input butalso upon the previous values. Sequential logic circuits often require a timing generator (aclock) for their operation.The latch (flip-flop) is a basic bi-stable memory element widely used in sequential logic circuits. Usually there are two outputs, Q and its complementary value. Some of the most widely used latches are listed below. SR LATCH: An S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using cross-coupled NAND gates as shown. The truth tables of the circuits are shown below. A clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called “enabled” S-R flip-flop. A D latch combines the S and R inputs of an S-R latchinto one input by adding an inverter. When the clock is high, the output follows the D input, and when the clock goes low, the state is latched. A S-R flip-flop can be converted to T-flip flopby connecting S input to Qb and R to Q.

Components Required1. IC 74082. IC 74043. IC 74024. IC 74005. Patch Cords & IC Trainer Kit.

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LAB # 15

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2) Stage a1 (apply)Procedure:1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.

3) Stage v (verify)

1. What is the difference between Flip-Flop & latch? 2. Give examples for synchronous & asynchronous inputs? 3. What are the applications of different Flip-Flops?

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1. What is the advantage of Edge triggering over level triggering? 2. What is the relation between propagation delay & clock frequency of flip-flop? 3. What is race around in flip-flop & how to overcome it? 4. Convert the J K Flip-Flop into D flip-flop and T flip-flop? 5. List the functions of asynchronous inputs

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Statement Purpose:

To design and test 3-bit binary asynchronous counter using flip-flop IC 7476 for the given sequence.

Activity Outcomes:To learn about Asynchronous Counter and its application

To learn the design of asynchronous up counter and down counter

1) StageJ(Journey)

A counter in which each flip-flop is triggered by the output goes to previous flip-flop.

As all the flip-flops do not change state simultaneously spike occur at the output. To avoid

This, strobe pulse is required. Because of the propagation delay the operating speed of asynchronous counter is low. Asynchronous counter areeasy and simple to construct.

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LAB # 16

2) Stage a1 (apply)

Procedure:

1. Check all the components for their working. 2. Insert the appropriate IC into the IC base. 3. Make connections as shown in the circuit diagram. 4. Verify the Truth Table and observe the outputs.

3) Stage v (verify)1. What is an asynchronous counter? 2. How is it different from a synchronous counter?


Assignment:

Realize asynchronous counter using T flip-flop

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Course: CSC--- Digital Logic Design - Muhammadiyahmnk.muhammadiyah.info/Lab Manuals/ver...

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