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8/10/2019 Course Introduction to Uvm Session8 Transactions Rsalemi
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[email protected] | www.verificationacademy.com
Introduction to the UVMTransact ions
Ray Salemi
Senior Verification Consultant
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Ray SalemiSenior Verification Consu
Introduction to
Advanced VerificationIntroduction
the UVM 2014 M
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Agenda
1. SystemVerilog for VHDL Engineers
2. Object Oriented Programming
3. SystemVerilog Interfaces4. Packages, Includes, and Macros
5. UVM Test Objects
6. UVM Environments
7. Connecting Objects
8. Transaction Level Testing9. The Analysis Layer
10. UVM Reporting
11. Functional Coverage with Covergroups
12. Introduction to Sequences
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Abstracting Complexity Away
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Abstracting Complexity Away
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Abstracting Complexity Away
+
X FF
X FF
FF
A
B
CD
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Thinking in Transactions
0nop
7
2
14
5
ValueField
d
c
b
a
0nop
7
2
14
5
ValueField
d
c
b
a
INPUT_TRAN
Field
result
Field
result(a*b) + (c*d)
RESULT_T
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Transaction Level Test Bench
Driver
RTL
or
Gate
clock
input_ready
Responder
result[15:0]b[7:0]
c[7:0]
d[7:0]
a[7:0]
result_ready
input
transaction
result
transaction
rst
Driver
RTL
or
Gate
clock
input_ready
Responder
result[15:0]result[15:0]b[7:0]b[7:0]
c[7:0]c[7:0]
d[7:0]d[7:0]
a[7:0]a[7:0]
result_ready
input
transaction
result
transaction
rst
Driver
RTL
or
Gate
clock
input_ready
Responder
result[15:0]b[7:0]
c[7:0]
d[7:0]
a[7:0]
result_ready
input
transaction
result
transaction
rst
Driver
RTL
or
Gate
clock
input_ready
Responder
result[15:0]result[15:0]b[7:0]b[7:0]
c[7:0]c[7:0]
d[7:0]d[7:0]
a[7:0]a[7:0]
result_ready
input
transaction
result
transaction
rst
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Running Tests
gen
(generator) stim_f result_f readerDriverRTLor
Gate
clock
input_ready
Responder
result[15:0]b[7:0]
c[7:0]
d[7:0]
a[7:0]
result_ready
rst
DriverRTLor
Gate
clock
input_ready
Responder
result[15:0]result[15:0]b[7:0]b[7:0]
c[7:0]c[7:0]
d[7:0]d[7:0]
a[7:0]a[7:0]
result_ready
rst
DriverRTLor
Gate
clock
input_ready
Responder
result[15:0]b[7:0]
c[7:0]
d[7:0]
a[7:0]
result_ready
rst
DriverRTLor
Gate
clock
input_ready
Responder
result[15:0]result[15:0]b[7:0]b[7:0]
c[7:0]c[7:0]
d[7:0]d[7:0]
a[7:0]a[7:0]
result_ready
rst
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Memory Testbench Transactions
mem_data
logic[15:0]data
logic[15:0]addr
ValueField
mem_data
logic[15:0]data
logic[15:0]addr
ValueField
mem_req
{read, writop
logic[15data
logic[15addr
ValueField
mem_req
{read, writop
logic[15data
logic[15addr
ValueField
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Transactions are Objects
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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Wh t k it T ti ?
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What makes it a Transaction?Extension
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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Wh t k it T ti ?
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What makes it a Transaction?`uvm_object_utils
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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What makes it a Transaction?
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What makes it a Transaction?constructor
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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Wh t k it T ti ?
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What makes it a Transaction?virtual function string convert2string()
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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Wh t k it T ti ?
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What makes it a Transaction?virtual function void do_copy(uvm_object rhs)
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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i t b t h
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load_data()is not necessary but he
mem_da
logidata
logiaddr
VField
mem_da
logidata
logiaddr
VField
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Extending Objects
Whenever you will copy code, consider exten
mem_data
logic[15:0]data
logic[15:0]addr
ValueField
mem_data
logic[15:0]data
logic[15:0]addr
ValueField
mem_req
{read, writop
logic[15data
logic[15addr
ValueField
mem_req
{read, writop
logic[15data
logic[15addr
ValueField
mem_req is just mem_dat
with an operation
So we extend!
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T ti
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mem_reqTransaction
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C d
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mem_req Code
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L < th d >
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Leverage super.
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Creating d () for this transaction
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Creating do_copy()for this transaction
This is why we use
uvm_object in the
parameter list
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Can even leverage l d d t ()
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Can even leverage load_data()
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Creating the TLM Testbench
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Creating the TLM Testbench
tester_e
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)responder(rsp)memory_if
driver(drv)
memory_
2014 M
verbose test
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verbose_test
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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tester env
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tester_env
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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tester env(cont)
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tester_env(cont)
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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tester
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tester
Abstraction in
action
Easy to
understand
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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tester (cont)
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tester (cont)
Where did clone
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
2014 M
interface base (cannot be used direct
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interface_base(cannot be used direct
Means that interface_base must be
extended. It cannot be used directl
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driver
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driver
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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responder
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responder
G
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
2014 M
printer
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printer
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
2014 M
Running the Test
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Running the Test
Transa
Transa
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The quiet test
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The quiet_test
Replace theprinterwith abit_buck
the factory
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bit bucket
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_
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
Inherits port interface from it
superclass the printer.
Get the data and throw it away
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quiet test
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q _
The environment thinks it is getting a printerfrom th
factory, but it is really getting a bit_bucket.
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
driver(drv)
memory_if
verbose_test
tester_env(t_env)
tester(tst)
printer(prt)
tlm_fifo(tester2drv)
tlm_fifo(rsp2printer)
responder(rsp)
memory_if
responder(rsp)
memory_if
driver(drv)
memory_if
driver(drv)
memory_if
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Run Quietly
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u Qu et y
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Summary: TLM Test Bench
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y
tester_
tester(tst)
printer
(prt)
tlm_fifo(tester2drv)
tlm_fifo
(rsp2printer)
responder
(rsp)
memory_if
driver(drv)
memory_
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Next Session
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1. SystemVerilog for VHDL Engineers
2. Object Oriented Programming
3. SystemVerilog Interfaces
4. Packages, Includes, and Macros
5. UVM Test Objects
6. UVM Environments
7. Connecting Objects
8. Transaction Level Testing
9. The Analysis Layer
10. UVM Reporting
11. Functional Coverage with Covergroups
12. Introduction to Sequences
2014 M
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[email protected] | www.verificationacademy.com
Introduction to the UVMTransact ions
Ray Salemi
Senior Verification Consultant