CONTACT: Email: [email protected]Tel.: 33.1.41.87.30.00 www.adas.fr APPLICATIONS ♦ 64 programmable digital I/O for each channel port ♦ High switching power of 70 V/100 mA ♦ TTL-compatible inputs/ outputs ♦ Protected inputs (70 V) ♦ Playback of outputs ♦ 16 interrupt sources ♦ "Photo" mode and external latch ♦ External and PXI triggers et sync. ♦ Programmable watchdog with predetermined fall-back values ♦ High reliability/high density ♦ Drivers supplied and supported CPCI 1264 board provides 64 programmable digital inputs/outputs for each 8-channel port. Inputs/outputs can be refreshed at any time, or under control of a timer, PXI triggers, or an external tick on front panel. Outputs provide the necessary power for components such as small relays, lamps ,displays, etc. Inputs are diode-protected (70 V max.) and remain TTL- compatible. CPCI 1264 features a programmable watchdog. If the latter “falls”, preset fall-back values will be displayed at the outputs (security process). The interrupts can be edge triggered for each of the first 16 channels. The interrupt sources are maskable. 64 DIGITAL INPUTS/OUTPUTS CPCI 1264 CHANNELS Number of channels 64 Direction Direction programming in 8 groups of 8 channels DIGITAL OUTPUTS Type Open collector DATA 1 = ON ; 0 = OFF Max. sust. voltage 70 V Max. current 100 mA Max. power 2 W DIGITAL INPUTS Type TTL compatible triggers Protection 70 V max. Vce SAT < 300 mV at 100 mA Switching time T"on" = 500 ns ; T"off" = 2.5 μs (RL = 1 kΩ ) Impedance ≥ 470 kΩ Readback These inputs enable automatic readback of the channels programmed as outputs Input frequency 100 kHz maximum Debounce All channels together: synchro ; 1μs ; 10μs ; 100μs Watchdog With/without available programmed outputs state POWER UP Channels programmed as inputs Output registers at "0" "off" state INTERRUPTS 16 channels can generate an interrupt as can the timers 1 interrupt level on « INTA » SPECIFICATIONS*
Documentation française Rév. B - Edition 3 – 10/18
Revised
Approved
Written
by
by
by B. THOUËNON
D. PIMONT
M. ROCHE
on
on
on
10/18
10/18
10/18
Visa
Visa
Visa
Warning: Unless otherwise stated, this revision overwrites the previous one which must be destroyed, along with any copies given to your collaborators.
Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.
Table of the modifications Table des évolutions (mots clés)
Page n°
B.7.1. Registre de contrôle 1 14
Mise à jour Data-Sheet, Correction erreur de syntaxe
DSQ - 4.5.a - Indice G – 28/02 T.S.V.P.
CPCI 1264 - Rev. B - Edition 3 – 10/18
2
NOTES :
CPCI 1264 - Rev. B - Edition 3 – 10/18
3
CPCI 1264
SOMMAIRE
Chapitre A Présentation .........................................5
A.1. Câblage et interconnexion......................................................5
Chapitre B Interface PCI .........................................6
REGISTRES DE CONFIGURATION PCI.....................................................34
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Chapitre A Présentation
La carte CPCI 1264 est une carte Compact PCI de format 3U. Elle est conçue pour gérer 64 entrées/sorties tout ou rien protégées. Les entrées sont protégées jusqu’à 70V et les sorties ont un pouvoir de coupure élevé, ce qui autorise la commande de petits relais, de voyants tout en restant compatible TTL. Un grand nombre de borniers existe dans notre offre STB et BCI pour assurer tout type d’interfaces. Les plus de la carte :
! Extension PXI avec possibilité de 4 triggers : TRIG0 ; TRIG1 ; TRIG2 ; TRIG STAR
! Filtre antirebond programmable pour l’ensemble des entrées : Synchro ; 1μs ; 10μs ; 100μs
! Fonction chien de garde très complète avec valeurs de replis programmables pour les processus de haute sécurité.
A.1. Câblage et interconnexion
Si le lecteur le souhaite, des exemples applicatifs d’interconnexions sont sur notre site internet www.adas.fr Cliquez sur l’icône : au chapitre « Câblage & configuration ».
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Chapitre B Interface PCI B.1. Avertissements
La carte CPCI 1264 est une carte qui s’insère dans un système possédant des connecteurs Compact PCI 32 bits. Elle présente de ce fait toutes les caractéristiques liées à cet environnement (PCI 2.1.). L’interface PCI est assurée par un composant spécialisé : AMCC S5335
B.2. Littérature Nous recommandons vivement au lecteur de se procurer la littérature suivante :
PCI HARDWARE and SOFTWARE
Architecture et Design Written by Edward SOLARI et George WILLSE
Edit. : ANNA BOOKS
ET
AMCC PCI CONTROLLERS
S5335 DATA BOOK
CPCI 1264 - Rev. B - Edition 3 – 10/18
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B.3. Registres de configuration PCI
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8
Pour la carte CPCI 1264, les registres sont configurés comme suit à la mise sous tension :
03 02 01 00
885C 10E8
0 0
0 0A
FFFFFFC0H
FFFFFFC0H
00
FFFF0001H
00 00 01 0B
00
00
00
00
00
00
00
3CH
38H
34H
30H
2CH
28H
24H
20H
1CH
18H
14H
10H
08H
04H
00H
D31 D0
0CH
ETAT A LA MST (Mise sous tension)
00
FF 0
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885C 10E8
0 0
FF 0 00 0A
FFFFFFC0H
FFFFFFC0H
00
00
00
00
00
00
FFFFF0001H
00
00
00 00 01 0B
D31 D0
3CH
38H
34H
30H
2CH
28H
24H
20H
1CH
18H
14H
10H
0CH
08H
00H
64K octets
EPROM
BOOT
AMCC at the
Power-up
16D wordsPCI USER REGISTER
CTL 00H
DOG 04H
LATCH 08H
INIT 0CH
DIRECT 1 10H
DIRECT 2 14H
BUFF 1 18H
BUFF 2 1CH
FRMQ 20H
ITIM 24H
28H
Control register
Maintening the watchdog
Synchronous update
Software reset
Direct read/write register G1
Direct read/write register G2
Read/write buffer G2
Masks and Interrupt Edges Registers IT
Timer and interrupt control IT
Read/write buffer G1
16D words
PCI OPERATION REGISTER
00H
Abreviations
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
Incoming Mailbox Register 1
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
NU CPCI 1264
Mailbox Empty/Full status
Interrupt Control/Status Register
Bus Master Control/Status Register
IMB1
MBEF
INTCSR
MCSR
CPCI 1264 CONFIGURATION
V31 Falling back V0
V63 Falling back V32 2CH
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B.4. Registres opérationels PCI
Ces 16 registres 32 bits sont accessibles via l’adresse 10H de l’espace de configuration (voir chapitre B.3. REGISTRES DE CONFIGURATION PCI).
10H FF FF FF C0
La carte CPCI 1264 n’utilise pas l’intégralité de ces registres mais seulement les registres suivants :
ADRESSE OFFSET ABREVIATION NOM DU REGISTRE
10H IMB1 Incoming MailBox register 1 34H MBEF MailBox Empty / Full status 38H INTCSR INTerrupt Control / Status Register 3CH MCSR Bus Master Control / Status Register
Ces registres concernent la carte dans le mode de fonctionnement esclave. Dans un but didactique, nous avons donné le contenu de l’ensemble des 16 registres vu du PCI au chapitre B.3.
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B.5. Registres utilisateur PCI
Ces 16 registres 32 bits sont accessibles via l’adresse 14H de l’espace de configuration.
14H FF FF FF C0
La carte CPCI 1264 n’utilise pas l’intégralité de ces registres, seuls les registres suivants sont opérationnels :
R/W Contrôle 2 Contrôle 1 Direction
FF FF C0 00 Base +0H
W0 Entretien chien de garde
FF FF FF FF + 4H
W0 Mise à jour synchrone (18H et 1CH)
FF FF FF FF + 8H
W0 Initialisation logicielle
FF FF FF FF + CH
R/W V31 Lecture/Ecriture directe G1 V0
00 00 00 00 + 10H
R/W V63 Lecture/Ecriture directe G2 V32
00 00 00 00 + 14H
R/W V31 Lecture/Ecriture G1 V0
Sans mise à jour + 18H
00 00 00 00
R/W V63 Lecture/Ecriture G2 V32
Sans mise à jour + 1CH
00 00 00 00
R/W FRONT V(15-8) FRONT V(7-0) MASK V(15-8) MASK V(7-0)
00 00 00 00 + 20H
R/W CTL interruption Timer 16 bits
00 00 00 00 + 24H
R/W V31 Valeurs Replis chien de garde V0 + 28H
00 00 00 00
R/W V63 Valeurs Replis chien de garde V32 + 2CH
00 00 00 00
NU + 3FH
D31 D24 D23 D16 D15 D8 D7 D0
La valeur en italique est la valeur Hexadécimale à la MST : R/W : Ecriture / Lecture W/0 : Ecriture seulement
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B.6. Registre de direction
Adresse de base + 0H Accès en lecture/écriture - 00H à la mise sous tension
Sens voies 63-56
Sens voies 55-48
Sens voies 47-40
Sens voies 39-32
Sens voies 7-0
Sens voies 15-8
Sens voies 23-16
Sens voies 31-24
D7 D6 D5 D4 D3 D2 D1 D0
Un bit à « 0 » positionne les voies concernées en entrée. Un bit à « 1 » positionne les voies concernées en sortie. Toutes les voies sont en entrée à la mise sous tension.
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B.7. Registres de contrôles
Les 2 registres de contrôles sont contigus avec le registre de direction. B.7.1. Registre de contrôle 1 Adresse de base + 1H Accès en lecture/écriture C0H à la mise sous tension
Etat fusible F1
Etat fusible F1
D15 D14 D13 D12 D11 D10 D9 D8
FUS1 FUS1 DB1 DB0 M3 M2 M1 M0
Modes de fonctionnement
Filtre des entrées (Debounce) Ce registre est essentiellement consacré aux modes de fonctionnement des latchs des E/S. Mode de fonctionnement des latchs entrées/sorties
Le fonctionnement des différents modes de latch sera expliqué dans les chapitres suivants.
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Filtrage des entrées
Il peut être necessaire de filtrer les entrées digitales si celles-ci ont des rebonds. Les bits D13 D12 (DB1 et DB0) selectionnent le filtrage pour l’ensemble des entrées.
La période d’incertitude (I) doit être évitée afin de conserver toute son intégrité au signal.
Fusible : Les deux bits D15 et D14 servent à connaître l’état du fusible alimentant en 5V le connecteur J1 sur la broche 1 (cette alimentation peut servir à alimenter les borniers de conditionnement). Lus à « 1 » pas de défaut fusible Lus à « 0 » défaut fusible
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B.7.2. Registre de contrôle 2 Ce registre est consacré à la fonction « chien de garde » Adresse de base + 2H Accès en lecture/écriture FFH à la mise sous tension
D23 D22 D21 D20 D19 D18 D17 D16
NU NU ECG1 ECG0 UCG1 UCG0 VCG1 VCG0
ECG1 ECG0 ENTRETIEN DU CG VCG1 VCG0 VALEUR DU CG
0 0 DOG ALL (Read/write on board) 0 0 ≥ 32ms
0 1 WRT (04H) only 0 1 ≥ 8ms
1 0 Latch only 1 0 ≥ 2ms
1 1 INACTIF (MST) 1 1 Pas de chien de garde (MST)
UCG1 UCG0 RESULTANTE SI CG TOMBE
0 0 RAZ : Carte en entrées
0 1 Fige les E/S en l’état
1 0 Chargement des valeurs de replis en sorties (28H et 2CH)
1 1 INACTIF (MST)
Jusqu’au reset Hard ou Soft
Sans rafraîchissement, le chien de garde tombe après le temps choisi.
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B.8. Initialisation logicielle
Adresse base + 0CH Une écriture fictive à l’adresse de base + 0CH permet de réinitialiser la carte CPCI 1264. Les ressources PCI ne sont pas réinitialisées. L’initialisation de la carte CPCI 1264 possède 4 sources.
! Initialisation totale lors de la mise sous tension ou par le signal RST* du bus PCI
! Initialisation logicielle des entrées/sorties (adresse base + 0CH) La carte se remet en entrée, les sorties sont positionnées à zéro
! Chute du chien de garde (mêmes fonctions réinitialisées que par logiciel avec UCG1 et UCG0 = ∅ en base + 2H)
! Positionnement par bit D24 du registre 3CH (registres opérationnels de l’AMCC
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B.9. Entretien du chien de garde
Adresse base + 4H Une écriture fictive à l’adresse de base + 4H entretient le chien de garde (si celui-ci est armé). La durée entre 2 écritures est fonction des 2 bits VCG0 et VCG1 du registre de contrôle 2. Cette écriture fictive n’entretient le chien de garde que dans le cas où les bits D21 et D20 (ECG1 et ECG0) sont à l’état 00 ou 01. Les bits D21 et D20 (ECG1 et ECG0) à l’état 00 ou 10 permettent d’entretenir le chien de garde par un latch sur les entrées / sorties. Si ce dernier tombe, les sorties sont positionnées en fonction des 2 bits D19 et D18 (UCG1 et UCG0).
00 RAZ, toutes les voies sont positionnées en entrée 01 L’état des entrées et des sorties est figé à la dernière valeur
latchée 10 Les voies en sorties sont positionnées à la valeur des
registres des valeurs de replis (28H et 2CH)
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B.10. Mise à jour synchrone (LATCH)
Adresse base + 8H Une écriture fictive à l’adresse de base + 8H permet de mémoriser les valeurs d’entrées et de transférer les registres en sortie de façon synchrone. En entrée : L’état des voies est mémorisé par groupe de 8 voies, cet
état est maintenu jusqu’à la lecture de l’octet considéré. En sortie : Les valeurs préalablement écrites dans les registres 18H et
1CH sont transférées en mode synchrone vers les buffers de sortie.
La mise à jour synchrone consiste à synchroniser le chargement des registres d’entrées ou de sorties au rythme d’un signal déterminé. C’est le déclenchement périodique des photos d’entrées et de sorties de la carte. Nous avons vu dans le registre de contrôle 1 qu’il existait 8 possibilités de synchronisation des latchs.
Synchro logicielle : Mode 0
M3 M2 M1 M0 0 0 0 0
SOFT
Synchro au rythme du Timer : Mode 4
M3 M2 M1 M0 0 1 0 0
TIMER
Voir le chapitre du Timer pour la périodisation des rafraîchissements.
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Synchro sur signal de FAV LEMO : Mode 2
M3 M2 M1 M0 0 0 1 0
Lemo FAV
Synchro sur changement d’état d’une voie : Mode 8
M3 M2 M1 M0 1 0 0 0
IT VOIE
Voir le chapitre des interruptions issues des voies d’entrées pour ce mode.
Synchro sur les triggers de fond de panier PXI
TRIGGERS PXI :
MODE M3 M2 M1 M0 PXI
3 0 0 1 1 TRIG0 7 0 1 1 1 TRIG1 B 1 0 1 1 TRIG2 F 1 1 1 1 TRIG STAR
Remarque : La forme et les niveaux des signaux sont donnés dans le chapitre C – Mise en œuvre.
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B.11. Registre de lecture / écriture
Les voies en sortie peuvent être latchées par des sources d’origines différentes :
! En mode direct par écriture dans les registres base + 10H et base + 14H
! En mode synchrone par les stimuli suivants : Par la commande de mise à jour synchrone à l’adresse
de base + 8H (transfert des valeurs écrites en base + 18H et en base+ 1CH)
Par le Timer Par la prise LEMO de Face Avant (S). Le latch se fait
sur un Pulse TTL 50ns minimum sur front descendant
50ns min Par une des entrées générant une interruption Par un des quatre TRIGGERS du Fond de panier PXI
Remarque : En mode synchrone « Logiciel » il faut respecter l’ordre en fonction d’une écriture ou d’une lecture des voies.
! Ecriture des données : Précharger les registres 18H et 1CH puis effectuer une écriture en 08H
! Lecture des données : Effectuer un latch par un accès en 08H puis lire les données dan les registres 18H et 1CH.
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B.12. Registre de lecture / écriture directe
Adresse 10H et 14H Accès en lecture/écriture 00H à la mise sous tension Ces registres servent à lire et à écrire les 64 voies de la carte avec mise à jour immédiate. Les bits D31 à D0 du registre base + 10H correspondent aux voies logiques V31 à V0 respectivement. Les bits D31 à D0 du registre base + 14H correspondent aux voies logiques V63 à V32 respectivement. La lecture ou l’écriture est directe En lecture, on obtient la valeur instantanée de chaque voie. En écriture, le changement de la sortie considérée est immédiat. (temps d’établissement de l’électronique : t « on » ; t « off »). C’est l’utilisation classique d’une carte d’entrées/sorties digitales. Le mode sera le mode ∅ état du registre de contrôle 1 à la MST, le latch est transparent.
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B.13. Registres des lectures / écritures synchrones
Adresse 18H et 1CH Accès en lecture/écriture 00H à la mise sous tension. Ces registres servent à lire et à écrire les 64 voies de la carte avec mise à jour synchrone évoquée au paragraphe précédent. En sortie : Lorsque l’on écrit dans ces registres, les valeurs de sortie
ne changent pas tant que l’on ne latche pas. En entrée : Après une commande de latch, les valeurs mémorisées sont
lues dans ces registres. Le fait de lire les registres remet les latchs d’entrée en transparent (par octet).
Les bits D31 à D0 du registre base + 18H correspondent aux voies logiques V31 à V0 respectivement. Les bits D31 à D0 du registre base + 1CH correspondent aux voies logiques V63 à V32 respectivement.
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B.14. Timer
Accès lecture/écriture, Etat 00H à la mise sous tension Adresse base +24H et +25H
D15 D8 D7 D0
Valeur du Timer (V)
Ce timer est alimenté par une fréquence issue de l’horloge CPCI divisée par 1280 soit 26kHz. Ce timer peut générer une interruption et/ou servir de latch en entrée et en sortie à intervalles réguliers.
Période : Fclk1280 = 38,4µs
Période du Timer = (V + 1) x 38,4µs V ≠ 0 NOTA : Pour utiliser le Timer en mode Latch des E/S, sélectionner le mode 4 dans le registre de contrôle 1
M3 M2 M1 M0 0 1 0 0
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B.15. Interruptions
La carte CPCI 1264 possède des ressources d’interruption qui peuvent être ou non utilisées. Quatre sources d’interruptions sont rencontrées :
! Les 16 premieres voies de la carte,
! Le Timer,
! Le chien de garde,
! 1 des Triggers externes. Les sous-chapitres qui suivent décrivent ces 4 possibilités B.15.1. Registre des masques des 16 premieres voies Accès lecture/écriture 00H à la mise sous tension >>Registres des masques : Adresses 20H et 21H
D15 D8 D7 D0
M15 M8 M7 M0
Masque Masque Voies 15 à 8 Voies 7 à 0
Le choix du masque des voies pouvant générer une interruption se fait par le positionnement des bits M15 à M0 correspondant respectivement aux voies logiques V15 à V0. Un bit à « 0 » : le masque est positionné Un bit à « 1 » : l’interruption est autorisée
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B.15.2. Registre des fronts des 16 premières voies Accès lecture / écriture, 00H à la MST >>Registres des fronts : Adresses 22H et 23H
D31 D24 D23 D16
FR15 FR8 FR7 FR0
Front Front Voies 15 à 8 Voies 7 à 0
Le choix du front de l’interruption se fait par le positionnement des bits FR15 à FR0 correspondant respectivement aux voies logiques V15 à V0. Un bit à « 0 », le front est montant Un bit à « 1 », le front est descendant B.15.3. Registre de contrôle des interruptions Contrôle des interruptions - Adresse 26H et 27H Accès lecture uniquement - 00H à la mise sous tension
D31 D24 D23 D19 D18 D17 D16
Lus à 0 R19 R18 R17 R16
Ces 4 bits permettent de connaître la provenance de l’interruption : R16 Passe à « 1 » lorsque le timer est la cause de l’interruption R17 Passe à « 1 » lorsqu’une des voies autorisées est la cause de l’interruption R18 Passe à « 1 » lorsque le chien de garde tombe R19 Passe à « 1 » lorsque 1 Trigger externe est la cause de l’interruption Le fait de lire ce registre remet les bits à « 0 ».
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B.16. Le chien de garde
La carte CPCI 1264 a été particulièrement étudiée pour les environnements industriels et les processus nécessitant un haut degré de fiabilité et de sécurité. Un chien de garde avec des ressources associées est présent pour ce type d’équipement. B.16.1. Les possibilités Nous avons vu au chapitre B.7.2. la configuration du registre de contrôle spécialement attribué au chien de garde. Valeur du temps d’activité : Pas de CG ; 2ms ; 8ms ; 32ms
Entretien du chien de garde : ! Lors des lectures/écritures sur la carte (code 00)
! Ecriture uniquement à l’adresse basse +04H (code 01)
! Lors d’un Latch des registres entrées / sorties quelque soit l’origine de celui-ci (HARD ou SOFT) (code 10)
Résultat si le chien de garde « tombe » ! RAZ de la carte qui se repositionne en entrée (état MST)
(code 00)
! Fige les E/S à l’état présent lors de la chute du CG (code 01)
! Chargement en sorties des valeurs de replis prédeterminées dans les registres base + 28H et + 2CH (code 10)
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B.16.2. Registres de replis
On écrit dans ces registres la valeur prédéfinie des sorties si le chien de garde « tombe ».
V31 Valeurs de replis V0 28HV63 Valeurs de replis V32 2CH
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Chapitre C Structure des voies
Chaque voie peut être assimilée au schéma suivant :
+ 5V
Clamp
Clamp
Carte I/O
CSWRT
DATA "D" O.C
La diode de "clamping" doit être polarisée au potentiel le plus élevé utilisé Exemple : Contrôle relais
Relais
Vx
1 J1 + 24V
24V retour
Diode "clamping"
GND
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Chapitre D Alimentation des borniers d’interfaces
La carte CPCI 1264 permet d’alimenter des borniers d’interfaces. L’utilisation de cette possibilité est néanmoins peu conseillée dans le cadre d’applications où il existe plusieurs borniers car les problèmes suivants peuvent apparaître :
! perte en ligne dans des nappes trop longues
! consommation importante et risques au niveau de l’alimentation du rack CPCI.
Un fusible réarmable de 1,5A protège cette sortie 5V. Remarque : Si la consommation est importante, le fusible disjoncte et les bits D14 et D15 du registre contrôle 1 passent à « 0 ».
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Chapitre E Connectique et DELs
E.1. Connecteurs
La carte CPCI 1264 possède 1 connecteur µD68pts pour câble plat de type micronappe 68 pts (J1). Câble préconisé : WR368/XXX vers les borniers. La carte CPCI 1264 possède également 1 prise LEMO pour le latch externe (S).
+ 5V
II
ABT 245
LEMO
Le tableau page suivante définit le brochage de J1
E.2. DELs La DEL A sur la face avant indique que la carte reçoit des latchs. La DEL B sur la face avant indique les accès du Bus PCI. La DEL C sur la face avant indique que le chien de garde est tombé.
CPCI J2 PIN ASSIGNMENT Connecteur femelle Bornes utilisées en gras
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Chapitre F Les borniers de couplage
La CPCI 1264 peut être raccordée à différents types de borniers ADAS rendant l'interconnexion avec le monde extérieur particulièrement aisée. Les plans ci-après illustrent les différentes possibilités.
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Annexe
PLAN DE CONFIGURATION
PLANS D’EQUIPEMENT
REGISTRES DE CONFIGURATION PCI
CPCI 1264
35
NOTE AU LECTEUR Ce chapitre est laissé volontairement en anglais afin de garder les termes utilisés dans la norme PCI.
00h–01h VID Vendor Identification02h–03h DID Device Identification04h–05h PCICMD PCI Command Register06h–07h PCISTS PCI Status Register08h RID Revision Identification Register09h–0Bh CLCD Class Code Register0Ch CALN Cache Line Size Register0Dh LAT Master Latency Timer0Eh HDR Header Type0Fh BIST Built-in Self-test10h–27h BADR0-BADR5 Base Address Registers (0-5)28h–2Fh — Reserved30h EXROM Expansion ROM Base Address34h–3Bh — Reserved3Ch INTLN Interrupt Line3Dh INTPIN Interrupt Pin3Eh MINGNT Minimum Grant3Fh MAXLAT Maximum Latency40h–FFh — Not used
PCI CONFIGURATION REGISTERSEach PCI bus device contains a unique 256-byte region called its configuration header space. Portions of thisconfiguration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.This section describes each of the configuration space fields—its address, default values, initialization options,and bit definitions—and also provides an explanation of its intended usage.
The VID register contains the vendor identificationnumber. This number is assigned by the PCI SpecialInterest Group and is intended to uniquely identifyany PCI device. Write operations from the PCI inter-face have no effect on this register. After reset isremoved, this field can be boot-loaded from the ex-ternal non-volatile device (if present and valid) so thatother legitimate PCI SIG members can substitute theirvendor identification number for this field.
Bit Description
15 010E8h
Vendor Identification Register (RO)
15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.
15:0 Device Identification Number: This is a 16-bit value initially assigned by AMCC to ADAS applications for PCI 102 card.
The DID register contains the vendor-assigned deviseidentification number. This number is generated by AMCCin compliance with the conditions of the PCI specification.Write operations from the PCI interface have no effect onthis register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present andvalid) so that other legitimate PCI SIG members cansubstitute their own device identification number for thisfield.
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PCI COMMAND REGISTERRegister Name: PCI CommandAddress Offset: 04h-05hPower-up value: 0000hBoot-load: not usedAttribute: Read/Write (R/W on 6 bits,
Only for all others)Size: 16 bits
This 16-bit register contains the PCI Command. Thefunction of this register is defined by the PCI specifi-cation and its implementation is required of all PCIdevices. Only six of the ten fields are used by thisdevice; those which are not used are hardwired to 0.The definitions for all fields are provided here forcompleteness.
15 0
Reserved = 00's
Fast Back-to-BackSERREWait Cycle EnableParity Error EnablePalette SnoopMemory Write and InvalidateSpecial Cycle EnableBus Master EnableMemory AccessI/O Access Enable
X 00 X 0 0 0 XXX
123456789
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15:10 Reserved. Equals all 0’s.
9 Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.This bit is cleared to a 0 upon RESET#.
8 System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drainoutput pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normallysignifies a parity error on the address/control bus.
7 Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5933controller never uses stepping, it is hardwired to 0.
6 Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. Whena parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testingdisabled) upon the assertion of RESET#.
5 Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. Thisfeature is used solely for PCI-based VGA devices.
4 Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the MemoryWrite and Invalidate PCI bus command when set to 1. When set to 0, masters must use the MemoryWrite command instead. The S5933 controller does not support this command when operated as amaster and therefore it is hardwired to 0.
3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when thisbit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit ishardwired to 0.
2 Bus Master Enable. This bit, when set to a one, allows the S5933 controller to function as a bus master.This bit is initialized to 0 upon the assertion of signal pin RESET#.
1 Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target formemory regions that may be defined in one of the five base address registers. This bit is initializedto 0 upon the assertion of signal pin RESET#.
0 I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycleswhich are to regions defined by any one of the five base address registers. This bit is initialized to 0upon the assertion of signal pin RESET#.
Bit Description
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PCI STATUS REGISTER (PCISTS)
Register Name: PCI Status
Address Offset: 06h-07h
Power-up value: 0080hBoot-load: not usedAttribute: Read Only (RO), Read/Write
DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved
This 16-bit register contains the PCI status informa-tion. The function of this register is defined by thePCI specification and its implementation is requiredof all PCI devices. Only some of the bits are used bythis device; those which are not used are hardwiredto 0. Most status bits within this register are desig-nated as “write clear,” meaning that in order to cleara given bit, the bit must be written as a 1. All bitswritten with a 0 are left unchanged. These bits areidentified in Figure 4 as (R/WC). Those which areRead Only are shown as (RO) in Figure 4.
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Bit Description
15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independentlyfrom the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.
14 Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can bereset by writing a 1 to this location.
13 Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset bywriting a 1 to this location.
12 Received Target Abort. This bit is set whenever this device has one of its own initiated cyclesterminated by the currently addressed target. This bit can be reset by writing a 1 to this location.
11 Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.This bit can be reset by writing a 1 to this location.
10:9 Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from thisdevice when accessed as a target.
8 Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involvingthe S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must beset in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this locationor by the assertion of the signal RESET#.
7 Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target.
The RID register contains the revision identificationnumber. This field is initially cleared. Write operationsfrom the PCI interface have no effect on this register.After reset is removed, this field can be boot-loadedfrom the external non-volatile device (if present andvalid) so that another value may be used.
Bit Description
7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.
7 000h
Revision Identification Number (RO)
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CLASS CODE REGISTER (CLCD)Register Name: Class CodeAddress Offset: 09h-0BhPower-up value: FF0000hBoot-load: External nvRAM offset
049h-4BhAttribute: Read OnlySize: 24 bits
This 24-bit, read-only register is divided into threeone-byte fields: the base class resides at location0Bh, the sub-class at 0Ah, and the programming in-terface at 09h. The default setting for the base classis all ones (FFh), which indicates that the devicedoes not fit into the thirteen base classes defined inthe PCI Local Bus Specification. It is possible, how-ever, through use of the external non-volatilememory, to implement one of the defined class codesdescribed in Table 7 below.
For devices that fall within the seven defined classcodes, sub-classes are also assigned. Tables 8through 20 describe each of the sub-class codes forbase codes 00h through 0Ch, respectively.
7 0Sub-Class
7070Base Class Prog I/F
(Bit)(Offset)@09h@0Ah@0Bh
Base-Class Description
00h Early, pre-2.0 PCI specification devices
01h Mass storage controller
02h Network controller
03h Display controller
04h Multimedia device
05h Memory controller
06h Bridge device
07h Simple communication controller
08h Base system peripherals
09h Input devices
0Ah Docking stations
0Bh Processors
0Ch Serial bus controllers
0D-FEh Reserved
FFh Device does not fit defined class codes (default)
Sub-Class Prog I/F Description
00h 00h All devices other than VGA
01h 00h VGA-compatible device
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Sub-Class Prog I/F Description
00h 00h RAM memory controller
01h 00h Flash memory controller
80h 00h Other memory controller
Sub-Class Prog I/F Description
00h 00h SCSI controller
01h xxh IDE controller
02h 00h Floppy disk controller
03h 00h IPI controller
04h 00h RAID controller
80h 00h Other mass storage controller
Sub-Class Prog I/F Description
00h 00h Ethernet controller
01h 00h Token ring controller
02h 00h FDDI controller
03h 00h ATM controller
80h 00h Other network controller
Sub-Class Prog I/F Description
00h 00h VGA-compatible controller
00h 01h 8514 compatible controller
01h 00h XGA controller
80h 00h Other display controller
Sub-Class Prog I/F Description
00h 00h Video device
01h 00h Audio device
80h 00h Other multimedia device
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Sub-Class Prog I/F Description
00h 00h Host/PCI bridge
01h 00h PCI/ISA bridge
02h 00h PCI/EISA bridge
03h 00h PCI/Micro Channel bridge
04h 00h PCI/PCI bridge
05h 00h PCI/PCMCIA bridge
06h 00h NuBus bridge
07h 00h CardBus bridge
80h 00h Other bridge type
Sub-Class Prog I/F Description
00h 00h Generic XT compatible serial controller
01h 16450 compatible serial controller
02h 16550 compatible serial controller
01h 00h Parallel port
01h Bidirectional parallel port
02h ECP 1.X compliant parallel port
80h 00h Other communications device
Sub-Class Prog I/F Description
00h 00h Generic 8259 PIC
01h ISA PIC
02h EISA PIC
01h 00h Generic 8237 DMA controller
01h ISA DMA controller
02h EISA DMA controller
02h 00h Generic 8254 system timer
01h ISA system timer
02h EISA system timers (2 timers)
03h 00h Generic RTC controller
01h ISA RTC controller
80h 00h Other system peripheral
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Sub-Class Prog I/F Description
00h 00h Keyboard controller
01h 00h Digitizer (Pen)
02h 00h Mouse controller
80h 00h Other input controller
Sub-Class Prog I/F Description
00h 00h Generic docking station
80h 00h Other type of docking station
Sub-Class Prog I/F Description
00h 00h Intel386™
01h 00h Intel486™
02h 00h Pentium™
10h 00h Alpha™
40h 00h Co-processor
Sub-Class Prog I/F Description
00 00h FireWire™ (IEEE 1394)
01h 00h ACCESS.bus
02h 00h SSA
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CACHE LINE SIZE REGISTER (CALN)Register Name: Cache Line SizeAddress Offset: 0ChPower-up value: 00h, hardwiredBoot-load: not usedAttribute: Read OnlySize: 8 bits
This register is hardwired to 0. The cache line con-figuration register is used by the system to define thecache line size in doubleword (64-bit) increments.This controller does not use the “Memory Write andInvalidate” PCI bus cycle commands when operatingin the bus master mode, and therefore does not inter-nally require this register. When operating in the tar-get mode, this controller does not have theconnections necessary to “snoop” the PCI bus andaccordingly cannot employ this register in the detec-tion of burst transfers that cross a line boundary.
The latency timer register has meaning only whenthis controller is used as a bus master and pertains tothe number of PCI bus clocks that this master will beguaranteed. The nonzero value for this register isinternally decremented after this device has beengranted the bus and has begun to assert FRAME#.Prior to this latency timer count reaching zero, thisdevice can ignore the removal of the bus grant andmay continue the use of the bus for data transfers.
This register consists of two fields: Bits 6:0 define theformat for bytes 10h through 3Fh of the device con-figuration header, and bit 7 establishes whether thisdevice represents a single function (bit 7 = 0) or amultifunction (bit 7 = 1) PCI bus agent. The S5933 isa single function PCI device.
7 0
Single/Multi-function device (Read Only)0 = single function1 = multi-function
The Built-In Self-Test (BIST) register permits theimplementation of custom, user-specific diagnostics.This register has four fields as depicted in Figure 10.Bit 7, when set signifies that this device supports abuilt-in self test. When bit 7 is set, writing a 1 to bit 6will commence the self test. In actuality, writing a 1 tobit 6 produces an interrupt to the Add-On interface.Bit 6 will remain set until cleared by a write operationto this register from the Add-On bus interface. Whenbit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value forthe completion code (bits 3:0).
Bit Description
7 BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one isreturned. A zero should be returned if this self test feature is not desired. This field is read onlyfrom the PCI interface.
6 Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only bewritten when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Otherthan through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On businterface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within2 seconds after being set, or the device will be failed.
5:4 Reserved. These bits are reserved. This field will always return zeros.
3:0 Completion Code. This field provides a method for detailing a device-specific error. It is consideredvalid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion codeindicates successful completion.
7 0
X
1
X
2
X
3
X
4
0
5
0
6
0X
Bit
Value
User definedCompletion Code (RO)
Reserved (RO)
Start BIST (WO)
BIST Capable (RO)
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BASE ADDRESS REGISTERS (BADR)Register Name: Base AddressAddress Offset: 10h, 14h, 18h, 1Ch, 20h, 24hPower-up value: FFFFFFC1h for offset 10h;
00000000h for all othersBoot-load: External nvRAM offset
050h, 54h, 58h, 5Ch, 60h(BADR0-4)
Attribute: high bits Read/Write; low bitsRead Only
Size: 32 bits
The base address registers provide a mechanism forassigning memory or I/O space for the Add-On func-tion. The actual location(s) the Add-On function is torespond to is determined by first interrogating theseregisters to ascertain the size or space desired, andthen writing the high-order field of each register toplace it physically in the system’s address space. Bitzero of each field is used to select whether the spacerequired is to be decoded as memory (bit 0 = 0) or I/O(bit 0 = 1). Since this PCI controller has 16 DWORDsof internal operating registers, the Base AddressRegister at offset 10h is assigned to them. The re-maining five base address registers can only be usedby boot-loading them from the external nvRAM inter-face. BADR5 register is not implemented and will re-turn all 0’s.
Determining Base Address SizeThe address space defined by a given base addressregister is determined by writing all 1s to a givenbase address register from the PCI bus and thenreading that register back. The number of 0s returnedstarting from D4 for memory space and D2 for I/Ospace toward the high-order bits reveals the amountof address space desired. Tables 23 and 24 list thepossible returned values and their corresponding sizefor both memory and I/O, respectively. Included inthe table are the nvRAM/EPROM boot values whichcorrespond to a given assigned size. A register re-turning all zeros is disabled.
Assigning the Base Address
After a base address has been sized as described inthe preceding paragraph, the region associated withthat base address register (the high order one bits)can physically locate it in memory (or I/O) space. Forexample, the first base address register returnsFFFFFFC1h indicating an I/O space (D0=1) and isthen written with the value 00000300h. This meansthat the controller’s internal registers can be selectedfor I/O addresses between 00000300h through0000033Fh, in this example. The base address valuemust be on a natural binary boundary for the requiredsize (example 300h, 340h, 380h etc.; 338h would notbe allowable).
31:4 Base Address Location. These bits are used to position the decoded region in memory space. Onlybits which return a 1 after being written as 1 are usable for this purpose. Except for Base AddressRegister 0, these bits are individually enabled by the contents sourced from the external boot memory.
3 Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachableregions can only be located within the region altered through PCI bus memory writes. This bit, whenset, also implies that all read operations will return the data associated for all bytes regardless of theByte Enables. Memory space which cannot support this behavior should leave this bit in the zerostate. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by theexternal boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is readonly from the PCI interface.
2:1 Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the spacelocation is restricted to be within the first megabyte of memory space. The table below describes theencoding:
Bits Description2 10 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space.
0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space.
1 0 Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.(Not supported by this controller.)
1 1 Reserved. (Not supported by this controller.)
1 The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The onlymeaningful option is whether it is desired to position memory space anywhere within 32-bit memoryspace or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the resetpin and later initialized by the external boot memory (if present).
0 Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space andthe remaining bits in the base address register are defined as shown in Table 22a.
Bit Description
Bit Description
31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bitswhich return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,these bits are individually enabled by the contents sourced from the external boot memory (EPROMor nvRAM).
1 Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for theentire register location, bits 31 through 0).
0 Space Indicator = 1. When one this bit identifies a base address region as an I/O space and theremaining bits in the base address register have the definition as shown in Table 11b.
1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.3. BADR5 register is not implemented and will return all 0’s.
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Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or
BIOS missing 3
FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFFDh
FFFFFFF9h 8 bytes (2 DWORDs) FFFFFFF9h
FFFFFFF1h 16 bytes (4 DWORDs) FFFFFFF1h
FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFE1h
FFFFFFC1h 64 bytes (16 DWORDs) FFFFFFC1h 4
FFFFFF81h 128 bytes (32 DWORDs) FFFFFF81h
FFFFFF01h 256 bytes (64 DWORDs) FFFFFF01h
4. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external bootmemory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h orFFFFFFC2h).
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EXPANSION ROM BASE ADDRESSREGISTER (XROM)
Register Name: Expansion ROM Base AddressAddress Offset: 30hPower-up value: 00000000hBoot-load: External nvRAM offset
The expansion base address ROM register providesa mechanism for assigning a space within physicalmemory for an expansion ROM. Access from the PCIbus to the memory space defined by this register willcause one or more accesses to the S5933 control-lers’ external BIOS ROM (or nvRAM) interface. SincePCI bus accesses to the ROM may be 32 bits wide,repeated operations to the ROM are generated bythe S5933 and the wider data is assembled internalto the S5933 controller and then transferred to thePCI bus by the S5933.
Bit Description
31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region inmemory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Thesebits are individually enabled by the contents sourced from the external boot memory (EPROM ornvRAM). The desired size for the ROM memory is determined by writing all ones to this register andthen reading back the contents. The number of bits returned as zeros, in order from least significantto most significant bit, indicates the size of the expansion ROM. This controller limits the expansionROM area to 64K bytes. The allowable returned values after all ones are written to this register areshown in Table 26.
10:1 Reserved. All zeros.
0 Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit.When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is requiredthat the PCI command register also have the memory decode enabled for this bit to have an effect.
Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or
This register indicates the interrupt routing for theS5933 controller. The ultimate value for this registeris system-architecture specific. For x86 based PCs,the values in this register correspond with the estab-lished interrupt numbers associated with the dual8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspondwith the IRQ numbers 0 through 15, and the valuesfrom 16 to 254 are reserved. The value of 255 (thecontroller’s default power-up value) signifies either“unknown” or “no connection” for the system inter-rupt. This register is boot-loaded from the externalboot memory, if present, and may be written by thePCI interface.
This register identifies which PCI interrupt, if any, isconnected to the controller’s PCI interrupt pins. Theallowable values are 0 (no interrupts), 1 (INTA#), 2(INTB#), 3 (INTC#), and 4 (INTD#). The defaultpower-up value assumes INTA#.
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MINIMUM GRANT REGISTER (MINGNT)Register Name: Minimum Grant
This register may be optionally used by bus mastersto specify how long a burst period the device needs.A value of zero indicates that the bus master has nostringent requirement. The units defined by the leastsignificant bit are in 250-ns increments. This registeris treated as “information only” and has no furtherimplementation within this device.
Values other than zero are possible when an externalboot memory is used.
This register may be optionally used by bus mastersto specify how often this device needs PCI bus ac-cess. A value of zero indicates that the bus masterhas no stringent requirement. The units defined bythe least significant bit are in 250-ns increments. Thisregister is treated as “information only” and has nofurther implementation within this device.
Values other than zero are possible when an externalboot memory is used.
7 0
Value x 250ns (RO)00-no requirement01-FFh
123456
0
bit
value0 0 0 0 0 0 0
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PCI BUS OPERATION REGISTERS
Address Offset Abbreviation Register Name
00h OMB1 Outgoing Mailbox Register 1
04h OMB2 Outgoing Mailbox Register 2
08h OMB3 Outgoing Mailbox Register 3
0Ch OMB4 Outgoing Mailbox Register 4
10h IMB1 Incoming Mailbox Register 1
14h IMB2 Incoming Mailbox Register 2
18h IMB3 Incoming Mailbox Register 3
1Ch IMB4 Incoming Mailbox Register 4
20h FIFO FIFO Register port (bidirectional)
24h MWAR Master Write Address Register
28h MWTC Master Write Transfer Count Register
2Ch MRAR Master Read Address Register
30h MRTC Master Read Transfer Count Register
34h MBEF Mailbox Empty/Full Status
38h INTCSR Interrupt Control/Status Register
3Ch MCSR Bus Master Control/Status Register
PCI BUS OPERATION REGISTERSThe PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can beeither exchanged through the mailboxes, transferred through the FIFO in blocks under program control, ortransferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.
These four DWORD registers provide a method forsending command or parameter data to the Add-Onsystem. PCI bus operations to these registers maybe in any width (byte, word, or DWORD). Writing tothese registers can be a source for Add-On bus inter-rupts (if desired) by enabling their interrupt genera-tion through the use of the Add-On’s interrupt control/status register.
These four DWORD registers provide a method forreceiving user defined data from the Add-On system.PCI bus read operations to these registers may be inany width (byte, word, or DWORD). Only read opera-tions are supported. Reading from these registers canoptionally cause an Add-On bus interrupt (if desired)by enabling their interrupt generation through the useof the Add-On’s interrupt control/status register.
Mailbox 4, byte 3 only exists as device pins on theS5933 devices when used with a serial nonvolatilememory.
This location provides access to the bidirectionalFIFO. Separate registers are used when readingfrom or writing to the FIFO. Accordingly, it is not pos-sible to read what was written to this location. TheFIFO registers are implicitly involved in all bus masteroperations and, as such, should not be accessedduring active bus master transfers. When operatingupon the FIFOs with software program transfers in-volving word or byte operations, the sequenceof the FIFO should be established as described un-der FIFO Endian Conversion Management in order topreserve the internal FIFO data ordering and flagmanagement. The FIFO’s fullness may be observedby reading the master control- status registerorMCSR register.
This register is used to establish the PCI address fordata moving from the Add-On bus to the PCI busduring PCI bus memory write operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MWTC, and must begin on a DWORD boundary.This DWORD boundary starting constraint is placedupon this controller’s PCI bus master transfers sothat byte lane alignment can be maintained betweenthe S5933 controller’s internal FIFO data path, theAdd-On interface, and the PCI bus.
Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.
After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.
The Master Write Address Register is continually up-dated during the transfer process and will always bepointing to the next unwritten location. Reading ofthis register during a transfer process (done when theS5933 controller is functioning as a target, i.e. not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master write transfers, the two leastsignificant bits presented on the PCI bus pinsAD[31:0] will always be zero. This identifies to thetarget memory that the burst address sequence willbe in a linear order rather than in an Intel 486 orPentium™ cache line fill sequence. Also, the PCI busaddress bit A1 will always be zero when this control-ler is the bus master. This signifies to the target thatthe S5933 controller is burst capable and that thetarget should not arbitrarily disconnect after the firstdata phase of this operation.
Under certain circumstances, MWAR can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.
The master write transfer count register is used toconvey to the S5933 controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIwrite operation until the transfer count reaches zero.
Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.
Under certain circumstances, MWTC can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.
This register is used to establish the PCI address fordata moving to the Add-On bus from the PCI busduring PCI bus memory read operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MRTC (Section 5.7) and must begin on a DWORDboundary. This DWORD boundary starting constraintis placed upon this controller’s PCI bus master trans-fers so that byte lane alignment can be maintainedbetween the S5933 controller’s internal FIFO datapath, the Add-On interface and the PCI bus.
Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.
After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.
The Master Read Address Register is continually up-dated during the transfer process and will always bepointing to the next unread location. Reading of thisregister during a transfer process (done when theS5933 controller is functioning as a target—i.e., not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master read transfers, the two leastsignificant bits presented on the PCI bus AD[31:0]will always be zero. This identifies to the targetmemory that the burst address sequence will be in alinear order rather than in an Intel 486 or Pentium™cache line fill sequence. Also, the PCI bus addressbit A1 will always be zero when this controller is thebus master. This signifies to the target that the con-troller is burst capable and that the target should notarbitrarily disconnect after the first data phase of thisoperation.
Under certain circumstances, MRAR can be ac-cessed from the Add-On bus instead of the PCI bus.
31 0
0
1
0
2 Bit
Value
DWORD Address (RO)
Read Transfer Address (R/W)
CPCI 1264
62
PCI CONTROLLED BUS MASTER READTRANSFER COUNT REGISTER (MRTC)
The master read transfer count register is used toconvey to the PCI controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIread operation until the transfer count reaches zero.Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.
Under certain circumstances, MRTC can be ac-cessed from the Add-On bus instead of the PCI bus.
31 025 Bit
Value
Transfer Count in Bytes (R/W)Reserved = 0's (RO)
26
00
CPCI 1264
63
MAILBOX EMPTY FULL/STATUSREGISTER (MBEF)
Register Name: Mailbox Empty/Full Status
PCI Address Offset: 34h
Power-up value: 00000000h
Attribute: Read Only
Size: 32 bits
This register provides empty/full visibility of each bytewithin the mailboxes. The empty/full status for theOutgoing mailboxes is displayed on the low-order 16bits and the empty/full status for the Incoming mail-boxes is presented on the high-order 16 bits. A valueof 1 signifies that a given mailbox has been written byone bus interface but has not yet been read by thecorresponding destination interface. A PCI bus in-coming mailbox is defined as one in which data trav-els from the Add-On bus into the PCI bus, and anoutgoing mailbox is defined as one where data trav-els out from the PCI bus to the Add-On interface.
31 015 Bit
Value
Outgoing MailboxStatus (RO)Incoming Mailbox Status (RO)
16
CPCI 1264
64
Bit Description
31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been writtenby the Add-On interface but have not yet been read by the PCI bus. Each bit location corre-sponds to a specific byte within one of the four incoming mailboxes. A value of one for each bitsignifies that the specified mailbox byte is full, and a value of zero signifies empty. The mappingof these status bits to bytes within each mailbox is as follows:
15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been writtenby the PCI bus interface but have not yet been read by the Add-On bus. Each bit location correspondsto a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies thatthe specified mailbox byte is full, and a value of zero signifies empty. The mapping of these statusbits to bytes within each mailbox is as follows:
Register Name: Interrupt Control and StatusPCI Address Offset: 38hPower-up value: 00000000hAttribute: Read/Write (R/W),
Read/Write_One_Clear (R/WC)Size: 32 bits
This register provides the method for choosing whichconditions are to produce an interrupt on the PCI businterface, a method for viewing the cause of the inter-rupt, and a method for acknowledging (removing) theinterrupt’s assertion.
Interrupt sources:
• Write Transfer Terminal Count = zero
• Read Transfer Terminal Count = zero
• One of the Outgoing mailboxes (1,2,3 or 4)becomes empty
• One of the Incoming mailboxes (1,2,3 or 4)becomes full.
23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interruptconditions is present. This bit is nothing more than the ORing of the interrupt conditions describedby bits 19 through 16 of this register.
22 Reserved. Always zero.
21 Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operatesas read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a writeto this bit with the data of “zero” will not change the state of this bit.
20 Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI buscycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will causethis bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.
19 Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. Thisinterrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.
18 Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. Thisinterrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.
17 Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of thisregister are written by the Add-On interface. This bit operates as read or write one clear. A write tothis bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”will not change the state of this bit.
16 Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this registeris read by the Add-On interface. This bit operates as read or write one clear. A write to this bit withthe data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not changethe state of this bit.
15 Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the readtransfer count reaches zero. This bit is read/write.
14 Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the writetransfer count reaches zero. This bit is read/write.
13 Reserved. Always zero.
12 Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identifiedby bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.
11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to bethe source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.
CPCI 1264
68
9:8 Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]bselects byte 2, and [11]b selects byte 3. This field is read/write.
7:5 Reserved, Always zero.
4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailboxregister identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.
3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be thesource for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2,[10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.
1:0 Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selectsbyte 2, and [11]b selects byte 3. This field is read/write.
This register provides for overall control of this de-vice. It is used to enable bus mastering for both datadirections as well as providing a method to performsoftware resets.
The following PCI bus controls are available:
• Write Priority over Read
• Read Priority over Write
• Write Transfer Enable
• Write master requests on 4 or more FIFO wordsavailable (full)
• Read transfer enable
• Read master requests on 4 or more FIFOavailable (empty)
• Assert reset to Add-On
• Reset Add-On to PCI FIFO flags
• Reset PCI to Add-On FIFO flags
• Reset mailbox empty full status flags
• Write external non-volatile memory
The following PCI interface status flags are provided:
• PCI to Add-On FIFO FULL
• PCI to Add-On FIFO has four or more emptylocations
• PCI to Add-On FIFO EMPTY
• Add-On to PCI FIFO FULL
• Add-On to PCI FIFO has four or more wordsloaded
• Add-On to PCI FIFO EMPTY
• PCI to Add-On Transfer Count = Zero
• Add-On to PCI Transfer Count = Zero
31 29 27 24 23 014 12 10 8 7 6 515 Bit
Value
FIFO STATUS (RO)D5=Add-on to PCI FIFO EmptyD4=Add-on to PCI FIFO 4+ WordsD3=Add-on to PCI FIFO FullD2=PCI to Add-on FIFO EmptyD1=PCI to Add-on FIFO 4+SpacesD0=PCI to Add-on FIFO Full
D7=Add-on to PCI Transfer Countequals zero (R0)
D6=PCI to Add-on Transfer Countequals zero (R0)
160
Write Transfer Control (R/W)(PCI memory writes)
D10=Write Transfer EnableD9=FIFO Management SchemeD8=Write vs Read Priority
Reset Controls (R/WC)D27=Mailbox Flags ResetD26=Add-on to PCI FIFO Status Flags ResetD25=PCI to Add-on FIFO Status Flags ResetD24=Add-On Reset nv operation address/data
Memory Read MultipleEnable = 1Disable = 0
Read Transfer Control (R/W) (PCI memory reads)
D14=Read Transfer EnableD13=FIFO Management SchemeD12=Read vs. Write Priority
nvRAM Access Ctrl
0 0
Control Status
CPCI 1264
70
Bit Description
31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatilememory. Write operations are achieved by a sequence of byte operations involving these bits and the8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address,and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready forthe access to the external memory. D31 must be written to a 1 before an access can begin, andsubsequent accesses must wait for bit D31 to become zero (ready).
D31 D30 D29 W/R
0 X X W Inactive
1 0 0 W Load low address byte
1 0 1 W Load high address byte
1 1 0 W Begin write
1 1 1 W Begin read
0 X X R Ready
1 X X R Busy
Cautionary note: The nonvolatile memory interface is also available for access by the Add-Oninterface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supportedby the S5933 device. Software must be designed to prevent the simultaneous access of nvmemory to prevent data corruption within the memory and provide for accurate data retrieval.
28 FIFO loop back mode.
27 Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY).It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Sincereading of this bit will always produce zeros, this bit is write only.
26 Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus mastermemory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFOFour Plus word flag to reset. It is not necessary to write this bit as zero because it is used internallyto produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only.
25 PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Busmaster memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to resetand the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zerobecause it is used internally to produce a reset pulse. Since reading of this bit will always producezeros, this bit is write only.
24 Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing azero to this pin is necessary to remove the assertion of reset. This register bit is read/write.
23:16 Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and29 of this register to access the external non-volatile memory. The contents written are either lowaddress, high address, or data as defined by bits 30 and 29. This register will contain the externalnon-volatile memory data when the proper read sequence for bits 31 through 29 is performed.
CPCI 1264
71
Bit Description
15 Enable memory read multiple during S5933 bus mastering mode.
14 Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers totake place. Writing a zero to this location will suspend an active transfer. An active transfer is onein which the transfer count is not zero.
13 Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevacant FIFO word.
12 Read versus Write priority. This bit controls the priority of read transfers over write transfers.When set to a 1 with bit D8 as zero this indicates that read transfers always have priority overwrite transfers; when set to a one with D8 as one, this indicates that transfer priorities willalternate equally between read and writes.
11 Reserved. Always zero.
10 Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to takeplace. Writing a zero to this location will suspend an active transfer. An active transfer is one inwhich the transfer count is not zero.
9 Write FIFO management scheme. When set to a one this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevalid FIFO word.
8 Write versus Read priority. This bit controls the priority of write transfers over read transfers.When set to a one with bit D12 as zero this indicates that write transfers always have priority overread transfers; when set to a one with D12 as one, this indicates that transfer priorities willalternate equally between writes and reads.
7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfercount is all zeros.
6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfercount is all zeros.
5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completelyempty.
4 Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid withinthe Add-On to PCI bus FIFO.
3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.
2 PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completelyempty.
1 PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words withinthe PCI to Add-On FIFO.
0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.
