CPE 631Lecture 10: Instruction Level Parallelism and Its...

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•Aleksandar Milenkovich •1

CPE 631 Lecture 10: Instruction Level Parallelism andIts Dynamic Exploitation

Aleksandar Milenkovic, [email protected] and Computer EngineeringUniversity of Alabama in Huntsville

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Outline

n Instruction Level Parallelism (ILP)n Recap: Data Dependenciesn Extended MIPS Pipeline and Hazardsn Dynamic scheduling with a scoreboard

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ILP: Concepts and Challenges

n ILP (Instruction Level Parallelism) –overlap execution of unrelated instructions

n Techniques that increase amount of parallelism exploited among instructions– reduce impact of data and control hazards– increase processor ability to exploit parallelism

n Pipeline CPI = Ideal pipeline CPI + Structural stalls + RAW stalls + WAR stalls + WAW stalls + Control stalls– Reducing each of the terms of the right-hand side

minimize CPI and thus increase instruction throughput

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Two approaches to exploit parallelism

n Dynamic techniques– largely depend on hardware

to locate the parallelism

n Static techniques– relay on software

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Techniques to exploit parallelism

DH stallsBasic compiler pipeline scheduling (A.2, 4.1)

CH stallsLoop Unrolling (4.1)

WAR and WAW stallsDynamic scheduling with register renaming (3.2)

DH stalls (RAW)Basic dynamic scheduling (A.8)

Control hazard stallsDelayed branches (A.2)

Data hazard (DH) stallsForwarding and bypassing (Section A.2)

Ideal CPI, and D/CH stallsCompiler speculation (4.4)

Ideal CPI and DH stallsSoftware pipelining and trace scheduling (4.3)

Ideal CPI, DH stallsCompiler dependence analysis (4.4)

RAW stalls w. memoryDynamic memory disambiguation (3.2, 3.7)

Data and control stallsSpeculation (3.7)

Ideal CPIIssuing multiple instruction per cycle (3.6)

CH stallsDynamic branch prediction (3.4)

Reduces Technique (Section in the textbook)

Dynamically Scheduled Pipelines

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Overcoming Data Hazards with Dynamic Scheduling

n Why in HW at run time?– Works when can’t know real dependence

at compile time– Simpler compiler – Code for one machine runs well on another

n Example

n Key idea: Allow instructions behind stall to proceed

DIV.D F0,F2,F4ADD.D F10,F0,F8SUB.D F12,F8,F12

SUB.D cannot execute because the dependence of ADD.D on DIV.D causes the pipeline to stall; yet SUBD is not data dependent on anything!

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Overcoming Data Hazards with Dynamic Scheduling (cont’d)

n Enables out-of-order execution => out-of-order completion

n Out-of-order execution divides ID stage:– 1. Issue—decode instructions,

check for structural hazards– 2. Read operands—wait until no data hazards,

then read operandsn Scoreboarding –

technique for allowing instructions to execute out of order when there are sufficient resources and no data dependencies (CDC 6600, 1963)

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Scoreboarding Implications

n Out-of-order completion => WAR, WAW hazards?

n Solutions for WAR– Queue both the operation and copies of its operands– Read registers only during Read Operands stage

n For WAW, must detect hazard: stall until other completes

n Need to have multiple instructions in execution phase => multiple execution units or pipelined execution units

n Scoreboard keeps track of dependencies, state or operations

n Scoreboard replaces ID, EX, WB with 4 stages



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Four Stages of Scoreboard Control

n ID1: Issue — decode instructions & check for structural hazards

n ID2: Read operands — wait until no data hazards, then read operands

n EX: Execute — operate on operands; when the result is ready, it notifies the scoreboard that it hascompleted execution

n WB: Write results — finish execution; the scoreboard checks for WAR hazards. If none, it writes results. If WAR, then it stalls the instruction


Scoreboarding stalls the the SUBD in its write result stage until ADDD reads its operands

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n 1. Issue—decode instructions & check for structural hazards (ID1)– If a functional unit for the instruction is free and no other active

instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared.

n 2. Read operands—wait until no data hazards, then read operands (ID2)– A source operand is available if no earlier issued active instruction is

going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order.

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n 3. Execution—operate on operands (EX)– The functional unit begins execution upon receiving operands. When

the result is ready, it notifies the scoreboard that it has completed execution.

n 4. Write result—finish execution (WB)– Once the scoreboard is aware that the functional unit has completed

execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, then it stalls the instruction.

– Example:

– CDC 6600 scoreboard would stall SUBD until ADD.D reads operands


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Three Parts of the Scoreboard

n 1. Instruction status—which of 4 steps the instruction is in (Capacity = window size)

n 2. Functional unit status—Indicates the state of the functional unit (FU). 9 fields for each functional unit– Busy—Indicates whether the unit is busy or not

– Op—Operation to perform in the unit (e.g., + or –)– Fi—Destination register– Fj, Fk—Source-register numbers– Qj, Qk—Functional units producing source registers Fj, Fk– Rj, Rk—Flags indicating when Fj, Fk are ready

n 3. Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register

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MIPS with a Scoreboard

Add1Add2Add3

FP Mult

Registers

Control/StatusScoreboard

FP Mult

FP Div

FP Div

FP Div

Control/Status

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Detailed Scoreboard Pipeline Control

Read operands

Execution complete

Instruction status

Write result

Issue

Bookkeeping

Rj← No; Rk← No

∀f(if Qj(f)=FU then Rj(f)← Yes);∀f(if Qk(f)=FU then Rj(f)← Yes);

Result(Fi(FU))← 0; Busy(FU)← No

Busy(FU)← yes; Op(FU)← op; Fi(FU)← ’D’; Fj(FU)← ’S1’;

Fk(FU)← ’S2’; Qj← Result(’S1’); Qk← Result(’S2’); Rj← not Qj; Rk← not Qk; Result(’D’)← FU;

Rj and Rk

Functional unit done

Wait until

∀f((Fj( f )?Fi(FU) or Rj( f )=No) &

(Fk( f ) ?Fi(FU) or Rk( f )=No))

Not busy (FU) and not result (D)

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Scoreboard Example

Instruction status Read ExecutionWriteInstruction j k Issue operandscomplete ResultL.D F6 34+ R2L.D F2 45+ R3MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 NoMult2 NoAdd NoDivide No

Register result statusClock F0 F2 F4 F6 F8 F10 F12 ... F30

FU

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Scoreboard Example: Cycle 1

Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1L.D F2 45+ R3MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 YesMult1 NoMult2 NoAdd NoDivide No


1 FU Integer

Issue 1st L.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2L.D F2 45+ R3MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



2 FU Integer

Issue 2nd L.D? Structural hazard!No further instructions will issue!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3L.D F2 45+ R3MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



3 FU Integer

Issue MUL.D?

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



4 FU Integer

Check for WAR hazards!If none, write result!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5MUL.D F0 F2 F4SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



5 FU Integer

Issue 2nd L.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6MUL.D F0 F2 F4 6SUB.D F8 F6 F2DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Integer No YesMult2 NoAdd NoDivide No


6 FU Mult1 Integer

Issue MUL.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7MUL.D F0 F2 F4 6SUB.D F8 F6 F2 7DIV.D F10 F0 F6ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Integer No YesMult2 NoAdd Yes Sub F8 F6 F2 Integer Yes NoDivide No


7 FU Mult1 Integer Add

Issue SUB.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6SUB.D F8 F6 F2 7DIV.D F10 F0 F6 8ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Integer No YesMult2 NoAdd Yes Sub F8 F6 F2 Integer Yes NoDivide Yes Div F10 F0 F6 Mult1 No Yes


8 FU Mult1 Integer Add Divide

Issue DIV.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9DIV.D F10 F0 F6 8ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger No

10 Mult1 Yes Mult F0 F2 F4 Integer Yes YesMult2 No

2 Add Yes Sub F8 F6 F2 Integer Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes


9 FU Mult1 Add Divide

Read operands for MUL.D and SUB.D!Assume we can feed Mult1 and Add units in the same clock cycle.Issue ADD.D? Structural Hazard (unit is busy)!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11DIV.D F10 F0 F6 8ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



0 Add Yes Sub F8 F6 F2 Integer Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes



Last cycle of SUB.D execution.

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2Functional unit status dest S1 S2 FU for jFU for kFj? Fk?


7 Mult1 Yes Mult F0 F2 F4 Integer Yes YesMult2 NoAdd Yes Sub F8 F6 F2 Integer Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes



Check WAR on F8. Write F8.

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13Functional unit status dest S1 S2 FU for jFU for kFj? Fk?


6 Mult1 Yes Mult F0 F2 F4 Integer Yes YesMult2 NoAdd Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes



Issue ADD.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14Functional unit status dest S1 S2 FU for jFU for kFj? Fk?



2 Add Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes



Read operands for ADD.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14Functional unit status dest S1 S2 FU for jFU for kFj? Fk?






Read operands for ADD.D!

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14 16Functional unit status dest S1 S2 FU for jFU for kFj? Fk?






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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14 16Functional unit status dest S1 S2 FU for jFU for kFj? Fk?





Why cannot write F6?

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14 16Functional unit status dest S1 S2 FU for jFU for kFj? Fk?





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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19 20SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8ADD.D F6 F8 F2 13 14 16Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Integer Yes YesMult2 NoAdd Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes



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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19 20SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8 21ADD.D F6 F8 F2 13 14 16Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 NoMult2 NoAdd Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 Yes Yes


21 FU Add Divide

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19 20SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8 21ADD.D F6 F8 F2 13 14 16 22Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 NoMult2 NoAdd Yes Add F6 F8 F2 Yes Yes

40 Divide Yes Div F10 F0 F6 Mult1 Yes YesRegister result statusClock F0 F2 F4 F6 F8 F10 F12 ... F30

22 FU Add Divide

Write F6?

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19 20SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8 21 61ADD.D F6 F8 F2 13 14 16 22Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 NoMult2 NoAdd No

0 Divide Yes Div F10 F0 F6 Mult1 Yes YesRegister result statusClock F0 F2 F4 F6 F8 F10 F12 ... F30

61 FU Divide

Write F6?

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Instruction status Read ExecutionWriteInstruction j k Issue operandscompleteResultL.D F6 34+ R2 1 2 3 4L.D F2 45+ R3 5 6 7 8MUL.D F0 F2 F4 6 9 19 20SUB.D F8 F6 F2 7 9 11 12DIV.D F10 F0 F6 8 21 61 62ADD.D F6 F8 F2 13 14 16 22Functional unit status dest S1 S2 FU for jFU for kFj? Fk?

Time Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 NoMult2 NoAdd NoDivide Yes Div F10 F0 F6 Mult1 Yes Yes


62 FU Divide

Write F6?

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Scoreboard Results

n For the CDC 6600– 70% improvement for Fortran– 150% improvement for hand coded assembly language– cost was similar to one of the functional units

• surprisingly low• bulk of cost was in the extra busses

n Still this was in ancient time– no caches & no main semiconductor memory– no software pipelining

– compilers?

n So, why is it coming back– performance via ILP

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Scoreboard Limitations

n Amount of parallelism among instructions– can we find independent instructions to execute

n Number of scoreboard entries– how far ahead the pipeline can look for

independent instructions (we assume a window does not extend beyond a branch)

n Number and types of functional units– avoid structural hazards

n Presence of antidependences and output dependences– WAR and WAW stalls become more important

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Tomasulo’s Algorithm

n Used in IBM 360/91 FPU (before caches)n Goal: high FP performance without special compilersn Conditions:

– Small number of floating point registers (4 in 360) prevented interesting compiler scheduling of operations

– Long memory accesses and long FP delays– This led Tomasulo to try to figure out how to get more

effective registers — renaming in hardware!

n Why Study 1966 Computer? n The descendants of this have flourished!

– Alpha 21264, HP 8000, MIPS 10000, Pentium III, PowerPC 604, …

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Tomasulo’s Algorithm (cont’d)

n Control & buffers distributed with Function Units (FU)– FU buffers called “reservation stations” =>

buffer the operands of instructions waiting to issue;

n Registers in instructions replaced by values or pointers to reservation stations (RS) => register renaming– avoids WAR, WAW hazards– More reservation stations than registers,

so can do optimizations compilers can’t

n Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs

n Load and Stores treated as FUs with RSs as welln Integer instructions can go past branches,

allowing FP ops beyond basic block in FP queue

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Tomasulo-based FPU for MIPS

FP addersFP adders

Add1Add2Add3

FP multipliersFP multipliers

Mult1Mult2

From Mem FP Registers

Reservation Stations

Common Data Bus (CDB)

To Mem

FP OpQueue

Load Buffers

Store Buffers

Load1Load2Load3Load4Load5Load6

From Instruction Unit

Store1Store2Store3

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Reservation Station Components

n Op: Operation to perform in the unit (e.g., + or –)n Vj, Vk: Value of Source operands

– Store buffers has V field, result to be stored

n Qj, Qk: Reservation stations producing source registers (value to be written)– Note: Qj/Qk=0 => source operand is already available in Vj

/Vk

– Store buffers only have Qi for RS producing result

n Busy: Indicates reservation station or FU is busy

Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.

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Three Stages of Tomasulo Algorithm

n 1. Issue—get instruction from FP Op Queue– If reservation station free (no structural hazard),

control issues instr & sends operands (renames registers)

n 2. Execute—operate on operands (EX)– When both operands ready then execute;

if not ready, watch Common Data Bus for result

n 3. Write result—finish execution (WB)– Write it on Common Data Bus to all awaiting units;

mark reservation station available

n Normal data bus: data + destination (“go to” bus)n Common data bus: data + source (“come from” bus)

– 64 bits of data + 4 bits of Functional Unit source address– Write if matches expected Functional Unit (produces result)– Does the broadcast

n Example speed: 2 clocks for Fl .pt. +,-; 10 for * ; 40 clks for /

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Tomasulo ExampleInstruction status: Exec Write

Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 Load1 NoLD F2 45+ R3 Load2 NoMULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Reservation Stations: S1 S2 RS RSTime Name Busy Op Vj Vk Qj Qk

Add1 NoAdd2 NoAdd3 NoMult1 NoMult2 No

Register result status:Clock F0 F2 F4 F6 F8 F10 F12 ... F30

0 FU

Clock cycle counter

FU countdown

Instruction stream

3 Load/Buffers

3 FP Adder R.S.2 FP Mult R.S.

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Tomasulo Example Cycle 1Instruction status: Exec Write

Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 Load1 Yes 34+R2LD F2 45+ R3 Load2 NoMULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2




1 FU Load1

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 Load1 Yes 34+R2LD F2 45+ R3 2 Load2 Yes 45+R3MULTD F0 F2 F4 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2




2 FU Load2 Load1

Note: Can have multiple loads outstanding

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 Load1 Yes 34+R2LD F2 45+ R3 2 Load2 Yes 45+R3MULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2


Add1 NoAdd2 NoAdd3 NoMult1 Yes MULTD R(F4) Load2Mult2 No


3 FU Mult1 Load2 Load1

• Note: registers names are removed (“renamed”) in Reservation Stations; MULT issued

• Load1 completing; what is waiting for Load1?

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 Load2 Yes 45+R3MULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6ADDD F6 F8 F2


Add1 Yes SUBD M(A1) Load2Add2 NoAdd3 NoMult1 Yes MULTD R(F4) Load2Mult2 No


4 FU Mult1 Load2 M(A1) Add1

• Load2 completing; what is waiting for Load2?

•2/16/2004


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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2


2 Add1 Yes SUBD M(A1) M(A2)Add2 NoAdd3 No

10 Mult1 Yes MULTD M(A2) R(F4)Mult2 Yes DIVD M(A1) Mult1


5 FU Mult1 M(A2) M(A1) Add1 Mult2

• Timer starts down for Add1, Mult1

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4DIVD F10 F0 F6 5ADDD F6 F8 F2 6


1 Add1 Yes SUBD M(A1) M(A2)Add2 Yes ADDD M(A2) Add1Add3 No



6 FU Mult1 M(A2) Add2 Add1 Mult2

• Issue ADDD here despite name dependency on F6?

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 7DIVD F10 F0 F6 5ADDD F6 F8 F2 6


0 Add1 Yes SUBD M(A1) M(A2)Add2 Yes ADDD M(A2) Add1Add3 No



7 FU Mult1 M(A2) Add2 Add1 Mult2

• Add1 (SUBD) completing; what is waiting for it?

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6


Add1 No2 Add2 Yes ADDD (M-M) M(A2)

Add3 No7 Mult1 Yes MULTD M(A2) R(F4)

Mult2 Yes DIVD M(A1) Mult1


8 FU Mult1 M(A2) Add2 (M-M) Mult2

•2/16/2004


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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6







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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6 10







• Add2 (ADDD) completing; what is waiting for it?

•2/16/2004


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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6 10 11


Add1 NoAdd2 NoAdd3 No



11 FU Mult1 M(A2) (M-M+M)(M-M) Mult2

• Write result of ADDD here?• All quick instructions complete in this cycle!

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 15 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6 10 11






• Mult1 (MULTD) completing; what is waiting for it?

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 15 16 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6 10 11


Add1 NoAdd2 NoAdd3 NoMult1 No

40 Mult2 Yes DIVD M*F4 M(A1)


16 FU M*F4 M(A2) (M-M+M)(M-M) Mult2

• Just waiting for Mult2 (DIVD) to complete

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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 15 16 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5ADDD F6 F8 F2 6 10 11






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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 15 16 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5 56ADDD F6 F8 F2 6 10 11






• Mult2 (DIVD) is completing; what is waiting for it?

•2/16/2004


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Instruction j k Issue Comp Result Busy AddressLD F6 34+ R2 1 3 4 Load1 NoLD F2 45+ R3 2 4 5 Load2 NoMULTD F0 F2 F4 3 15 16 Load3 NoSUBD F8 F6 F2 4 7 8DIVD F10 F0 F6 5 56 57ADDD F6 F8 F2 6 10 11


Add1 NoAdd2 NoAdd3 NoMult1 NoMult2 Yes DIVD M*F4 M(A1)


56 FU M*F4 M(A2) (M-M+M)(M-M) Result

• Once again: In-order issue, out-of-order execution and out-of-order completion.

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Tomasulo Drawbacks

n Complexity– delays of 360/91, MIPS 10000, Alpha 21264,

IBM PPC 620 in CA:AQA 2/e, but not in silicon!n Many associative stores (CDB) at high speedn Performance limited by Common Data Bus

– Each CDB must go to multiple functional units ⇒ high capacitance, high wiring density

– Number of functional units that can complete per cycle limited to one!

• Multiple CDBs ⇒ more FU logic for parallel assoc stores

n Non-precise interrupts!– We will address this later

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Tomasulo Loop Example

n This time assume Multiply takes 4 clocksn Assume 1st load takes 8 clocks

(L1 cache miss), 2nd load takes 1 clock (hit)n To be clear, will show clocks for SUBI, BNEZ

– Reality: integer instructions ahead of Fl. Pt. Instructions

n Show 2 iterations

Loop: LD F0 0(R1)MULTD F4 F0 F2SD F4 0 R1SUBI R1 R1 #8BNEZ R1 Loop

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Loop ExampleInstruction status: Exec Write

ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 Load1 No1 MULTD F4 F0 F2 Load2 No1 SD F4 0 R1 Load3 No2 LD F0 0 R1 Store1 No2 MULTD F4 F0 F2 Store2 No2 SD F4 0 R1 Store3 No

Reservation Stations: S1 S2 RS Time Name Busy Op Vj Vk Qj Qk Code:

Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1Mult1 No SUBI R1 R1 #8Mult2 No BNEZ R1 Loop

Register result statusClock R1 F0 F2 F4 F6 F8 F10 F12 ... F30

0 80 Fu

Added Store Buffers

Value of Register used for address, iteration control

Instruction Loop

Iter-ationCount

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Loop Example Cycle 1Instruction status: Exec Write

ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 80

Load2 NoLoad3 NoStore1 NoStore2 NoStore3 No


Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1Mult1 No SUBI R1 R1 #8Mult2 No BNEZ R1 Loop


1 80 Fu Load1

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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 No

Load3 NoStore1 NoStore2 NoStore3 No


Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8Mult2 No BNEZ R1 Loop


2 80 Fu Load1 Mult1

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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 No1 SD F4 0 R1 3 Load3 No

Store1 Yes 80 Mult1Store2 NoStore3 No




3 80 Fu Load1 Mult1

Implicit renaming sets up data flow graph

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4 80 Fu Load1 Mult1

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5 72 Fu Load1 Mult1

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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 Yes 721 SD F4 0 R1 3 Load3 No2 LD F0 0 R1 6 Store1 Yes 80 Mult1

Store2 NoStore3 No




6 72 Fu Load2 Mult1

•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 Yes 721 SD F4 0 R1 3 Load3 No2 LD F0 0 R1 6 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 No

Store3 No


Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1Mult1 Yes Multd R(F2) Load1 SUBI R1 R1 #8Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop


7 72 Fu Load2 Mult2

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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 Yes 721 SD F4 0 R1 3 Load3 No2 LD F0 0 R1 6 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No




8 72 Fu Load2 Mult2

•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 Load1 Yes 801 MULTD F4 F0 F2 2 Load2 Yes 721 SD F4 0 R1 3 Load3 No2 LD F0 0 R1 6 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No




9 72 Fu Load2 Mult2

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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 Load2 Yes 721 SD F4 0 R1 3 Load3 No2 LD F0 0 R1 6 10 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No


Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1

4 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #8Mult2 Yes Multd R(F2) Load2 BNEZ R1 Loop


10 64 Fu Load2 Mult2

•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 Load2 No1 SD F4 0 R1 3 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No



3 Mult1 Yes Multd M[80] R(F2) SUBI R1 R1 #84 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop



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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 Load2 No1 SD F4 0 R1 3 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 Mult12 MULTD F4 F0 F2 7 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No






•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R22 MULTD F4 F0 F2 7 15 Store2 Yes 72 Mult22 SD F4 0 R1 8 Store3 No


Add1 No LD F0 0 R1Add2 No MULTD F4 F0 F2Add3 No SD F4 0 R1Mult1 No SUBI R1 R1 #8

0 Mult2 Yes Multd M[72] R(F2) BNEZ R1 Loop



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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R22 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R22 SD F4 0 R1 8 Store3 No



4 Mult1 Yes Multd R(F2) Load3 SUBI R1 R1 #8Mult2 No BNEZ R1 Loop



•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R22 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R22 SD F4 0 R1 8 Store3 Yes 64 Mult1





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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 18 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 Yes 80 [80]*R22 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R22 SD F4 0 R1 8 Store3 Yes 64 Mult1





•2/16/2004


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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 No1 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 18 19 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 No2 MULTD F4 F0 F2 7 15 16 Store2 Yes 72 [72]*R22 SD F4 0 R1 8 19 Store3 Yes 64 Mult1





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ITER Instruction j k Issue CompResult Busy Addr Fu1 LD F0 0 R1 1 9 10 Load1 Yes 561 MULTD F4 F0 F2 2 14 15 Load2 No1 SD F4 0 R1 3 18 19 Load3 Yes 642 LD F0 0 R1 6 10 11 Store1 No2 MULTD F4 F0 F2 7 15 16 Store2 No2 SD F4 0 R1 8 19 20 Store3 Yes 64 Mult1





• Once again: In-order issue, out-of-order execution and out-of-order completion.

•2/16/2004


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Why can Tomasulo overlap iterations of loops?

n Register renaming– Multiple iterations use different physical

destinations for registers (dynamic loop unrolling)

n Reservation stations – Permit instruction issue to advance past integer

control flow operations– Also buffer old values of registers - totally avoiding

the WAR stall that we saw in the scoreboard

n Other perspective: Tomasulo building data flow dependency graph on the fly

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Tomasulo’s scheme offers 2 major advantages

n (1) the distribution of the hazard detection logic– distributed reservation stations and the CDB– If multiple instructions waiting on single result, &

each instruction has other operand, then instructions can be released simultaneously by broadcast on CDB

– If a centralized register file were used, the units would have to read their results from the registers when register buses are available.

n (2) the elimination of stalls for WAW and WAR hazards

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What about Precise Interrupts?

n Tomasulo had:In-order issue, out-of-order execution, and out-of-order completion

n Need to “fix” the out-of-order completion aspect so that we can find precise breakpoint in instruction stream

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Relationship between precise interrupts and speculation

n Speculation is a form of guessingn Important for branch prediction:

– Need to “take our best shot” at predicting branch direction

n If we speculate and are wrong, need to back up and restart execution to point at which we predicted incorrectly:– This is exactly same as precise exceptions!

n Technique for both precise interrupts/exceptions and speculation: in-order completion or commit

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HW support for precise interrupts

n Need HW buffer for results of uncommitted instructions: reorder buffer– 3 fields: instr, destination, value– Use reorder buffer number instead of reservation station

when execution completes– Supplies operands between

execution complete & commit– (Reorder buffer can be operand source

=> more registers like RS)– Instructions commit– Once instruction commits,

result is put into register– As a result, easy to undo

speculated instructions on mispredicted branches or exceptions

ReorderBuffer

FPOp

Queue

FP Adder FP Adder

Res Stations Res Stations

FP Regs

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Four Steps of Speculative TomasuloAlgorithm

n 1. Issue—get instruction from FP Op Queue– If reservation station and reorder buffer slot free, issue instr &

send operands & reorder buffer no. for destination (this stage sometimes called “dispatch”)

n 2. Execution—operate on operands (EX)– When both operands ready then execute; if not ready, watch

CDB for result; when both in reservation station, execute; checks RAW (sometimes called “issue”)

n 3. Write result—finish execution (WB)– Write on Common Data Bus to all awaiting FUs

& reorder buffer; mark reservation station available.

n 4. Commit—update register with reorder result– When instr. at head of reorder buffer & result present, update

register with result (or store to memory) and remove instr from reorder buffer. Mispredicted branch flushes reorder buffer (sometimes called “graduation”)

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What are the hardware complexities with reorder buffer (ROB)?

n How do you find the latest version of a register?– (As specified by Smith paper) need associative comparison network– Could use future file or just use the register result status buffer to track which

specific reorder buffer has received the value

n Need as many ports on ROB as register file

ReorderBuffer

FPOp

Queue

FP Adder FP Adder

Res Stations Res Stations

FP Regs

Compar network

Reorder Table

Des

t Re

g

Resu

lt

Exce

ptions

?

Valid

Prog

ram C

ount

er

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Summary

n Reservations stations: implicit register renaming to larger set of registers + buffering source operands– Prevents registers as bottleneck– Avoids WAR, WAW hazards of Scoreboard– Allows loop unrolling in HW

n Not limited to basic blocks (integer units gets ahead, beyond branches)

n Today, helps cache misses as well– Don’t stall for L1 Data cache miss (insufficient ILP for L2 miss?)

n Lasting Contributions– Dynamic scheduling– Register renaming– Load/store disambiguation

n 360/91 descendants are Pentium III; PowerPC 604; MIPS R10000; HP-PA 8000; Alpha 21264

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CPE 631Lecture 10: Instruction Level Parallelism and Its...

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