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CPE555A: Real-Time Embedded Systems. Lecture 5 Ali Zaringhalam Stevens Institute of Technology. Outline. Timer interrupt Process concept Scheduling Reference: Giorgio C. Buttazzo, Hard Real-Time Computing Systems, Predictable Scheduling Algorithms and Applications - PowerPoint PPT Presentation
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Fall 2015, arz 1 CPE555A: Real-Time Embedded Systems Lecture 5 Ali Zaringhalam Stevens Institute of Technology CS555A – Real-Time Embedded Systems Stevens Institute of Technology
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Page 1: CPE555A: Real-Time Embedded Systems

Fall 2015, arz 1

CPE555A:Real-Time Embedded Systems

Lecture 5Ali Zaringhalam

Stevens Institute of Technology

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Fall 2015, arz 22

Outline

Process concept Scheduling Reference: Giorgio C. Buttazzo,

Hard Real-Time Computing Systems, Predictable Scheduling Algorithms and Applications Available online in library

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

Page 3: CPE555A: Real-Time Embedded Systems

Fall 2015, arz 3

The Path Of I/O Transfer

In both programmed I/O & interrupt-driven I/O, the path for data transfer is through the processor registers

For high-performance systems and high-bandwidth I/O peripherals both techniques are inefficient

Alternative: Direct-Memory Access (DMA) removes the processor from the data transfer path

a limited form of multiprocessing (DMA is a specialized processor)

Common Memory & I/O bus

RegistesRegistes

Processor

ROM

RAM

I/OLOAD

STORE

Mem

ory

-map

ped

I/O

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 4

I/O Using DMA

CPU sends device name, address, length and transfer direction to DMA controller (via memory-mapped I/O)

CPU issues start command to DMA controller DMA controller provides handshake signals to I/O device &

memory including addresses DMA controller interrupts processor when transfer is complete

CPU

CPU

Memory

Memory

Interface

I/OPeripheral

I/OPeripheral

Interface

I/OPeripheral

I/OPeripheral

ROM

RAM

I/O DMAController

DMAController

DMA

Mem

ory

-map

ped

I/O Data

transferControl

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 55

Multiprogramming

Single-CPU computers don’t really run multiple programs simultaneously, it just looks that way

Each program runs to completion, but is interleaved with other programs

As a program runs, it may have to wait for user input or disk I/O

While one program waits, another can run

This is multiprogrammingCS555A – Real-Time Embedded Systems

Stevens Institute of Technology

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Fall 2015, arz 66

Process Concept

An operating system executes a variety of programs

In multi-programming, several programs share (multiplex) CPU resources

Process – a program in execution in CPU, with its own “framework” including program counter stack data section code heap allocated static memory

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 77

Processes in Memory

Process A Process B

Both processes may be running the same program (i.e., text). Example: two users opening a browser. Each process has its own resources such as stack, heap and CPU state.

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

Page 8: CPE555A: Real-Time Embedded Systems

CS555A – Real-Time Embedded SystemsStevens Institute of TechnologyFall 2015, arz 88

Process States As a process executes, it changes state

new: The process is newly created ready: The process is waiting to be scheduled in the CPU running: Program instructions are being executed waiting: The process is waiting for some event such as I/O

completion to occur terminated: The process has finished execution

Only a single process can be in the running state in a single-core CPU at any given time. But many processes can be in the other states.

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Process Control Block (PCB)

Information maintained by the operating system for each process in PCB:

Process state Program counter CPU registers CPU scheduling information (e.g.

process priority) Memory-management information

(base & bound registers) Accounting information (e.g., start

time, memory usage) I/O status information

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1010

Context Switch

The CPU multiplexes process execution by switching processes in and out

When the CPU switches to another process The operating system must save the state of the

old process Then load the saved state (i.e., context) of the

new process Context-switch time is overhead; the system

does no useful work while switching

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1111

CPU Switch From Process to Process

Overhead of contextswitching. Nothing useful is done.

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1212

Process Scheduling Queues

The operating system manages multi-program execution using a number of queues

Job queue – set of all processes in the system

Ready queue – set of all processes residing in main memory, ready and waiting to execute

Device queues – set of processes waiting for an I/O device

Processes migrate among the various queues during execution

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1313

Ready Queue And Various I/O Device Queues

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1414

Scheduling Concepts

Typically there are more processes than processors Scheduling is the issue of ordering the use of system

resources for concurrent programs in order to meet some well-defined objectives (e.g. meeting deadlines)

Scheduling decisions1. Allocation/assignment: which processor/core should

execute the task2. Ordering: the order of task execution (e.g., when there is

dependency)3. Timing/dispatching: when the task must execute

activation dispatchingexecution

preemption

termination

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Fall 2015, arz 1515

Scheduler Categories

Static schedulers make all three decisions at design time

May be implemented as part of the compiler May design to avoid critical section issues altogether

by scheduling thread execution Difficult to realize: execution time typically depends

on data input which may vary at run-time and cannot be anticipated at design time

Dynamic scheduler Performs all three decisions at run-time Scheduling unit is typically a thread or process

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Preemption

Dynamic schedulers typically support preemption Each task has an assigned priority When a higher-priority task is ready to run,

the current lower-priority running task is suspended and the higher-priority task is dispatched to the CPU

The higher-priority task could be A newly-arrived task Or an interrupt that must be handled

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling With No Preemption

Each task runs to completion before the next task is scheduled

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling With Preemption

A task can be executed in disjointed intervals assigned by the scheduler based on priority

Example: P(J3) > P(J2) > P(J1)

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Task Categories & Deadline

Hard: A real-time task is said to be hard if missing its deadline may have catastrophic consequences on the system under control.

Nuclear core shutdown Firm: A real-time task is said to be firm if missing

its deadline does not cause any damage to the system, but the output has no value.

A monitored event (e.g., snowstorm) is reported late Soft: A real-time task is said to be soft if missing

its deadline has still some utility for the system, although causing a performance degradation.

Switching from active to standby blade later than required

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Timing Definitions

Arrival time ai is the time at which a task becomes ready for execution; aka request time or release time ri

Computation time Ci is the worst-case time necessary for the processor to execute the task without interruption

Absolute Deadline di is the time before which a task should be completed to avoid damage to the system

Relative Deadline Di is the difference between the absolute deadline and the request time

Di = di − ri

/ri

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Timing Definitions - Continued

Start time si is the time at which a task starts its execution Finishing time fi is the time at which a task finishes its

execution Response time Ri is the difference between the finishing

time and the request time: Ri = fi − ri Lateness: Li = fi −di represents the delay of a task

completion with respect to its deadline; note that if a task completes before the deadline, its lateness is negative

Laxity or Slack time: Xi = di − ri − Ci is the maximum time a task can be delayed on its activation to complete by its deadline

/ri

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Example

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Example – Non-preemptive Response Time

R1=f1-a1=3-1=2 R2=f2-a2=5-2=3 R3=f3-a3=8-2=6

0 2 4 6 8 10 12 14 16

1

2

3

Time

Task

Lateness L1=f1-d1=3-6=-3 L2=f2-d2=5-5=0 L3=f3-d3=8-11=-3

Slack Time X1=d1− a1−C1=3 X2=d2- a2−C2=1 X3=d3− a3−C3=6

Deadline

Deadline

Deadline

Maximum Lateness = 0

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Example –preemptive Response Time

R1=f1-a1=5-1=3 R2=f2-a2=4-2=2 R3=f3-a3=8-2=6

0 2 4 6 8 10 12 14 16

1

2

3

Time

Task

Lateness L1=f1-d1=5-6=-1 L2=f2-d2=4-5=-1 L3=f3-d3=8-11=-3

Slack Time X1=d1− a1−C1=3 X2=d2- a2−C2=1 X3=d3− a3−C3=6

• Performs better than non-preemptive in terms of maximum lateness.• There can be many feasible schedules with different characteristics.

Deadline

Deadline

Deadline

Maximum Lateness = -1

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Fall 2015, arz 2525

Periodic & Aperiodic Tasks

Aperiodic: infinite sequence of identical activities With irregular activation

Periodic: infinite sequence of identical activities Activated regularly with period Ti

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Fall 2015, arz 2626

Precedence Constraints

The execution of some tasks may depend on the completion of other tasks

Precedence graph shows the dependency It must be acyclic

Beginning Task: has no predecessor.

Ending Task: has no successor.

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Fall 2015, arz 2727

Resource Constraints Multiple tasks

may depend on a single resource (e.g., file, device) for their execution

Read/write access must be synchronized for correct execution

Shared buffer must be updated atomically (all or none)

Shared Buffer

x=4 is updated but not y=8Y=8 is updated late

Plot is incorrect

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

Writer Reader

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Fall 2015, arz 2828

Critical Sections & Mutex

Access to the common resource is a critical section

Critical sections must be protected via mutual exclusion

We will discuss these in later lectures

tw leaves critical sectiontw enters

critical section

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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The Scheduling Problem Input

A set of n tasks Γ = {τ1, τ2, . . . , τn}, A set of m processors P = {P1, P2, . . . , Pm} A set of s types of resources R = {R1,R2, . . . , Rs} Constraints: timing (deadline), precedence

Output Assigning processors from P and resources from R to

tasks from Γ in order to complete all tasks under the specified constraints

This problem, in its general form, has been shown to be computationally intractable

To make the problem of constructing feasible schedules tractable, certain assumptions are made

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling Classification - 1

Preemptive The running task can be interrupted at any

time to assign the processor to another active task, according to a predefined scheduling policy

Non-preemptive A task, once started, is executed by the

processor until completion. All scheduling decisions are taken when the

current task terminates its execution

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling Classification - 2

Static Scheduling decisions are based on fixed

parameters (such as static priority), assigned to tasks before their activation

Dynamic Scheduling decisions are based on

dynamic parameters (such as dynamic priority) that may change during task execution

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling Classification - 3

Off-line A fixed set of tasks are known at start & never

change The scheduling algorithm is executed on the entire

task set before task activation The schedule is stored in a table and later executed

by a dispatcher On-line

Tasks can arrive at run time The scheduling decisions are taken at runtime every

time a new task enters the system or when a running task terminates

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Scheduling Classification - 4

Optimal An optimal schedule minimizes some given cost

function defined over the task set If there is no cost function, then the only concern is to

achieve a feasible schedule meeting deadlines An algorithm is said to be optimal with respect to

feasibility if it is able to find a feasible schedule, if one exists

Heuristic Uses a heuristic approach in taking its scheduling

decisions A heuristic algorithm tends toward the optimal

schedule, but does not guarantee finding it

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Guarantee-Based Algorithms

A dynamic scheduler with real-time deadline and admission control A new task arrives The task is accepted only if the deadlines of

current tasks are unaffected

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Example Scheduler Metrics

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Earliest Due Date (EDD)

Jackson’s algorithm A set of n aperiodic tasks A single processor Optimization metric

Minimizing maximum lateness Lmax=Maxi(fi-di)

Designation: 1 | sync | Lmax sync means that tasks arrive “synchronously”,

at the same time Each task can have a different computation time and

deadline But they all arrive at the same time

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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EDD Algorithm Given a set of n independent tasks, any

algorithm that executes the tasks in order of non-decreasing deadlines is optimal with respect to minimizing the maximum lateness

Because all tasks arrive at the same time, preemption is not an issue The static priority assigned to each task is

the deadline: the shorter the deadline, the higher the priority

We can assume that all tasks arrive at t=0 Each task is characterized by computation

time and deadline (C,d)

No random task arrival. All tasks arrive at the same time.

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Proof of EDD

Suppose there was a non-EDD schedule S. There must be two tasks a and b where a immediately precedes b but da > db. Why?

The schedule can be improved to reduce maximum lateness by interchanging a and b No non-EDD schedule can do better in

minimizing maximum lateness The complexity of the EDD algorithm is

O(nxlogn): the complexity of the sorting algorithm

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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1. Tasks are scheduled as soon as the CPU is available.

2. There is no preemption. A task runs to completion.

3. If the schedule is feasible, all deadlines are met and fi-di is negative for all i.

Non-EDD: i finishes earlier but has a later deadline than j. In this example both fi-di and fj-dj are negative.

Note that fj=f’i because tasks execute consecutively

EDD & Non-EDD Schedules

Two cases for possible value of L’max: L’max = f’i – di = fj-di <= fj – dj

L’max = f’j – dj <= fj – dj The non-EDD Lmax = fj-dj

So in both cases L’max <= Lmax

So EDD is no worst than non-EDD

Non-EDD

EDD

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Example 1J1 J2 J3 J4 J5

fi 1 8 4 7 3

di 3 10 7 8 5

Li -2 -2 -3 -1 -2

J4 has maximum lateness = -1

J1

J5

J3

J4

J2

Queue

DequeueCS555A – Real-Time Embedded Systems

Stevens Institute of Technology

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EDD & Feasibility

EDD produces a schedule which minimizes maximum lateness

But it may not be a feasible schedule in the sense of meeting all deadlines So EDD cannot be relied upon to obtain a

feasible schedule meeting all deadlines But if there does exist a feasible

schedule, then EDD can find it From any feasible schedule you can use

EDD to obtain another feasible schedule which minimizes maximum lateness

Complexity of EDD O(nlogn) – A heap sorting algorithm

CS555A – Real-Time Embedded SystemsStevens Institute of Technology

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Example 2J1 J2 J3 J4 J5

fi 1 4 2 10 6

di 2 5 4 8 6

Li -1 -1 -2 2 0

J1

J3

J2

J5

J4

Queue

Dequeue

Deadline missed

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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• The scheduler lets a task to continue to completion before scheduling another task• There is no timer interrupt

Dynamic Run-Time Scheduler

The scheduler is invoked by the ISR or the OS service call invoked by the user

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Tasks are switched in and out when the timer interrupt kicks in and invokes the scheduler .

Typically a lower numerical value represents a higher priority

• By user • Or by the scheduler possibly to prevent starvation of lower-priority tasks

In contrast, a non-preemptive priority-based scheduler allows a task to complete. The next task to run is determined by priority.

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Earliest Deadline First (EDF)

Horn’s algorithm N independent tasks with arbitrary arrival

time. Tasks are not synchronous Preemption is allowed 1 | preemp | Lmax

Optimization metric is the same as in EDD Minimizing maximum lateness Lmax=Maxi(fi-di)

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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EDF Algorithm

Given a set of n independent tasks with arbitrary arrival times, any algorithm that at any instant executes the task with the earliest absolute deadline among all the ready tasks is optimal with respect to minimizing the maximum lateness.

Complexity O(n2) if ready queue is a linear list O(nlogn) if the ready queue is implemented

as a heap

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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EDF Proof

This is a non-EDF feasible schedule Maximum lateness is Lmax=0 associated with J1

Preemption is allowed: so break up time in slices. Tasks can execute in disjointed intervals

Interchanging the execution of J4 and J2 at t=4 does not increase maximum lateness

Task J2 arrives at t=4. The scheduler rethinks the existing schedule and makes changes.

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

At time t=4, the executing task J4 has a deadline of td=15. (t)=arrival time; (tE)=execution time.

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EDF Proof - Continued

Interchange the execution of J2 and J4 at t=4. Maximum lateness remains the same at L=0

for J1 Continue this in all time slices

After the interchange the resulting schedule is also feasible because the deadline of J4 is after the deadline associated with J2.

CS555A – Real-Time Embedded Systems Stevens Institute of Technology

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Example Both J1 and J2 arrive at t=0. J1 is scheduled first because its deadline is (d1=2) < (d2=5).

Completed tasks• None

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Example - ContinuedJ3 arrives at t=2. J3 has a deadline of d3=4 whereas the currently executing task J2 has a deadline of d2=5. Because d3 < d2, J2 is preempted and J3 is dispatched for execution.

preemption Completed tasks• J1

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Example - ContinuedJ4 arrives at t=3. Its deadline is d4=10. The earliest deadline is still d3=4. So J3 remains in execution. No preemption at t=3.

Completed tasks• J1

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Example - ContinuedJ5 arrives at t=6. Its deadline is d5=9. which is earlier than the d4=10 of J4 which is currently executing. So J4 is preempted and J5 is dispatched.

preemption

Completed tasks• J1• J2• J3

Lmax = 0

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Some Observations

A schedule is computed at t=0 based on the ready tasks

The schedule is re-examined only when a new task arrives

You can view the task with the earliest deadline as having the highest priority

If a feasible schedule (one that meets all deadlines) exists, EDF will find it. It also has the minimum lateness

However an EDF schedule is not necessarily feasible (may not meet deadlines)

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Institute of Technology

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After task 1, task 4 has the earliest deadline but it cant’ be scheduled because it has a dependency on task 2 which must be scheduled first. So task 3 is the first EDF task meeting dependency requirements that can be scheduled.NO.

• Task 1: meets deadline d=2• Task 2: meets deadline d=5• Task 3: meets deadline d=4• Task 4: does NOT meet deadline d=3• Task 5: meets deadline d=5• Task 6: meets deadline d=6

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Institute of Technology

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Institute of Technology

LDF assumes a fixed, finite set of tasks with deadlines. No arrival of new tasks. No preemption.

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What’s nice about a leaf node is that no other task is dependent on it.

LDF assumes a fixed, finite set of tasks with deadlines. No arrival of new tasks. No preemption.

6

StackPush

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6

5

StackPush

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6

5

3

StackPush

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6

5

3

4

StackPush

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6

5

3

4

2

StackPush

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6

5

3

4

2

1

StackPop

StackPush

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So it is also optimal with respect to feasibility. Why?

The complexity of LDF is O(n2).

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1=1

r2=0c2=1d2=5

r3=0c3=1d3=4

r4=0c4=1d4=3

r5=0c5=1d5=5

r6=0c6=1d6=6

Assume all tasks arrive at ai=ri=0

All tasks require execution time ci=1

Rule of thumb for this strategy: the deadline of a task cannot exceed its own deadline or the minimum slack time of its dependent tasks.

ej is extecution time of task j

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Timing Definitions - Continued

Start time si is the time at which a task starts its execution Finishing time fi is the time at which a task finishes its

execution Response time Ri is the difference between the finishing

time and the request time: Ri = fi − ri Lateness: Li = fi −di represents the delay of a task

completion with respect to its deadline; note that if a task completes before the deadline, its lateness is negative

Laxity or Slack time: Xi = di − ai − Ci is the maximum time a task can be delayed on its activation to complete within its deadline

/ri

Xi = di − Ci when ai=0

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1’’=1

r2=0c2=1d2=5

r3=0c3=1d3=4

r4=0c4=1d4=3r5=0c5=1d5=5

r6=0c6=1d6=6

Start with i=1 Tasks immediately

depending on 1 D(1) = {2, 3}

d2-c2=4 d3-c3=3 d1’=min(1, min(4,3))=1

Slack time: Xi = di − ai − Ci = di – Cibecause ai = ri = 0 Rule of Thumb:The deadline of a task cannot exceed its own deadline or the minimum slack time of its dependent tasks.

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1’’=1

r3=0c3=1d3=4

r4=0c4=1d4=3r5=0c5=1d5=5

r6=0c6=1d6=6

Next select i=2 with d2=5 Tasks immediately depending

on 2 D(2) = {4, 5}

d4-c4=2 d5-c5=4 d2’=min(5, min(2,4))=2

r2=0c2=1d2’’=2

Slack time: Xi = di − ai − Ci = di – Cibecause ai = ri = 0 Rule of Thumb:The deadline of a task cannot exceed its own deadline or the minimum slack time of its dependent tasks.

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1’’=1

r3=0c3=1d3’=4

r4=0c4=1d4=3r5=0c5=1d5=5

r6=0c6=1d6=6

Next select i=3 with d3=4 Tasks immediately

depending on 3 D(3) = {6}

d6-c6=5 d3’=min(4, min(5))=4

r2=0c2=1d2’’=2

Slack time: Xi = di − ai − Ci = di – Cibecause ai = ri = 0 The deadline of a task cannot exceed its own deadline or the minimum slack time of its dependent tasks.

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1’’=1

r3=0c3=1d3’=4

r4=0c4=1d4’=3r5=0c5=1d5’=5

r6=0c6=1d6’=6

The remaining nodes are leaf nodes. No other task depends on them

So their deadlines remain unchanged

r2=0c2=1d2’’=2

Slack time: Xi = di − ai − Ci = di – Cibecause ai = ri = 0 The deadline of a task cannot exceed its own deadline or the minimum slack time of its dependent tasks.

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EDF With Precedence

1

2

4

5

3

6

r1=0c1=1d1’’=1

r3=0c3=1d3’=4

r4=0c4=1d4’=3r5=0c5=1d5’=5

r6=0c6=1d6’=6

Now apply normal EDF: Task 1 Task 2 Task 4 Task 3 Task 5 Task 6

r2=0c2=1d2’’=2

EDF with precedence rationalizes deadlines. Instead of accepting the given deadline, the algorithm ensures that the assigned “virtual” deadlines take into account deadlines of successor. A task cannot have a later deadline than the minimum slack of its successors.

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Optimality

EDF with precedence is optimal in the sense of minimizing maximum lateness

A schedule obtained may not be feasible Tasks may not meet their deadline

But if a feasible schedule exists, EDF with precedence will find it.

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