Cpi

Computer Peripherals & Interfacing CSE-333

Mahmud HasanLecturerDepartment of Computer Science & EngineeringStamford University, Bangladesh

Fall, 2011

Course Overview

Microprocessor Basics Memory Interface Basic I/O Interface Interrupts Direct Memory Access Controller 8237 Programmable Peripheral Interface 82C55 Programmable Interval Timer 8254 Programmable Interrupt Controller 8259A Parallel Printer Interface Universal Serial Bus, PCI Bus, ISA Bus NRZI Encoding Technique

Reference Books

The Intel Microprocessor (4th to 7th Edition)Barry B. Brey

IBM PC and Clones (2nd Edition)B. Govindarajalu

Microprocessors and Interfacing (2nd Edition)

Douglas V. Hall

Course in Progress


Lecture OneMicroprocessor Basics

Programming Model of Intel x86

Segment and Offset Address Segment Address defines the beginning of any memory

segment. Offset Address selects any location within this memory

segment.

address=segment×10+offset

Microprocessor Instruction- MOV

Microprocessor Instruction- MOV

Microprocessor Instruction- PUSHand POP

The PUSH instruction takes data froma 16-bit register, segment register or16-bit memory location and places itinto stack.

The POP instruction removes datafrom stack and places it into thetarget 16-bit register, segmentregister or 16-bit memory location.

Microprocessor Instruction- IN andOUT

Arithmetic InstructionsADD AL,BL AL=AL+BLADC AL,AH AL=AL+AH+CarrySUB CL,BL CL=CL-BLSBB AH,AL AH=AH-AL-CarryINC BL BL=BL+1DEC BH BH=BH-1CMP CL,BL CL-BLMUL CL AX=AL×CLMUL CX DX-AX=AX×CX

DIV CL AX/CL; AL contains quotient and AH contains remainder

Logic Instructions

AND, OR, XOR and NOT are the basic logic operations.

AND AL, BL means AL=AL and BL, so do the OR and XOR.

NOT means one’s complement.NEG means two’s complement.

TEST instruction performs the AND operation but without changing the content of the destination operand.

Shift Instruction

Rotate Instruction

JMP, CALL and RET Instructions

JMP Instruction transfers the program control to a memory location. If the JMP is within the current memory segment, then the JMP is near; else the JMP is far.

CALL is similar to JMP, except that it has a return address.

RET instruction is usually used at the ending of a procedure so that the flow of program can be returned to the address stored in stack.

Hierarchy of Memory

MicroprocessorCacheMemoryStorage Device

# Data Processing Speed Increases# Amount of Data Decreases# Cost of Production Increases

Registers

Questions on Lecture One1. Find the memory address specified by the following segment and offset.

1. CS=1000H and IP=2000H2. CS=2000H and IP=1000H3. CS=2300H and IP=1A00H4. CS=3456H and IP=ABCDH

2. What happens when we execute the instruction MOV BL,DX?3. Why do we need to study Computer Peripherals and Interfacing?4. Differentiate between-

1. PUSH and POP2. CALL and JMP3. AND and TEST4. NOT and NEG5. Shift and Rotate6. IN and OUT

5. Why is arithmetic shift is different than logical shift? What’s the difference?6. What are the responsibilities of Accumulator Register?

Course in Progress


Lecture TwoBUS Systems

The Universal Serial Bus (USB)

USB has two types of connectors, in either case, there are four pins on each connector.

The USB sues NRZI (non-return-to-zero-inverted) encoding technique for transmitting packets.

NRZI does not change the signal level for the transmission of logic-1, but the signal level is inverted for each change to a logic-0.

USB Connectors, Pin Configurations and Interface

NRZI Encoding

PCI Bus System PCI Stands for Peripheral System Interconnect.

It Has Plug-&-Play Characteristics.

PCI can function with 64 bit data bus and 32 bit address bus, sometimes, these buses are multiplexed.

It contains a series of registers, located in a small memory device on the PCI interface, that contain information about PCI board.

The information allow the computer to automatically configure the PCI card.

System Structure of PCI Bus

Block Diagram of PCI Interface

Comparison between ISA and PCI

ISA PCIISA Stands for Industry Standard Architecture.

PCI Stands for Peripheral Component Interconnect.

It doesn’t have Plug-&-Play Characteristics.

It has Plug-&-Play Characteristics.

ISA functions with 8 or 16 bit data bus.

PCI functions with 64 bit data bus.

The clocking speed is lower than that of PCI.

The clocking speed is greater than that of ISA.

ISA interfaces modems, sound cards etc.

PCI interfaces video controller, disk controller etc.

Questions on Lecture Two1. Draw the waveform as the result of NRZI encoding

of the digital data 0101010111000100101.

2. Explain the circuit operation of USB interface.

3. What is the purpose of memory on PCI expansion board?

4. What do you mean by Plug-&-Play Characteristics?

5. Differentiate and relate between PCI and ISA.

Course in Progress


Lecture ThreeThe 8237 DMA Controller

Basic Idea behind DMA Technique

Direct Memory Access (DMA) is a technique that allows thedirect data transfer between memory and I/O deviceskeeping the microprocessor temporary disabled.

Two control signals are used to request and acknowledgeDMA transfer.

1. HOLD pin is an input that is used to request a DMAaction.

2. HLDA pin is an output that is used to acknowledge aDMA action.

Timing for HOLD and HLDA

IF HOLD=logic-1, DMA action is requested. Microprocessor responds to it by suspending its execution and placing its address, data and control buses at high-impedence state. Then the I/O devices can access the system buses.

DMA Operation

Pin Configuration of 8237A0-A7: Address Pins DB0-DB7: Data PinsIOR: I/O Read PinIOW: I/O Write PinMEMR: Memory Read PinMEMW: Memory Write PinReady: Ready Signal PinHLDA: Hold Acknowledge PinCS: Chip Select PinCLK: Clock PinRESET: Reset Circuit PinDACK0-DACK3: DMA Acknowledge PinsDREQ0-DREQ3: DMA Request PinsAEN: Address Enable PinADSTB: Address Strobe PinHRQ: Hold Request PinEOP: End-of-Process Pin

Internal Registers of 8237 8237 has 9 internal registers for different purposes. Most of the registers are 8-bit long and each bit has its

special operation. The registers are: CAR, CWCR, BA and BWC, CR, MR,

BR, MRSR, MSR, SR. As an example of typical 8237 internal register, let us

notice the following bit pattern.

0 0 1 0 0 1 1 0

Registers’ Descriptions CAR: CAR stands for Current Address Register. It is

used to hold the 16 bit memory address usedfor DMA transfer.

CWCR: CWCR stands for Current Word CountRegister. It holds the number of bytes to betransferred.

BA-BWC: Base Address and Base Word Count registersare used when auto initialization is selectedfor any channel. They reload CAR and CWCRafter a DMA action is accomplished.

CR: Command Register programs the operation of8237 DMA controller.

MR: Mode Register programs the mode ofoperation for a channel.

BR: Bus Request register is used to request a DMAtransfer via software.

Registers’ Description (continued)

MRSR: Mask Register Set/Reset sets or clears thechannel masks. If the mask is set, the channelis disabled.

MSR: Mask Register clears or sets all the masks withone command instead of individual channelsas with MRSR.

SR: The Status Register shows the status of eachDMA channel.

8237 Command Register

Questions on Lecture Three1. What are the functions of HLDA and HOLD pins in

case of DMA Transfer?

2. Draw a block diagram and illustrate how a DMAtransfer takes place.

3. Discuss the functions of different pins of 8237.

4. How many registers does 8237 have? Brieflydiscuss each of them.

5. Draw the bit pattern of command register andindicate the functions of each bit.

Course in Progress


Lecture FourMemory and I/O Interface

Basic Input Interface: Three State Buffer

A three-state-buffer is a basicinput device. It fixes up thevoltage level for the binarydata.

Whenever SEL is logic-0, thecontents of the switchers arepassed through the bufferand sent to microprocessor.

Basic Output Interface: Latch

The peed of microprocessor is much larger than the speedof output devices. To synchronize their speeda latch is used. The latchmakes a delay of the signalgenerated for the outputdevices.

This synchronization processis referred to as Handshakingor Polling.

Address Decoding Address Decoding refers to the operation of preparing and

sending different addresses from the microprocessor to thememory or I/O devices so that various devices can be used inthe system.

Without address decoding only one memory or I/O devicecould be connected to a microprocessor which would make itvirtually useless.

Most of memory or I/O devices have different number ofaddress pins, 8086 microprocessor has 20 address pins. Ifmicroprocessor sends 20 bit address, most of the devices willnot operate.

To resolve this problem, we need a technique that mustconvert the 20 bit address to desired-number-of-bit address.This task is known as address decoding.

Types of Address Decoding

Since a computer system involves simply amicroprocessor, I/O devices and a memory; weneed to interface the microprocessor with either I/Oor memory.

Therefore, we have to decode address only foreither I/O devices or memory.

Thus we have either memory address decoding orI/O address decoding.

Memory Decoding: A simple NAND gate Decoder

A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0

1 1 1 1 1 1 1 1 1 X X X X X X X X X X X1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1Therfore, Starting Address FF800 H

Ending Address FFFFF H

Memory Decoding: 3-to-8 Line Decoder (74LS138)

A circuit that uses eight 2764 EPROMs for a 64Kx8 section of memory in an 8088 microprocessor based system:

Fixed Addressing and Variable Addressing

Fixed Addressing: The 8-bit form (P8) where the I/Oaddress of 16 bit is stored is called a fixed addressbecause it is stored with the instruction.IN AL, 12H

Variable Addressing: The 16-bit I/O address in DX iscalled a variable address because it is stored in DXand then used to address the I/O device.MOV DX, 0063HOUT DX, AL

Isolated I/O and Memory Mapped I/O

Isolated I/O Memory Mapped I/O

Difference between Isolated I/Oand Memory Mapped I/O

Isolated I/O Memory Mapped I/O

The I/O locations are isolated from memory system in a separated I/O address space.

I/O locations are mapped within the memory.

Memory can be expanded to its full size without using any of memory space for I/O devices.

Full memory can’t be expanded since a portion is used as I/O map.

Data transfer between microprocessor and I/O requires IN, INS, OUT and OUTS instructions.

No such instruction is required for transferring data.

Expanded amount of memory. Reduced amount of memory.

Separate control signals that indicate IORC or IOWC operations.

IORC and IOWC have no function and may reduce the amount of circuitry.

Questions on Lecture Four1. Draw the basic input interface and basic output interface

and explain how they operate in a computer system.2. Define Address Decoding. Briefly explain why address

decoding is necessary.3. Differentiate between Isolated I/O and Memory Mapped

I/O.4. With necessary diagram explain the construction and

operation of a simple NAND gate decoder.5. Design a 64KB EPROM to select the memory for address

range F0000H to FFFFFH.6. Design a circuit by using 3-8 line decoder to select the

memory for address range D8000H-D8FFFH.7. Design a circuit that uses eight 2764 EPROMs for a 64KBx8

section of memory in an 8086 microprocessor basedsystem to select the memory for address range D0000H-DFFFFH.

Course in Progress


Lecture FiveParallel Printer Interface

Signals in Centronic Interface

Printer Controller Printer

Data LinesSTROBE (take data)

ACK (give data)

busy

PE (no paper)

ERROR (fault)

SLCT IN (enable interface)

SLCT (selected)

AUTO FEED XT (h/w line feed)

INIT (reset)ground

Interfacing and Centronic Interface

Interfacing

The process of connecting peripherals with themicroprocessor for transferring instructions andresults is known as interfacing.

Centronic Interface

The interface that shows or provides a handshakingprotocol between a computer and a printer is calledthe centronic iterface.

Centronic Interface Timing Diagram

5 μs

0.5 μs

0.5 μs

0.5 μs

STROBE

Data

ACK

Busy

The printer controller sends data to the printer.After a minimum gap of 0.5 μs, STROBE is low and kept lowfor minimum duration 0.5 μs. As soon as STROBE is low, theBusy pin is high. The controller should retain data on the datalines for a minimum interval of 0.5 μs from the trailing edge of STROBE. When the printer is ready to receive next character of data,It makes ACK line low, thereby removing Busy.

Programming Sequence for Printer Interface

Start

Establish Logical Connection

PrinterLogically

Connected?

Reset the Printer

Read Device Status

Is Printer Busy?

Send Data

Make STROBE Active Make STROBE Inactive Read Status

Is ACKLow?

Send Next Data

Is ACK

High forLong Time?

Analyze the Reason

Display Error Message

Act as directed by the userYes

No

Yes

No

No

No

Yes

Yes

Line Printer (LPT) LPT stands for Line Printer which is known as the

parallel printer interface. This interface gives the useraccess to 8-lines that can be programmed to send orreceive parallel data.

The parallel port LPT1 operates at I/O addresses378H, 379H and 37AH. The secondary port LPT2, ifpresent, operates at I/O addresses 278H, 279H and27AH.

The centronic interface uses two connectors: a 25-pinD-Connector on the back of the PC and a 36-pincentronic on the back of the printer.

Data Port and Status Registerof LPT

Port 378HBit-0Bit-7

9 8 7 6 5 4 3 pins

It is the data port that connects to bits D0-D7.

Port 379H

x x x

NERROR (1=no error)ONLINE (1=online)PAPER (1=out of paper)

ACK (1=acknowledge)

NBUSY(1=not busy)

This is status register which is a read-only port that returns theinformation from the printer through signals.

Additional Status Port of LPT

x x

Port 37AH

STR (pulse high to print)

ALF (1=line feed by printer)

INI (0=initialize printer)

DSL (1=select printer)

IRQ (1=enabled)

Bidirectional (1=input, 0=output)

Reading or Writing Parallel PortIf the bidirectional bit of port 37AH is set, the port is initialized for reading.

# Initialization:MOV AL, 20HMOV DX, 37AHOUT DX, AL

# Reading:MOV DX, 378HIN AL,DX

Again, if the bidirectional bit of port 37AH is reset, the port is initialized for writing.

# Initialization:MOV AL, 00HMOV DX, 37AHOUT DX, AL

# Writing:MOV DX, 378HMOV AL, WRITE-DATAOUT DX, AL

Questions on Lecture Five1. Define Interfacing and Centronic Interface.

2. Draw and explain the centronic interface timing diagram.

3. Show the signals that are interacting in a centronic interface. Explaineach of their functions.

4. Draw the flow-chart of the programming sequence that are followedby software routines for printer interface.

5. What do you mean by LPT? Illustrate the contents of the data port,status register and additional status port of LPT.

6. With appropriate example show how the parallel port can be read orwritten.

7. Explain why we have to send 20H and 00H to port 37AH for initializingreading and writing respectively.

Course in Progress


Lecture SixProgrammable Peripheral Interface

(82C55)

Basic Description of 82C55 The 82C55 is a very popular, cost effetive interfacing component for μP. It has 24 pins and three I/O ports. Group-A consists of Port-A and upper half of Port-C. Group-B consists of Port-B and lower half of Port-C. Register selection is done by A1, A0 pins. It can operate in three distinct modes of operations:

Mode-0 (simple I/O) Mode-1 (strobed I/O) Mode-2 (bidirectional I/O)

The I/O port assignment of 82C55

Operating Modes Mode-0 Operation:

It causes the 82C55 to function as either a buffered input device oras a latched output device. For example, 82C55 can be interfacedwith LED display (latched output) or with keyboard (bufferedinput).

Mode-1 Operation: It causes Port-A and/or Port-B to function as latching input device.

Port-C is used for control or handshaking signals in this mode.

Mode-2 Operation: It allows only group-A. Here, Port-A becomes bidirectional,

allowing data to be transmitted and received over the same eightwires.

Programming 82C55

Command Byte B

Command Byte AThe Command Byte A functions for group-A and Group-B and Command Byte B sets or resets the bits of Port-C only if 82C55 is programmed in mode-1 or mode-2.

Group-A can operate in all three modes while Group-Bcan operate in only mode-0 and in mode-1.

Control Word and Programming 82C55

Control Word

It is a word stored in a register named control register used to control the operation of a program of a digital device.

Find the control word for PA=out, PB=in, PC0-PC3=in, PC4-PC7=out; and write a program to get data from Port-B and send it to Port-A. In addition, data from PCL is sent out to the PCU. Use port addresses 300H-303H for 82C55 chip.

1 0 0 0 0 0 1 1

Therefore, Control Word = 83H

The Program (continued)B82C55 EQU 300HCNTL EQU 83HMOV DX, B82C55+3MOV AL, CNTLOUT DX, ALMOV DX, B82C55+1IN AL, DXMOV DX, B82C55OUT DX, ALMOV DX, B82C55+2IN AL, DXAND AL, 0FHMOV CL, 4ROL AL, CLOUT DX, AL

Basic Structure of Delay Code for Delay

DELAY PROC NEARMOV CX, XXXXD1:

LOOP D1RET

DELAY ENDP

Finding Value for XXXX

pTimeForLooDelayTimeXXXX =

Example:

In pentium-4 system, loop requires 5 clocks.And the clock rate is 2GHz. Let, T be Timefor Loop.

Since T=1/f secor T=1/(2x109) secor T=5x10-10x109 nsor T=0.5 nsTherefore, Delay Time= 0.5x5 ns=2.5 ns

8-Digit LED Display Interfaced to 8088 Microprocessor through 82C55

Port-B provides logic-0 to select which LED will operate.Port-A provides particular values for a selected LED.

Multiplexing 8-Digit LED DisplayMOV AL, 80HMOV DX, 703HOUT DX, ALDISP PROC NEAR

PUSHFMOV BX, 8MOV AH, 7FHMOV SI, OFFSET MEM-1MOV DX, 701H.REPEAT

MOV AL, AHOUT DX, ALDEC DXMOV AL, [BX+SI]OUT DX, ALCALL DELAYROR AH, 1INC DXDEC BX

UNTIL BX==0POPFRET

DISP ENDP

Suppose, 82C55 is interfaced tomicroprocessor through PAL16L8so that it functions at I/O port0700H-0703H

Operation of a Stepper Motor

A stepper motor is a digitalmotor as it moves in discrete steps.

Figure(a) shows that the rotoris repelled by the same poleand moves a step to 45o. Then it is attracted by the different pole and moves another step to 135o. Thus it also movesUpto 225o and 315o.

Interfacing Stepper Motor through 82C55

# In order to flow high current through the coils, darlington amplifiers are used in stepper motor interfacing.

# Since a motor is an inductive load, it will produce a back EMF which could damage second transistor.The single diode prevents the damage by sorting out the back EMF.

Controlling Stepper Motor in its Full Step Operation

The following procedure controls the stepper motor’s full step operationwhere the motor is interfaced to the port A (40H) of 82C55.

PORT EQU 40HSTEP PROC NEAR

MOV AL, POSOR CX,CXIF !ZERO?

IF !SIGN?.REPEAT

ROL AL,1OUT PORT, ALCALL DELAY

.UNTIL CXZELSE

AND CX, 7FFFH.REPEAT

ROR AL, 1OUT PORT, ALCALL DELAY

.UNTIL CXZENDIF

ENDIFMOV POS, ALRET

STEP ENDP

Interfacing a 4×4 Key-Board

Port-A is programmed to read the rows while Port-B is programmedto select a column. If 1110 is output to Port-B, column-0 has logic-1.So the four keys of column-0 are selected. Now, if a key is pressed incolumn-0, corresponding Port-A line can detect the stroke.

Electrical contacts in mechanical push buttonswitches often make and break contacts severaltimes when the button is first pushed. This is calledDebouncing. A debouncing circuit removes the resulting ripplesignal and provides a clean transition to its output.

Mode-1 and Mode-2 Operation of 82C55.

Mode-1 Strobed Input

Mode-1 Strobed Output

Mode-2 Bidirectional Input

Mode-1 Strobed Input

Mode-1 Strobed Output

Mode-2 Bidirectional Operation

Questions on Lecture Six What does PPI stand for? Give a brief description of 82C55 PPI. What are the operating modes of 82C55? Discuss in short. Show the I/O port assignment of 82C55. Show the content of command byte-A and command byte-B of 82C55. What do you mean by control word? Discuss the basic structure of Delay. Interface an 8-digit LED display to microprocessor through 82C55. Write a procedure that multiplexes the 8-digit LED display where this

procedure must be called from a program at whenever possible to display7-segement coded data from memory.

Explain the Full-Step Operation of a Stepper Motor. How is it interfaced toMicroprocessor?

What are the purposes of using Darlington Amplifiers in Stepper MotorInterfacing? What does diode do here?

Write an assembly language program that controls the full-step operationsof a Stepper Motor.

Define Debouncing. Illustrate how a 4x4 keyboard can be interfacedthrough 82C55 PPI.

Explain Mode-1 and Mode-2 operation of 82C55.

Course up to Mid-Term


Mid-Term!

Course in Progress


Lecture SevenInterrupt

Defining Interrupts

An Interrupt is a hardware initiated procedure thatinterrupts whatever program is currently executing bythe microprocessor and requests it to perform somespecific tasks.

Interrupts are particularly useful when interfacing I/Odevices that provide or require data at relatively lowdata transfer rates.

Types of Interrupts The Microprocessor has two types of interrupts-

Hardware Interrupts Software Interrupts

Hardware Interrupts

Two pins are available for it- INTR and NMI.

Software Interrupts

It can be caused by the commands like INT, INT0, INT3and BOUND.

Hardware Interrupts Revised INTR

The INTR pin is level sensitive which means that it must be held atlogic-1 level until it is recognized. INTR is set by an external event andcleared inside the interrupt service procedure. INTR is automaticallydisabled once it is accepted by the microprocessor and re-enabled bythe IRET instruction at the end of the ISP.

NMI

NMI stands for Non-Maskable-Interrupt which is an edge triggeredinput that requests an interrupt on the positive edge. After a positiveedge, the NMI pin must remain at logic-1 until it is recognized by themicroprocessor. Before the positive edge is recognized, the NMI pinmust be a logic-0 for at least two clocking periods.The NMI is often used for parity errors and other major system faultssuch as power failure.

Difference between RET and IRET Instructions

RET instruction is used for hardware interruptsbut IRET is used for both hardware andsoftware interrupts.

RET only retrieves the return address from thestack while IRET also retrieves a copy of flagregister from the stack.

Power Failure Detection by NMI

Converting INTR to Edge-Triggered Interrupt Request

Questions on Lecture Seven How will you define Interrupt? When interrupts are

useful? Give a brief classification of Interrupts. Differentiate

between hardware interrupts and software interrupts. Write short notes on INTR and NMI. Note down the basic

difference of them. Differentiate between RET and IRET instructions. With necessary sketch, briefly describe how NMI detects

power failure. How can we make the INTR edge-triggered? Draw the

necessary circuit arrangement for this task. Write down at least two specific interrupt names that are

performed by NMI.

Course in Progress


Lecture EightProgrammable Interrupt Controller

(8259)

Introduction and Importance of 8259A PIC The 8259A is a PIC. It is called a priority interrupt

controller because it can add eight vectored priorityencoded interrupts to the microprocessor.

The 8086 microprocessor has only two interrupt inputs-INTR and NMI. As the microprocessor cannot avoid NMI,only one interrupt (INTR) is left for all other applications.To have interrupts from multiple sources, we need anexternal device that helps to have multiple interrupts.

8259A is such a device that can assign priority to eachinterrupt request and inform the microprocessoraccordingly.

Functional Block Diagram of 8259A

Interfacing 8259A to Microprocessor

Without any other additionalhardware, 8259A can beexpanded to accept up to 64interrupt requests. But, forthis expansion, one master8259A and eight slave 8259Aare required.

Command Words of 8259A 8259A is programmed by two command words called

Initialization Command Words (ICW) and OperationCommand Words (OCW).

ICWs are programmed before the 8259A is able tofunction in the system and dictate the basic operationsof 8259A.

OCWs are programmed during the normal course ofoperation and control the operations of 8259A.

Initialization order of ICWsICW1

ICW2

In Cascade Mode?

ICW3

ICW4

Is ICW4 needed?

Ready to accept interrupt request

YES (SNGL=0)

NO(SNGL=1)

YES (IC4=1)NO (IC4=0)

ICW1 is selected When A0=0Other ICWs are selected when A0=1

For OCW1, A0=0.But for all other OCWs, A0=1.

Describing ICW1

ICW1 programs the basic operations of 8259A.

Describing ICW2

ICW2 selects the vector number used with the interrupt request input.

Describing ICW3

Master Device

Slave Device

ICW3 indicates where the slave is connected to the master.

Describing ICW4

ICW4 is used with only8086-Pentium microprocessors.

Special Fully Nested Mode and Automatic End of Interrupt

Special Fully Nested ModeSelecting SFNM allows the highest priority interruptrequest from a slave to be recognized by the masterwhile processing another interrupt from a slave.

Automatic End of InterruptIf it is selected, the interrupt automatically resets theinterrupt request bit and does not modify priority. It isthe preferred mode of operation for 8259A and reducesthe length of ISPs. If it is not selected, the EOI commandof OCW2 are used.

Describing OCW1

OCW1 is used to set and read the IMR. When a mask bit is set, it will turn-off (mask) the corresponding interrupt input.

Describing OCW2

OCW2 selectsthe way 859Aresponds toan Interrupt.

Describing OCW3

OCW3 selects the register to be read,the operation of the special mask registerand the poll command.

PIC Terminologies Non Specific End of Interrupt:

A command sent by the ISP to signal the end of interrupt. The 8259A automatically determineswhich interrupt level was active and resets the correct bit of the interrupt status register.Resetting the status bit allows the interrupt to take action again or a lower priority interrupt totake effect.

Specific End of Interrupt:

A command that allows a specific interrupt request to be reset. The exact position isdetermined with bits L2-L0 of OCW2.

Rotate on Non Specific EOI:

It is similar to NSEOI except that it rotates interrupt priorities after resetting the interruptstatus register bit. If IR4 was first serviced by this command it becomes the lowest priorityinterrupt input and IR5 becomes the highest priority.

Rotate on Specific EOI:It is similar to specific EOI except that it selects rotating priority.

Rotate on Automatic EOI:Selects automatic EOI with rotating priority. This command must be sent to 8259A once if thismode is desired. If this mode must be turned off, use the clear command.

Set Priority:Allows the programmer to set the lowest priority interrupt input using L2-L0 bits.

Questions on Lecture Eight Mention the importance of Programmable Interrupt

Controller. Why do we call it priority interrupt controller? Draw the block diagram of 8259A and explain the task of each block. How many internal registers does 8259A have? Mention their functionalities. What do you mean by ICW and OCW? State each of their tasks. How does 8259A handle master-slave interrupt control? Explain with appropriate

figure. Write down the order of ICWs in which they should be initialized. Write short notes on-

Automatic End of Interrupt Special Fully Nested Mode Non Specific End of Interrupt Specific End of Interrupt Rotate on NSEOI Rotate on SEOI Rotate on Automatic EOI Set Priority

Course in Progress


Lecture NineProgrammable Interval Timer

(8254)

Purpose of Programmable Interval Timer The programmable interval timer is used in

personal computer for controlling real timeevents such as real time clocks, eventscounter, motor speed control and directioncontrol. It does the following works in a PC-

Generate a basic timer interrupt that occurs atapproximately 18.2 Hz.

Cause the DRAM memory system to be refreshed. Provide a timing source to the internal speaker and

other device.

Internal Structure of 8254

Pin Definition of 8254

Gate input controls the operation of the counter in some mode of operation.

Command Byte of 8254

Mode of Operation of 8254 8254 has three counters. Each counter can operate in any of six

available modes.

Mode-0: In this mode, 8254 counter can work as event counter. The output is zero untiln+count. If count=5, the out=0 for 6 counts beginning with n. G needs to be 1 in thiscase.

Mode-1: In this mode, the counter functions as retriggerable monostable multivibrator.When G triggers the count, the count generates logic-0 for the duration of count. If G istriggered within a output pulse, the count is reloaded and out continues for the totallength.

Mode-2: In this mode, the counter can generate a series of continuous pulses. Thecount determines the separation between pulses. For count=10, the out=1 for 9 clockingperiods and out=0 for 10th clock period.

Mode-3: It generates a continuous square wave if G=1. Here, out=1 for half of countand out=0 for other half of count. But if count=5(odd), out=1 for 3 clock period andout=0 for 2 clock period.

Mode-4: In this mode, counter produces a single pulse at output. If count=10, out=1 for10 clocking period and out=0 for 1 clocking period. G must be 1.

Mode-5: It is similar to mode-4 except that G is triggered by hardware instead ofsoftware.

Mode-0, Mode-1, Mode-2

Mode-3, Mode-4, Mode-5

Interfacing 8254 with Microprocessor

Interface the 8254 so that it functions at I/O locations 0700H, 0702H, 0704H and0706H. If the clock rate of the microprocessor is 8MHz, then write a procedure thatgenerates 100KHz square wave at OUT0 and 200KHz continuous pulse at OUT1.

Interfacing 8254 with Microprocessor (continued…)

8010100

1081008

3

6

=××

=KHz

MHz

4010200

1082008

3

6

=××

=KHz

MHz

Wave shaping by 8254 Program COUNTER 1 of 8254 so that it generates a

continuous series of pulses that have high time of100 µs and a low time of 1 µs.

MOV AL, 74HOUT CONTROL, AL

MOV AL, 65H

OUT TIMER1, AL

MOV AL, 0

OUT TIMER1, AL

100+1=101 µs101D=65HCOUNT=65H

DC Motor Speed & Direction Control

When Q=1, Q3=ON, Q2=ONQ1=OFF, Q4=OFF

When =1, Q1=ON, Q4=ONQ3=OFF, Q2=OFF

If =1, motor rotates in reverse direction

If Q=1, motor rotates in forward direction

Timing for Motor Speed and Direction Control

DC Motor Speed & Direction Control

Questions on Lecture Nine Why is Programmable Interval Timer used in personal computers?

What are its major tasks? Draw the internal structure of 8254 and briefly mention each of

the block’s function. Describe the command byte of 8254 with necessary sketch. With details signals, mention the mode of operations of every

counter of 8254. Interface an 8254 so that it functions at XX10H, XX12H, XX14H and

XX16H using operating frequency 8 MHz. Write a program thatprograms COUNTER 2 to generate an 80 KHz square wave if theCLK input to COUNTER 2 is 8MHz.

Draw the schematic diagram of DC Motor and its associative drivercircuitry including the correlation with the 8254 timer and Flip-Flop. Briefly explain the operation of motor driver circuitry.

Explain the timing diagram of forward and reverse directionrotation of a DC Motor.

Write a program that can control the speed and direction of a DCMotor.

Course Ends


Term Final !!!

My best wishes for Your Life…

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