CPLD Board Diagnostic System Reference Manual

CPLD Board Diagnostic System Reference Manual Version: 1.0 Date: November 10, 2004 Designed and Developed By:

System Level Solutions, Inc. (USA) 14702 White Cloud Ct. Morgan Hill, CA 95037 System Level Solutions (India) Pvt. Ltd 9/B, Radhakrishna Colony MangalPura Road, Anand-380001

CPLD Board Diagnostic System Reference Manual

System Level Solutions i

About this Manual

This manual provides details about the CPLD Board and the embedded CPLD Board Diagnostic System. The following table shows the CPLD Board Diagnostic System Reference Manual revision history: Date Description November 2004

First publication of the CPLD Board Diagnostic System Reference Manual

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CPLD Board Diagnostic System Reference Manual

ii System Level Solutions

Contact Information

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CONTENTS

ABOUT THIS MANUAL........................................................................................................ I

HOW TO FIND INFORMATION......................................................................................... I

CONTACT INFORMATION................................................................................................II

LIST OF FIGURES .............................................................................................................. IV

LIST OF TABLES ..................................................................................................................V

1 INTRODUCTION............................................................................................................1 1.1 OVERVIEW OF THE CPLD BOARD (ENTRY LEVEL TOOL) ...........................................1

2 CPLD BOARD COMPONENT DETAILS ...................................................................3 2.1 MAX CPLD...............................................................................................................4 2.2 POWER SUPPLY JACK..................................................................................................4 2.3 CLOCK SELECTION HEADER........................................................................................4 2.4 JTAG DOWNLOAD HEADER .......................................................................................5 2.5 8-WAY DIP SWITCHES ...............................................................................................5 2.6 PUSH BUTTON SWITCHES............................................................................................6 2.7 LED............................................................................................................................7 2.8 7-SEGMENT LED DISPLAY .........................................................................................8

3 CPLD BOARD DIAGNOSTIC SYSTEM...................................................................11 3.1 OVERVIEW ................................................................................................................11 3.2 SELECTING CPLD BOARD DIAGNOSTIC TEST USING DIP SWITCHES........................12 3.3 CPLD BOARD DIAGNOSTIC TESTS ...........................................................................12

3.3.1 7-Segment LED Display and LED Test ...........................................................12 3.3.2 DIP Switch Test................................................................................................13 3.3.3 Push Button Switch Test...................................................................................14

3.4 IMPORTANT TIPS FOR USING CPLD BOARD DIAGNOSTIC SYSTEM ...........................15

4 CPLD SIGNAL MAPPING ..........................................................................................17 4.1 CLOCK SIGNAL .........................................................................................................17 4.2 DIP SWITCH SIGNALS...............................................................................................17 4.3 PUSH BUTTON SWITCH SIGNALS...............................................................................18 4.4 7-SEGMENT LED DISPLAY SIGNALS.........................................................................18

5 REFERENCES...............................................................................................................19

LIST OF FIGURES FIGURE 2-1 GENERAL DIAGRAM OF THE CPLD BOARD .............................................................3 FIGURE 2-2 CLOCK SELECTION HEADER ....................................................................................4 FIGURE 2-3 DIP SWITCHES AND CORRESPONDING HEADERS......................................................6 FIGURE 2-4 PUSH BUTTON SWITCHES, LEDS AND CORRESPONDING HEADERS ..........................7 FIGURE 2-5 7-SEGMENT LED DISPLAYS ....................................................................................8 FIGURE 2-6 SEGMENT IDENTIFICATION OF THE 7-SEGMENT LED DISPLAY ................................8

LIST OF TABLES TABLE 2-1 CLOCK SELECTION FOR THE CPLD USING CLOCK SELECTION HEADER ...................5 TABLE 3-1 DIAGNOSTIC TEST SELECTION USING DIP SWITCHES .............................................12 TABLE 3-2 SEGMENT MAPPING FOR THE DIP SWITCH TEST ......................................................13 TABLE 3-3 SEGMENT MAPPING FOR THE PUSH BUTTON SWITCH TEST ......................................14 TABLE 4-1 MAPPING OF THE CLOCK SIGNAL ............................................................................17 TABLE 4-2 MAPPING OF THE DIP SWITCH SIGNALS .................................................................17 TABLE 4-3 MAPPING OF THE PUSH BUTTON SWITCH SIGNALS .................................................18 TABLE 4-4 MAPPING OF THE 7-SEGMENT LED DISPLAY SIGNALS ...........................................18

1 INTRODUCTION

This section gives general introduction to the CPLD Board (the “Entry Level Tool”).

It also gives information about how this reference manual is organized.

1.1 Overview of the CPLD Board (Entry Level Tool)

The CPLD Board (Entry Level Tool) is designed for the MAX Device (EPM3064). This

board can be used for any other device having similar pin out configuration. The

user is encouraged to check out the board schematics for the further details. This

board contains various peripherals, such as DIP Switches, Push Button Switches,

LEDs, 7-Segment LED Displays, etc. interfaced with the MAX Device.

The board is by default programmed with a *.jam file, which contains CPLD Board

Diagnostic System. This system can be used to test all the peripherals that are on

board with the CPLD, such as, DIP Switches, Push Button Switches, LEDs, 7-

Segment LED Displays, headers, etc.

The second section gives the information about all the hardware components and

peripherals on this CPLD Board.

The third section gives the information regarding the CPLD Board Diagnostic

System that is embedded within the CPLD. This section gives details about all the

tests that can be done using this system and how to use this system for testing

onboard peripherals.

The fourth section gives signal mapping between the CPLD and all the peripherals.

The fifth section indicates the reference material associated with this board.

Introduction CPLD Board Diagnostic System Reference Manual

2 System Level Solutions

2 CPLD BOARD COMPONENT DETAILS

This section gives the component details about the CPLD Board Hardware. This

section describes all the peripherals that are integrated with the CPLD.

The generalized diagram of the CPLD Board is shown in Figure 2-1. As shown in the

figure, the board contains two 8-way DIP Switches, eight Push Button Switches,

eight LEDs, two 7-Segment LED Displays, Connection headers for inputs and

outputs (shared), JTAG header for downloading the bit files and ten clock selection

options for the CPLD system clock.

Figure 2-1 General Diagram of the CPLD Board

The subsequent sections describe the Hardware components that are integrated

with the CPLD.

CPLD Board Component Details CPLD Board Diagnostic System Reference Manual


2.1 MAX CPLD

This board is mainly designed around EPM3064ALC44-10 (U1) (MAX CPLD). The

CPLD used is a 44-pin PLCC package used in PLCC socket. So the user can change

the CPLD part if it gets damaged. This also gives the flexibility to the user to

replace the EPM3064 part with another CPLD part having similar pin out

configuration to be used with the appropriate HDL design file.

The core voltage required for the CPLD is 3.3 volts while the IOs can be operated at

3.3 volts or 5.0 volts. This board uses 3.3 volts as both the core voltage and IO

voltage. Since the IOs are 5.0 volt tolerant, user can use 3.3 volt or 5.0 volt input

to the CPLD.

2.2 Power Supply Jack

The CPLD board has an input power supply jack (SW1) to get the unregulated

supply to the input of the regulator of +3.3V. The polarity of the Jack is center

Positive. The user can use 6VDC, 500mA SMPS power supply with this board.

2.3 Clock Selection Header

This board contains a 20-pin Clock Selection Header (JP1) for selecting the input

system clock to the CPLD.

The board uses 32.768 KHz Crystal to generate its clock. This 32.768 KHz

frequency is divided by 14-Stage ripple-carry Binary Counter/Divider and Oscillator

chip HEF4060. This chip gives 10 clock outputs, out of which user can select any

clock (as per the requirement) using Clock Selection Header (JP1).

Figure 2-2 shows the Clock Selection Header JP1 and how the user can select any

of the 10 available clocks using jumper.

Figure 2-2 Clock Selection Header

Pin 2 Pin 1

Pin 20 Pin 19

CPLD Board Diagnostic System Reference Manual CPLD Board Component Details

System Level Solutions 5

Table 2-1 shown below gives information about which clock is fed to the CPLD by

shorting which pins of the Clock Selection Header (JP1) using jumper.

Table 2-1 Clock Selection for the CPLD using Clock Selection Header

Sr. No. Pins to be shorted of Clock

Selection Header JP1 Clock Frequency

(Available to the CPLD)

1. JP1.1 – JP1.2 2.048 KHz 2. JP1.3 – JP1.4 1.024 KHz 3. JP1.5 – JP1.6 512.0 Hz 4. JP1.7 – JP1.8 256.0 Hz 5. JP1.9 – JP1.10 128.0 Hz 6. JP1.11 – JP1.12 64.0 Hz 7. JP1.13 – JP1.14 32.0 Hz 8. JP1.15 – JP1.16 8.0 Hz 9. JP1.17 – JP1.18 4.0 Hz 10. JP1.19 – JP1.20 2.0 Hz

2.4 JTAG Download Header

This board contains the standard JTAG download header (JP4) to download the

design into the CPLD (*.jam files, *.jbc files, etc.). This header can also be used for

the JTAG Boundary Scan Testing of the CPLD (if the JTAG pins are not used as IOs

in the design). The user can use Altera’s ByteBlaster or MasterBlaster or USBBlaster

cable to download the design into the CPLD using this header.

Important Note:

It should be noted that all the JTAG pins are shared with four pins of DIP switch

(SW9 and hence JP3). The user is encouraged to refer to the schematics for further

details.

2.5 8-Way DIP Switches

The CPLD Board contains two 8-way DIP switches (SW4 & SW9), which can be used

as two 8-bit user inputs. The CPLD reads HIGH when the DIP switch is turned OFF

and reads LOW when the DIP switch is turned ON.


6

Figure 2-3 below shows the two DIP switches (SW4 & SW9):

Figure 2-3 DIP Switches and corresponding Headers

All the pins of SW4 a

JP2. Similarly all the p

pin header JP3. This

inputs as external inp

give external inputs to

Important Note:

It should be noted th

with the JTAG pins. T

details.

2.6 Push Button Sw

This board contains e

which can be used a

Switch is pressed and

Important Note:

It should be noted th

The user is encourage

Figure 2-4 below show
JP2 SW4 SW9 JP3
System Level Solutions

re also mapped one-to-one with all the pins of 8-pin header

ins of SW9 are also mapped one-to-one with all the pins of 8-

facility is provided to give the flexibility to use these 8-bit

uts. The user can keep all the DIP switches turned OFF and

JP2 and JP3 to use them as external inputs to the CPLD.

at four pins of DIP switch (SW9 and hence JP3) are shared

he user is encouraged to refer to the schematics for further

itches

ight push button switches (SW2-SW11 except SW4 & SW9),

s user inputs. The CPLD reads LOW when the Push Button

reads HIGH when the Push Button Switch is released.

at all the Push Button Switches are shared with all the LEDs.

d to refer to the schematics for further details.

s the Push Button Switches:



Figure 2-4 Push Button Switches, LEDs and corresponding Headers

All the Push Button Switches (and hen

the pins of 8-pin header JP5. This fa

this 8-pin header as either external in

both. The user can keep all the Push

inputs to JP5 to use them as external

mode, whatever data is coming out o

corresponding pins of the JP5 header.

2.7 LED

This board contains eight Light Emittin

as user outputs. The CPLD outputs LO

turn OFF the LEDs. Figure 2-4 above s

Important Note:

It should be noted that all the LEDs a

The user is encouraged to refer to the

SW

5 S

W1

0 S

W6

S

W1

1

5

D9 D8

S

W8

D7 D6

S

W3

D5 D4

S

W7
D3 D2
JP

7

ce LEDs) are also mapped one-to-one with all

cility is provided to give the flexibility to use

put or external output or the combination of

Button switches released and give external

inputs to the CPLD. When used in the output

n the LEDs is straight away available on the

g Diodes (LEDs) (D2-D9), which can be used

W to turn ON the LEDs and outputs HIGH to

hows the LEDs.

re shared with all the Push Button Switches.

schematics for further details.

SW

2


8

All the LEDs (and hence Push Button Switches) are also mapped one-to-one with all

the pins of 8-pin header JP5. This facility is provided to give the flexibility to use

this 8-pin header as either external input or external output or the combination of

both. The user can keep all the Push Button switches released and give external

inputs to JP5 to use them as external inputs to the CPLD. When used in the output

mode, whatever data is coming out on the LEDs is straight away available on the

corresponding pins of the JP5 header.

2.8 7-Segment LED Display

This board contains two 7-segment LED displays (U6 & U8), which can be used as

user outputs. The CPLD board has common anode 7-segment LED displays on the

board hence the CPLD should output LOW to turn ON a particular segment and

output HIGH to turn OFF a particular segment.

Figure 2-5 below shows the two 7-segment LED displays that are on the CPLD

board.

Figure 2-5 7- Displays

Figure 2-6 below shows the segm

Figure 2-6 Segment identif

6

Segment LED

U8 U


ent mapping for the 7-segment LED displays.

ication of the 7-Segment LED Display



The board design is such that a 7-bit data bus (for Segments A-G) is shared

between the two 7-segment LED displays through separate transparent latches

74HC573 (U5 & U7) for each of the displays (U6 & U8 respectively). The latches

have active high Latch Enable signals. Hence the user should give a positive pulse

to latch the 7-bit display data corresponding to the segments A-G for the respective

7-segment LED displays.



3 CPLD BOARD DIAGNOSTIC SYSTEM

This section gives information about the CPLD Board Diagnostic System that is

embedded within the EPM3064 CPLD by default.

3.1 Overview

The EPM3064 CPLD by default contains a JAM file called

“CPLD_Board_Diagnostic_System.jam”. This file contains a system, which contains

all the peripherals that are integrated with the CPLD. The user can use this file to

diagnose the peripherals on the CPLD Board.

The CPLD Board Diagnostic System contains mainly 3 tests:

1. 7-Segment LED Display and LED Test

2. DIP Switch Test

3. Push Button Switch Test

The subsequent sections give details about each test that can be carried out using

this system.

Important Note:

All the displays (7-Segment LED Displays and LEDs) can be viewed as if they are

updated continuously at the half clock rate of the CPLD input clock frequency, i.e.,

if the CPLD Clock frequency is selected as 2 Hz, then the two 7-Segment LED

Displays and the LEDs can be viewed as if they are updated at 1 Hz rate. This is

because the data for one 7-Segment LED Display is updated in one clock cycle and

the data for the other 7-Segment LED Display is updated in the next consecutive

clock cycle. This holds true for all the tests.

CPLD Board Diagnostic System CPLD Board Diagnostic System Reference Manual


3.2 Selecting CPLD Board Diagnostic Test using DIP Switches

The user can select any test for the CPLD Board using DIP Switches. The first pins

of DIP Switches SW4 & SW9 act as the test select inputs to the CPLD. The following

table gives information about the test selection using DIP Switches.

Table 3-1 Diagnostic Test Selection using DIP Switches

Sr. No.

State of SW4.1 (1st pin of SW4)

State of SW9.1 (1st pin of SW9)

Selected Test

1. OFF (Logic High) OFF (Logic High) 7-Segment LED Display and LED Test 2. OFF (Logic High) ON (Logic Low) 7-Segment LED Display and LED Test 3. ON (Logic Low) OFF (Logic High) DIP Switch Test 4. ON (Logic Low) ON (Logic Low) Push Button Switch Test

3.3 CPLD Board Diagnostic Tests

This section gives information about all the Diagnostic Tests for the CPLD Board.

3.3.1 7-Segment LED Display and LED Test

The user can select 7-Segment LED Display Test and LED Test by keeping SW4.1

and SW9.1 in the OFF position (preferably) or by keeping SW4.1 OFF and SW9.1

ON.

In this test, the data corresponding to a continuously running 8-Bit counter is

displayed on the 7-Segment LED Displays and the last latched data on the LED bus

gets left rotated on the LED bus. Both of the display devices can be viewed as if

they are updated at the half clock rate of the CPLD input clock frequency.

So during this test if any segment of the 7-segment LED display is not working then

it can be tracked down by visual inspection of the counter running on the 7-

segment LED displays. The same holds true for the LEDs also. The LEDs display a

pattern that is continuously left shifting the last latched pattern on the LEDs. This

last latched pattern will vary with the test selected and the user will get more

familiar with that as soon as he/she understands the flow.

CPLD Board Diagnostic System Reference Manual CPLD Board Diagnostic System


3.3.2 DIP Switch Test

The user can select DIP Switch Test by keeping SW4.1 ON and SW9.1 in the OFF

position.

In this test, the data corresponding to SW4 is displayed on the 7-segment LED

display U8 and the data corresponding to SW9 is displayed on the 7-segment LED

display U6. Here each pin of the DIP switch is mapped one-to-one with the

segments on the 7-segment LED displays. If any switch is turned ON, the

corresponding mapped segment gets illuminated.

Table 3-2 shows the segment mapping of the DIP switch test.

Table 3-2 Segment mapping for the DIP Switch test

Sr. No. DIP.SW Display.Segment

1. SW4.2 U8.a 2. SW4.3 U8.b 3. SW4.4 U8.c 4. SW4.5 U8.d 5. SW4.6 U8.e 6. SW4.7 U8.f 7. SW4.8 U8.g

8. SW9.2 U6.a 9. SW9.3 U6.b 10. SW9.4 U6.c 11. SW9.5 U6.d 12. SW9.6 U6.e 13. SW9.7 U6.f 14. SW9.8 U6.g

Important Note:

It should be noted that SW4.1 and SW9.1 are used for the test selection purpose

and hence are not mapped to any segments of the 7-segment LED displays.

The 7-segment LED displays are verified in the first test. So it is made sure that

they are working properly. Now when a DIP switch is turned ON and corresponding

segment doesn’t get illuminated, this implies that something is wrong with the DIP

switch or CPLD since the input information doesn’t propagate to the output. In this

way both of the DIP switches can be verified.



If a valid hex digit is displayed on the 7-segment LED displays, then their

corresponding binary value is represented on the LEDs otherwise all the LEDs

remain turned ON (representing 0xF HEX value). The binary value corresponding to

the hex digit on the U8 display is represented on {D9, D7, D5, D3} LED column

with D9 representing the MSB. Similarly the binary value corresponding to the hex

digit on the U6 display is represented on {D8, D6, D4, D2} LED column with D8

representing the MSB.

Now if the 7-segment LED test mode is selected after this test, whatever data is

displayed on the LEDs gets shift rotated, while the 7-segment LED display shows

continuously running counter contents.

3.3.3 Push Button Switch Test

The user can select Push Button Switch Test by keeping SW4.1 and SW9.1 in the

ON position.

In this test, the data corresponding to {D9, D7, D5, D3} LED column is displayed

on the 7-segment LED display U8 and the data corresponding to {D8, D6, D4, D2}

LED column is displayed on the 7-segment LED display U6. Here each Push Button

switch is mapped one-to-one with the segments on the 7-segment LED displays. If

any Push Button switch is turned ON (pressed), the corresponding mapped

segment gets illuminated.

Table 3-3 below shows the segment mapping of the Push Button switch test.

Table 3-3 Segment mapping for the Push Button Switch test

Sr. No. Push Button Switch Display.Segment

1. SW11 U8.e 2. SW6 U8.d 3. SW10 U8.b 4. SW5 U8.a

5. SW8 U6.e 6. SW3 U6.d 7. SW7 U6.b 8. SW2 U6.a

CPLD Board Diagnostic System Reference Manual CPLD Board Diagnostic System


The 7-segment LED displays are verified in the first test. So it is made sure that

they are working properly. Now when a Push Button switch is turned ON (pressed)

and corresponding segment doesn’t get illuminated, this implies that something is

wrong with the Push Button switch or CPLD since the input information doesn’t

propagate to the output. In this way all the Push Button switches can be verified.

As the LEDs are shared with the Push Button switches, the LEDs remain turned OFF

during this test. Whenever a Push Button switch is pressed, the shared LED gets

illuminated as long as the Push Button switch is kept pressed (due to hardware

design).

Now if the 7-segment LED test mode is selected after this test, hex value 0x88 is

displayed on the LEDs and gets shift rotated, while the 7-segment LED display

shows continuously running counter contents.

3.4 Important Tips for using CPLD Board

The user can download any custom *.jam/*.jbc file generated for the

EPM3064 part using the JTAG download header. Sometimes if the JTAG

shared DIP Switches are kept ON then the programmer cannot access the

JTAG port of the CPLD and hence cannot program the CPLD (A Warning

message is displayed in the Quartus II software). To solve this issue, keep

the JTAG shared DIP Switches turned OFF.

The CPLD Board Diagnostic system does not have any reset input. But a

Power on reset module is designed in the CPLD Board Diagnostic System. So

all the user needs to do is select the input clock to the CPLD using JP1 and

apply power to the board. The system will get reset automatically. The reset

time depends upon the input clock frequency selected. Depending upon the

state of the SW4.1 & SW9.1, the system starts the selected test.

The CPLD Board Diagnostic System contains a counter, which is running

continuously. At power-up this counter gets reset and after that it is running

continuously, whether the 7-segment LED Display test is selected or not.

Hence the counter contents are updated continuously.



4 CPLD SIGNAL MAPPING

This section describes the mapping of each and every signal coming out of the

CPLD with all the peripherals and its corresponding pin-assignment.

4.1 Clock Signal

The mapping of the Clock signals for the CPLD Board is given in Table 4-1 below:

Table 4-1 Mapping of the Clock Signal

Sr. No. CPLD Pin CPLD Signal

Name Peripheral Shared

Peripheral Shared

Peripheral 1 43 Clock - - -

4.2 DIP Switch Signals

The mapping of the DIP Switch signals for the CPLD Board is given in Table 4-2

below:

Table 4-2 Mapping of the DIP Switch Signals

Sr. No.

CPLD Pin

CPLD Signal Name

Peripheral Shared Peripheral

Shared Peripheral

1. 40 DIP_SW_0 SW4.1 (DIP Switch 1) JP2.1 (Header) - 2. 41 DIP_SW_1 SW4.2 (DIP Switch 1) JP2.2 (Header) - 3. 44 DIP_SW_2 SW4.3 (DIP Switch 1) JP2.3 (Header) - 4. 1 DIP_SW_3 SW4.4 (DIP Switch 1) JP2.4 (Header) - 5. 2 DIP_SW_4 SW4.5 (DIP Switch 1) JP2.5 (Header) - 6. 4 DIP_SW_5 SW4.6 (DIP Switch 1) JP2.6 (Header) - 7. 5 DIP_SW_6 SW4.7 (DIP Switch 1) JP2.7 (Header) - 8. 6 DIP_SW_7 SW4.8 (DIP Switch 1) JP2.8 (Header) -

9. 7 TDI_DIP_SW_8 SW9.1 (DIP Switch 2) JP3.1 (Header) JP4.9 (JTAG_TDI) 10. 8 DIP_SW_9 SW9.2 (DIP Switch 2) JP3.2 (Header) - 11. 9 DIP_SW_10 SW9.3 (DIP Switch 2) JP3.3 (Header) - 12. 11 DIP_SW_11 SW9.4 (DIP Switch 2) JP3.4 (Header) - 13. 12 DIP_SW_12 SW9.5 (DIP Switch 2) JP3.5 (Header) - 14. 13 TMS_DIP_SW_13 SW9.6 (DIP Switch 2) JP3.6 (Header) JP4.5 (JTAG_TMS) 15. 32 TCK_DIP_SW_14 SW9.7 (DIP Switch 2) JP3.7 (Header) JP4.1 (JTAG_TCK) 16. 38 TDO_DIP_SW_15 SW9.8 (DIP Switch 2) JP3.8 (Header) JP4.3 (JTAG_TDO)

CPLD Signal Mapping CPLD Board Diagnostic System Reference Manual


4.3 Push Button Switch Signals

The mapping of the Push Button Switch signals for the CPLD Board is given in Table

4-3 below:

Table 4-3 Mapping of the Push Button Switch Signals

Sr. No.

CPLD Pin

CPLD Signal Name


Shared Peripheral

1. 18 LED_PB_SW_0 SW2 (PB Switch) JP5.1 (Header) D2 (LED) 2. 19 LED_PB_SW_1 SW5 (PB Switch) JP5.2 (Header) D3 (LED) 3. 20 LED_PB_SW_2 SW7 (PB Switch) JP5.3 (Header) D4 (LED) 4. 21 LED_PB_SW_3 SW10 (PB Switch) JP5.4 (Header) D5 (LED) 5. 24 LED_PB_SW_4 SW3 (PB Switch) JP5.5 (Header) D6 (LED) 6. 25 LED_PB_SW_5 SW6 (PB Switch) JP5.6 (Header) D7 (LED) 7. 26 LED_PB_SW_6 SW8 (PB Switch) JP5.7 (Header) D8 (LED) 8. 27 LED_PB_SW_7 SW11 (PB Switch) JP5.8 (Header) D9 (LED)

4.4 7-Segment LED Display Signals

The mapping of the 7-Segment LED Display signals for the CPLD Board is given in

Table 4-4 below:

Table 4-4 Mapping of the 7-Segment LED Display Signals

Sr. No.

CPLD Pin

CPLD Signal Name


Shared Peripheral

1. 31 SEG_DATA_0 U5.2 (Display Latch 1) U7.2 (Display Latch 2) - 2. 14 SEG_DATA_1 U5.3 (Display Latch 1) U7.3 (Display Latch 2) - 3. 33 SEG_DATA_2 U5.4 (Display Latch 1) U7.4 (Display Latch 2) - 4. 34 SEG_DATA_3 U5.5 (Display Latch 1) U7.5 (Display Latch 2) - 5. 37 SEG_DATA_4 U5.6 (Display Latch 1) U7.6 (Display Latch 2) - 6. 16 SEG_DATA_5 U5.7 (Display Latch 1) U7.7 (Display Latch 2) - 7. 39 SEG_DATA_6 U5.8 (Display Latch 1) U7.8 (Display Latch 2) - 8. 29 EN_DISP_1 U5.11 (Display Latch 1) - - 9. 28 EN_DISP_2 - U7.11 (Display Latch 2) -

5 REFERENCES

Entry Level Tool Schematics, System Level Solutions (INDIA) Pvt. Ltd.

Copyright©2004 System Level Solutions, Inc. (SLS) All rights reserved. SLS, An Embedded systems company, the stylized SLS logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of SLS in India and other countries. All other products or service names are the property of their respective holders. SLS products are protected under numerous U.S. and foreign patents and pending applications, mask working rights, and copyrights. SLS reserves the right to make changes to any products and services at any time without notice. SLS assumes no responsibility or liability arising out of the application or use of any information, products, or service described herein except as expressly agreed to in writing by SLS. SLS customers are advised to obtain the latest version of specifications before relying on any published information and before orders for products or services. CPLDBDSREFMNL1.0

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