CPRE 583 Reconfigurable Computing Lecture 3: Wed 9/1/2010 (Reconfigurable Computing Hardware)

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Hardware Iowa State University (Ames)

CPRE 583Reconfigurable Computing

Lecture 3: Wed 9/1/2010(Reconfigurable Computing Hardware)

Instructor: Dr. Phillip Jones([email protected])

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/

http://class.ece.iastate.edu/cpre583/


• Send me top 3 choices for topic for mini literary survey– PowerPoint tree due: Fri 9/17 by class, so try to have to

me by 9/16 night. My current plan is to summarize some of the classes findings during class.

– Final 5-10 page write up on your tree due: Fri 9/24 midnight.

Announcements/Reminders


• Logic

• Interconnect/Routing

• Optimized resources– Adders, Multipliers– Memory– System-on-chip building blocks

• Example Commercial FPGA structure

Overview


• Basic understanding of the major components that make up an FPGA device.

What you should learn


Basic FPGA Architectural Components

• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

CLB CLB CLB CLB

Configurable Logic Block(CLB)


Computational Fabric - LUT

4-LUT

Z LUT = Look up Table

00000001

11101111

ABCD Z

BCD

A

00000001

11101111

ABCD Z00

01

ANDZA

BCD

00000001

11101111

ABCD Z01

11

ORZA

BCD

X000X001X010

X101X110X111

ABCD Z010

011

B

2:1Mux

CD

Z10



4-LUT


BCD

A

How many 4-LUTs needed to OR 32-bits

Draw

32

1



4-LUT


BCD

A

How many 4-LUTs needed to OR 32-bits

Draw

32

1

4LUT

4LUT

4LUT

4 LUT4 LUT4 LUT4 LUT




4-LUT


BCD

A

How many 4-LUTs needed to AND 2-bits with the 32-bit OR

Draw

32

1

4LUT

4LUT

4LUT





4-LUT


BCD

A


Draw

32

1

4LUT

4LUT

4LUT





4-LUT


BCD

A


Draw

32

1

4LUT

4LUT

4LUT



0000000100100011010001010110011110001001101010111100110111101111

Write out the Truth tableABCD Z



4-LUT


BCD

A


Draw

32

1

4LUT

4LUT

4LUT



0000000100100011010001010110011110001001101010111100110111101111

000000

000000




4-LUT


BCD

A


Draw

32

1

4LUT

4LUT

4LUT



0000000100100011010001010110011110001001101010111100110111101111

0000000100000011




4-LUT


BCD

A

How could one build a 4-LUT?

000

001

1x16 Memory

16:1Mux

4ABCD

Z



4-LUT


BCD

A

How many different 4 input functions can a 4-LUT implement?

000

001

1x16 Memory

16:1Mux

4ABCD

Z

216 = 65536



4-LUT


BCD

A

How many different N input functions can a N-LUT implement?

000

001

1x16 Memory

16:1Mux

4ABCD

Z



4-LUT


BCD

A


000

001

1x16 Memory

16:1Mux

NABCD

Z



4-LUT


BCD

A


000

001

1x2N Memory

16:1Mux

NABCD

Z

216 =224=65536

N = 4

= 22N


Granularity of ComputationTrade-offs associated with LUT size

Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits

1024-bits

2-LUT

10-LUTMicroprocessor




1024-bits

2-LUT


4

3

3AB

op3




1024-bits

2-LUT


4

3

3AB

op3

4

3

3AB

op3

4

3

3AB

op3




1024-bits

2-LUT


4

3

3AB

op

3

4

3

3AB

op

3

3

3

3AB

op




1024-bits

2-LUT


4

3

3AB

op

3

4

3

3AB

op

3

4

3

3AB

op

3




1024-bits

2-LUT

10-LUT

Bit logic and constants




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)

A

B




1024-bits

2-LUT

10-LUT


(A and “1100”) or (B or “1000”)

A AND

OR

OR

1

0

B

4

4

It’s much worse, each 10-LUT only has one output

Area that wasrequired using

2-LUTS


• LUTs are fine for implementing any arbitrary combinational logic (output is ONLY a function of its inputs) function. But what about sequential logic (output is a function of input AND previous state information)?

Computational Fabric - DFF

4-LUT

ZBCD

A

Need Memory!!



4-LUT

Z(t)BCD

A

DFF

Z(t+1)

1/0

0/0 1 11 110 1101

1/0 0/0

1/1

0/0Start 1/0

Input/output

Detect the pattern “1101”

DFF = D Flip Flop



4-LUT

Z(t)BCD

A

DFF

Z(t+1)

Increase circuit performance (pipelining)

4-LUTBCD

A

DFF4-LUT

DFF

4-LUT

DFF

4-LUT

DFF

4 LUT delays per output

4-LUTBCD

A

DFF4-LUT

DFF

4-LUT

DFF

4-LUT

DFF

1 DFF delay per output

DFF = D Flip Flop


Need a mechanism to move results of computation around.

Communication: Interconnect & Routing

CLB

CLB

CLB

CLB

CLB

CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB




Nearest Neighbor:

CLB

CLB

CLB

CLB

CLB

CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB




CLB

Nearest Neighbor:

Segmented:

CLB

CLB

CLB

CLB

CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB




Nearest Neighbor:

Segmented:

Hierarchical:

CLB

CLB

CLB

CLB

CLB

CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB

CLB CLB CLB CLB CLB


LUTs + DFFs can implement any arbitrary digital logic. But not optimally (ASICs give make much better use of silicon area for Power, Speed, routing resources)• Arithmetic

– Add, Multiply• On chip memory• System on chip building blocks

– Processor, PCI-express, Gigabit Ethernet, ADC, etc.

Optimized Resources: Dedicated Logic



Carry Look Aheadc4

Carry in

Carry out

6-LUT

6-LUT

6-LUT

A3

B3

A2

B2

A1

B1

Sum 3

Sum 2

Sum 1

G1

P1

Sum1

CLB P2

Carry2 G2

CLB Sum2

A1

B1

A1

B1

A1B1

Carry1

Carry1

Carry1

A2 B2

Fast AdditionTwo output LUT

generate propagatelogic

Dedicated routingresources


Optimized Resources: Dedicated LogicEmbedded Memory

8

12

96 bits, 300 MHz



Dedicated memory

block

Embedded Memory8

12

18 Kbits, 550 MHz


Optimized Resources: Dedicated LogicMultiplication

Type # LUTs Latency SpeedLUT ~400 5 clks 380 MHz

Dedicated 18x18 Multiplier 0 3 clks 450 MHz

Virtex-5 (6-LUTs)

18x18 multiply

Very rough estimate of Silicon area comparison (assuming SX95 andLX110 have about the same die size)

6-LUT 6-LUT

6-LUT 6-LUT

18x18Multiplier

In other word you can replace one LUT based 18x18 multiplier With 100 dedicated 18x18 Multipliers!!!


Optimized Resources: Dedicated LogicProcessor

PowerPC hard-core MicroBlaze soft-core

• 500 MHz•Super scalor•Highspeed 2x5 switch fabric

• 250 MHz• Simple scalar


Optimized Resources: Dedicated LogicSystem on Chip

EthernetMAC

RAM

MotorPIDController

SensorAD

C

Sensor

DataBuffer

Dedicated LogicReconfigurable Logic

Matrix MultiplierCoprocessor

Also see Actel Fusion:http://www.actel.com/products/fusion/default.aspx

http://www.actel.com/products/fusion/default.aspx


Xilinx CLB Architecture• Virtex 5 FPGA User Guide

http://class.ece.iastate.edu/cpre583/ref/EDK/Virtex5_ug190.pdf


Questions/Comments/Concerns


• N-Lut, 3,4…6,…8-LUT– AND, XOR, NOT– Exercises

• How many 4-LUTs to OR 32 bits (draw)• How many 4-LUTs to AND 2 bits with the OR of

these 32 bits (draw)• Draw the truth table for the 4-LUT that gives the final

output– How could one implement a LUT (Memory + MUX)– How many ways can a 4-LUT be programmed– How many ways can a N-LUT be programmed

• Granularity trade-off: Functionality vs. propagation delay (2-LUT -> CPU), bit-level vs. datapath



• Enable building circuits that can store information (sequential circuits, state machines)

• Enables pipelining to increase operating frequency/ throughput



• Need a mechanism to move the results of a LUT to other LUTs.

• Island stale (Array of CB)– Nearest neighbor (paper on reconfigure arch that uses

this)• Not scalable (large delays, and uses logic elements for

routing?)– Segmented (different length for latency trade-off)

• Multi hop scales < O(N)?• Avoid using logic

– Hierarchical (good for apps with lots of local communication and little remote communication)

• Typical an FPGA silicon area will be 10% logic and 90% interconnect!!



• LUTs + DFFs can implement any arbitrary digital logic. But not optimally (ASICs give make much better use of silicon area for Power, Speed, routing resources)

• Arithmetic– Add, Mult

• On chip memory• System on chip building blocks

– Processor, PCI-express, Gigbit Ethernet, A/D

Optimized Resources: Hard Cores

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CPRE 583 Reconfigurable Computing Lecture 3: Wed 9/1/2010 (Reconfigurable Computing Hardware)

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