CPS 4150 CPS 4150 Computer Computer

OrganizationOrganizationFall 2006Fall 2006

Ching-Song Don WeiChing-Song Don Wei

IntroductionIntroduction• Computer hardware electronic

circuits, displays, magnetic and optical storage media, electromechanical equipment, and communication facilities.

• Compute architecture specification of an instruction set and the hardware units that implement the instructions.

1.1 Computer Types1.1 Computer Types• Desktop• Notebook• Workstation• Supercomputer• mainframe

1.2 Functional Unit1.2 Functional Unit• A computer consists of five

functionally independent main parts:– Input– Memory– Arithmetic and logic– Output– Control unit

1.2 Functional Unit1.2 Functional Unit

Figure 1.1. Basic functional units of a computer.

I/O

Output

Memory

Input andArithmetic

logic

Control

Processor

1.2 Functional Unit1.2 Functional Unit• Information handled by computer are:

– Instruction set• Govern transfer of information within a

computer as well as between the computer and its I/O devices

• Specify the arithmetic and logic operations to performed.

• Memory fetched by processor process

– Data• Numbers and encoded characters that are

used as operands by the instruction.

1.2 Functional Unit1.2 Functional Unit• Program compiler object program

1.2.1 Input Unit1.2.1 Input Unit• Key board• Trackball• Mouse• joysticks

1.2.2 Memory Unit1.2.2 Memory Unit• There are two classes of storage:

– Primary storage: fast memory that operates as electronic speeds. • Unit of word (n bits) is organized.• Address to access the word easily.• Word length of the computer = The number

of bits in each word.• Program must reside in the memory during

execution.

1.2.2 Memory Unit1.2.2 Memory Unit• Memory in which any location can be reached in a

short and fixed amount of time after specifying its address is called random-access memory (RAM).

• The time required to access one word is called the memory access time. (ns ~ 100 ns).

– Cache small and fast, tightly coupled with processor and contained on the same integrated circuit chip to achieve high performance.

– Main memory, larger and slower

– Secondary storage:• Magnetic disks, tape and CD-ROM

1.2.3 arithmetic and Logic 1.2.3 arithmetic and Logic UnitUnit

• Arithmetic and logic unit (ALU) performs operations

• Data (operands) are brought into the processor stored in registers.

• Each register can store one word of data. Its speed is faster than cache.

1.2.4 Output Unit1.2.4 Output Unit• Send processed result to the outside

world.– Printer

• Ink jet stream• Laser printer

– Graphic display (I/O)

1.2.5 Control Unit1.2.5 Control Unit• Coordinates the operations of

memory, arithmetic and logic, and I/O unit to store and process information and perform input and output operations.

• It uses timing signals to govern the data transfers between them, to determine when a given action is to take place.

1.2.5 Control Unit1.2.5 Control Unit• The computer accepts information in the

form of programs and data through an input unit and stores in the memory

• Information stored in the memory is fetched , under program control, into a arithmetic and logic unit, where it is processed.

• Processed information leaves the computer through an output unit.

• All activities inside the machine are directed by the control unit.

1.3 Basic Operational 1.3 Basic Operational ConceptsConcepts

• Add LOCA, RO

• In modern computers, memory access operation and ALU operation are performed separately for performance purpose.

• Load LOCA, R1• Add R1, R0

1.3 Basic Operational 1.3 Basic Operational ConceptsConcepts

Figure 1.2. Connections between the processor and the memory.

Processor

Memory

PC

IR

MDR

Control

ALUR

n 1-

R1

R0

MAR

n general purposeregisters

1.3 Basic Operational 1.3 Basic Operational ConceptsConcepts

• Instruction Register (IR): holds the instruction that is currently being executed.

• Program counter (PC): contains the address of next instruction to be executed.

• Memory address register (MAR): holds the address of the location to be accessed.

• Memory data register (MDR) contains the data to be written into or read out of the addressed location.

1.3 Basic Operational 1.3 Basic Operational ConceptsConcepts

• Normal execution of program may be preempted if some device requires urgent servicing such as interrupt.

• An interrupt is a request by an I/O device for service by processor.

• The processor provides the requested service by executing an appropriate interrupt-service routine.

1.4 Bus Structures1.4 Bus Structures

Figure 1.3. Single-bus structure.

MemoryInput Output Processor

1.4 Bus Structures1.4 Bus Structures• When a word of data is transferred

between units, all its bits are transferred in parallel.

• A group of lines that serves as a connecting path for several devices is called bus.

• The simplest way to interconnect functional units is to use a single bus.

1.4 Bus Structures1.4 Bus Structures• A efficient transfer mechanism that is not

constrained by the slow devices and that can be used to smooth out the differences in timing among processors, memories and external devices is using buffer registers which is a common approach.

• When a processor sends the encoded character over the bus the printer, it sends to the buffer which is an electronic registers and fast.

• Once the buffer is loaded, the printer can start printing without further intervention by the processor. The bus and processor are no longer needed and can be released for other activities.

1.5 Software1.5 Software• System software (CPS 4200):

– Operating System– Text Editor– Compiler, loader and linker– Utility programms

1.6 Performance1.6 Performance• The speed with which a computer

executes program is affected by the design of its hardware and its machining language instructions.

• C++ compiler machine language.

• Performance ~ (compiler + machine instruction set + hardware)

1.6 Performance1.6 Performance

Figure 1.4. User program and OS routine sharing of the processor.

Printer

Disk

Program

routinesOS

Timet 0 t 1 t 2 t 3 t 4 t 5

Figure 1.4. User program and OS routine sharing of the processor.

1.6 Performance1.6 Performance• t0 to t1, an OS routine initiates loading the

application program from disk to memory. Wait until the transfer is completed, and then passes execution control to the application program

• The total time required to execute the program in Figure 1.4 is t0 – t5 elapsed time. (Think about the efficient way of using OS for multitasking.)

1.6 Performance1.6 Performance• Processor time = OS routines time +

program time• Processor time ~ hardware + execution of

individual machine instruction.• Hardware processor + memory + bus• Using cache to minimize the movement of

instructions and data between the main memory and the processor.

1.6 Performance1.6 Performance

Mainmemory Processor

Bus

Cachememory

Figure 1.5. The processor cache.

1.6.1 Processor Clock1.6.1 Processor Clock• Clock cycle to execute a basic step

of a instruction• If the clock cycle is P, the clock rate,

R = 1/P• Cycle rate: cycle per second hertz

(Hz)• ~ Megahertz (MHz) to Gigahertz

(GHz)

1.6.2 Basic Performance 1.6.2 Basic Performance EquationEquation

• The program execution time T = (N X S)/R

Where T : the processor timeN : actual number of instruction executionS : the average number of basic steps

(each basic step is completed in one clock cycle) needed to execute one machine instruction

1.6.2 Basic Performance 1.6.2 Basic Performance EquationEquation

• N and S decreases and R increases to achieve high performance

• N is reduced if the source program is compiled into fewer machine instructions.

• S is reduced if instructions have small number of basic step.

• R is increased if a higher-frequency clock is used

1.6.2 Basic Performance 1.6.2 Basic Performance EquationEquation

• N,S,R are not independent.• Higher frequency may not mean

better performance because of different Ss.

1.6.3 Pipelining and 1.6.3 Pipelining and Superscalar Superscalar

Operation(9/7/2006)Operation(9/7/2006)• Overlapping the execution of successive

instructions, using a technique called pipelining

• If multiple pipelines are implemented in the processor, a higher degree of concurrency can be achieved. multiple functional units are used to create parallel paths through which different instructions can be executed in parallel.

1.6.4 Instruction Set: CISC 1.6.4 Instruction Set: CISC and RISCand RISC

• Simple instructions require a small number of basic steps to execute.N ↑ then S↓

• Complex instructions involve a large number of steps. S ↑ then N ↓

• Using pipelining, effective S 1, is sounds like CISC is better, but it is much easier to implement efficient pipelining in RISC.

1.6.6 Compiler1.6.6 Compiler• An optimizing compiler reduce N X

S total clock cycles to execute a program.

• It should be closely linked to the processor architecture for better performance.

1.6.7 Performance 1.6.7 Performance MeasurementMeasurement

• Benchmark program is used for computer community to adopt the idea of measuring computer performance.

• System Performance Evaluation Corporation (SPEC) selects and publishes representative programs for different application domains, together with test results for many commercially available computers.

• The reference machine is SPEC95 SUN SPARCstation 10/40, SPEC200 UltraSPARC workstation with 300 M-Hz UltraSPARC-Iii processor.

1.6.7 Performance 1.6.7 Performance MeasurementMeasurement

• SPEC rating = Running time on the reference computerRunning time on the computer under test

• Let SPECi be the rating for program i in the suite. The overall SPCE rating for the computer is given by

1.6.7 Performance 1.6.7 Performance MeasurementMeasurement

• SPEC rating = ( )1/n

Where n is the number of programs in the suits.

This a geometric mean of the results is computer in above equation.

1.6.7 Homework1.6.7 Homework

• Page 22, Problems#1.1, 1.2, 1.5, 1.6