CPSC 2105

Fall 2011

Questions

in Preparation

for the Final Exam

The final exam for this offering of the course will be

on Thursday, December 8, at 10:30 AM to 12:30 PM.

Material for the First Part of the Course (Quiz 1)

Hexadecimal Numbers

Convert the hexadecimal number 0xDE to unsigned decimal.

ANSWER:

0xD is decimal 13 and 0xE is decimal 14. 1316 + 14 = 208 + 14 = 222.

Convert the hexadecimal number 0xCAFE to unsigned decimal.

ANSWER:

162 = 256 and 163 = 4096

0xC is decimal 12, 0xA is decimal 10, 0xF is decimal 15, and 0xE is decimal 14.

0xCAFE is 124096 + 10256 + 1516 + 14

49152 + 2560 + 240 + 14 = 51,966.

More Hexadecimal Numbers

Convert the unsigned decimal value 47806 to hexadecimal.

ANSWER: This involves repeated division by 16,

with the remainders expressed as hexadecimal digits.

47806 / 16 is 2987 with remainder 14 hexadecimal E

2987 / 16 is 186 with remainder 11 hexadecimal B

186 / 16 is 11 with remainder 10 hexadecimal A

11 / 16 is 0 with remainder 11 hexadecimal B

Read bottom to top as 0xBABE.

Binary Numbers

Convert the hexadecimal number 0xCAFE BABE to binary.

ANSWER: Begin with the binary values of the hexadecimal digits.

A is 1010 D is 1101

B is 1011 E is 1100

C is 1100 F is 1111

CAFE BABE is C A F E B A B E

1100 1010 1111 1110 1011 1010 1011 1110

Convert the binary number 1011100101010010 to hexadecimal.

ANSWER: Break the bits into groups of four from the right.

1011100101010010 becomes 1011 1001 0101 0010

or B 9 5 2, thus 0xB952.

NOTE: 11101110101101 would be 11 1011 1010 1101

or 0011 1011 1010 1101 3BAD.

More Binary Numbers

Convert the following decimal numbers to binary numbers.

The numbers are unsigned. Use as many bits as necessary.

a) 102 b) 240

ANSWERS: a) 102 / 2 = 51 remainder = 0

51 / 2 = 25 remainder = 1

25 / 2 = 12 remainder = 1

12 / 2 = 6 remainder = 0

6 / 2 = 3 remainder = 0

3 / 2 = 1 remainder = 1

1 / 2 = 0 remainder = 1 1100110 or 110 0110 or 0x66

b) 240 / 2 = 120 remainder = 0

120 / 2 = 60 remainder = 0

60 / 2 = 30 remainder = 0

30 / 2 = 15 remainder = 0

15 / 2 = 7 remainder = 1

7 / 2 = 3 remainder = 1

3 / 2 = 1 remainder = 1

1 / 2 = 0 remainder = 1 1111 0000 0r 0xF0.

Still More Binary Numbers

Convert the following unsigned binary numbers to decimal numbers.

Use as many decimal digits as necessary.

a) 10111000 b) 1010101

ANSWERS:

Powers of 2: 20 = 1, 21 = 2, 22 = 4, 23 = 8, 24 = 16, 25 = 32, 26 = 64, 27 = 128

a) 1011 1000 is 127 + 026 + 125 + 124 + 123 + 022 + 021 + 020

or 1128 + 064 + 132 + 116 + 18 = 184

Check: In hexadecimal, the number is 0xB8, which is 1116 + 8 = 176 + 8 = 184

b) 1010101 is 126 + 025 + 124 + 023 + 122 + 021 + 120

or 164 + 032 + 116 + 08 + 14 + 02 + 11

or 64 + 16 + 4 + 1 = 85

Check: In hexadecimal, the number is 0x55, which is 516 + 5 = 80 + 5 = 85

Two’s Complement Integers and Memory Maps

Given the memory map from a byte–addressable memory.

Address 406 407 408 409 40A

Value 7F 2C 10 D4 32

What is the value of the 16–bit two’s complement integer stored at address 408

if the value is stored in big–endian format?

ANSWER:

In big–endian, the high–order byte is stored first, so that the hexadecimal

value of the integer is 0x10D4. Powers of 16: 1, 16, 256, 4096, etc.

The value is 14096 + 0256 + 1316 + 4 = 4096 + 208 + 4 = 4308.

Two’s Complement Integers and Memory Maps (Part 2)

Given the memory map from a byte–addressable memory.

Address 406 407 408 409 40A

Value 7F 2C 10 D4 32

What is the value of the 16–bit two’s complement integer stored at address 408

if the value is stored in little–endian format?

ANSWER:

In big–endian, the high–order byte is stored first, so that the hexadecimal

value of the integer is 0xD410.

Note that the high–order hexadecimal digit is greater than 7.

This indicates that the sign bit is set. Convert first to binary.

0xD410 is 1101 0100 0001 0000

One’s complement 0010 1011 1110 1111

Two’s complement 0010 1011 1111 0000 or 0x2BF0.

24096 + 11256 + 1516 = 8192 + 2816 + 240 = 11,248.

The answer is the negative number –11,248.

Packed Decimal Format

Given the memory map from a byte–addressable memory.

Address 406 407 408 409 40A

Value 07 2C 10 4D 32

a) What is the value of the 3–digit packed decimal stored at address 406?

Assume that the value is a whole number in big–endian form.

b) What is the value of the 3–digit packed decimal stored at address 408?

Assume that the value is a whole number in big–endian form.

ANSWER:

In big–endian form, the values are 072C and 104D.

072C represents the positive number 072 or just 72.

104D represents the negative number –104.

NOTE: In this form, the question must specify the number of digits stored.

More Packed Decimal

Give the packed decimal representations of the following decimal numbers.

a) 1024

b) –2048

c) –3.14159

d) 98.6

ANSWER: Packed decimal form does not store the decimal point.

Also, it requires an odd number of decimal digits.

a) 1024 has four digits, so it is extended to 01024, and stored as 01 02 4C.

b) –2048 has four digits, so it is extended to 02048, and stored as 02 04 8D.

c) –3.14159 is first stripped of the decimal point to become –314159.

It has six decimal digits, so it is extended to seven, as 0314159,

and stored as 03 14 15 9D.

d) 98.6 is stripped of the decimal to become 986, stored as 98 6C.

Floating–Point

Example: The Negative Number – 0.750

Step 1: The number is negative. The sign bit is S = 1.

Step 2: 0.750 = 1.5 0.50 = 1.5 2–1. The exponent is P = – 1.

Step 3: P + 127 = – 1 + 127 = 126. As an eight–bit number, this is 0111 1110.

Step 4: Convert 1.5 to binary. 1.5 = 1 + ½ = 1.12. The significand is 10000. To get the

significand, drop the leading “1.” from the number. Note that we do not extend the

significand to its full 23 bits, but only place a few zeroes after the last 1 in the string.

Step 5: Arrange the bits: Sign | Exponent | Significand

Sign Exponent Significand 1 0111 1110 1000 … 00

Step 6: Rearrange the bits

1011 1111 0100 0000 … etc.

Step 7: Write as 0xBF40. Extend to eight hex digits: 0xBF40 0000.

The trick with the significand works because it comprises the bits to the right of the

binary point. So, 10000 is the same as 1000 0000 0000 0000 0000 000.

Example in Reverse: 0x42E8 0000

Given the 32–bit number 0x42E8 0000, determine the value of the floating point number

represented if the format is IEEE–754 Single Precision. Just do the steps backwards.

Step 1: From left to right, convert all non–zero hexadecimal digits to binary.

If necessary, pad out with trailing zeroes to get at least ten binary bits.

4 2 E 8

0100 0010 1110 1000

Step 2: Rearrange the bits as 1 bit | 8 bits | the rest

Sign Exponent Significand

0 1000 0101 1101000

Step 3: Interpret the sign bit. S = 0; the number is non–negative.

Step 4: Interpret the exponent field. 1000 01012 = 128 + 4 + 1 = 133.

P + 127 = 133; P = 6.

Step 5: Extend and interpret the significand. Extend to 1.11012. Drop the trailing 0’s.

1.11012 = 1 + 1/2 + 1/4 + 1/16 = 1 13/16 = 1.8125

Example in Reverse: 0x42E8 0000 (continued)

Step 6: Evaluate the number.

I show three ways to compute the magnitude.

6a Just do the multiplication.

We have 1.8125 26 = 1.8125 64 = 116.0

6b Consider the fractional powers of 2. 1.11012 = 1 + 1/2 + 1/4 + 1/16, so

we have (1 + 1/2 + 1/4 + 1/16)64 = 64 + 32 + 16 + 4 = 116.0

6c The “binary” representation is 1.11012 26. Move the binary point

six places to the right to remove the exponent.

But first pad the right hand side of the significand to six bits.

The “binary” representation is 1.1101002 26.

This equals 111 0100.0 = 64 + 32 + 16 + 4 = 116.0

REMARK: Whenever the instructor gives more than one method to solve a problem,

the student should feel free to select one and ignore the others.

Consider the following memory map. All values are in hexadecimal.

The computer is byte addressable, using the big–endian format.

Address 408 409 40A 40B 40C

Value 41 53 43 49 49

What is the 5 character ASCII string stored at address 408?

ANSWER: We use the standard ASCII values.

0 1 2 3 4 5 6 7 8 9 A B C D E F

4 @ A B C D E F G H I J K L M N O

5 P Q R S T U V W X Y Z [ \ ] ^ _

0x41 is “A”, 0x53 is “S”, 0x43 is “C”, 0x49 is “I”. The string is “ASCII”.

Produce the truth-table for the Boolean function

G(A, B, C) = (AB + C)(A + BC).

ANSWER:

A B C AB BC AB + C A + BC G(A, B, C)

0 0 0 0 0 0 0 0

0 0 1 0 0 1 0 0

0 1 0 0 0 0 0 0

0 1 1 0 1 1 1 1

1 0 0 0 0 0 1 0

1 0 1 0 0 1 1 1

1 1 0 1 0 1 1 1

1 1 1 1 1 1 1 1

Produce the -list and -list representations of this function.

A B C F(A, B, C)

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

ANSWER:

The function has value 1 for rows 1, 2, 4, 5, and 7, so F(A, B, C) = (1, 2, 4, 5, 7)

The function has value 0 for rows 0, 3, and 6, so F(A, B, C) = (0, 3, 6).

Represent this function in SOP (Sum of Product) form.

A B C F(A, B, C)

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

ANSWER: The SOP is

Use two 2-input OR gates to make a 3-input OR gate. Show the design.

ANSWER:

Use a single 3-input OR gate to make a 2-input OR gate. Show the design.

ANSWER:

One solution doubles an input and the other connects the input to ground. Recall that

(X + Y + Y) = (X + Y), and that (X + Y + 0) = (X + Y).

Prove the following equality for Boolean variables X and Y by any valid

means you find convenient. Show all of your work.

YXYXYX

ANSWER: The easiest way to do this is to use a truth-table approach.

Begin Quiz 2 Review

A computer memory module is controlled by two signals:

Select#

R/W#

Show the signal settings for a read from memory and a write to memory.

Method:

In order to answer these questions, you must understand what each signal does?

Question: What values can the signal take?

Question: What is the meaning of the “#” on the signal name?

Question: What does “Select” mean?

Question: What does “R/W#” mean?

Answer:

A computer memory module is controlled by two signals:

Select#

R/W#

Show the signal settings for a read from memory and a write to memory.

What are the possible signal levels?

All signals are binary. They have two values: 0 and 1.

What is the significance of the “#” in the name?

It means that the signal is asserted low.

For Select#, it means that the module is selected when Select# = 0.

For R/W#, it means that memory is read by the CPU for R/W# = 1, and

memory is written by the CPU for R/W# = 0.

Read memory Select# = 0 and R/W# = 1

Write to memory Select# = 0 and R/W# = 0

a) A given CPU has a 2.5 GHz clock. What is its clock period?

b) Another CPU has a clock period of 2 nanoseconds.

What is its clock period.

Method:

In order to answer these questions, you should understand the following.

i) What do the terms MHz and GHz mean?

ii) What is the relationship between frequency and clock period?

Answer:

Each of MHz and GHz are units of frequency. The real unit of frequency

is “per second” or sec–1.

MHz is millions of cycles per second, technically million/sec or

million sec–1. A 1 MHz clock has one million pulses per second.

GHz denotes billions of cycles per second, technically billion sec–1.

Frequency and clock period are inverses of each other:

Frequency = 1 / clock period, and

Clock period = 1 / frequency.

a) Frequency = 2.5 GHz = 2.5109 sec–1.

Clock period = 1.0 / ( 2.5109 sec–1 ) = 1.0 / ( 2.5109 ) sec–1

= 0.410–9 sec = 0.4 nanoseconds = 400 picoseconds.

b) Clock period = 2.0 nanoseconds = 2.010–9 sec

Frequency = 1.0 / ( 2.010–9 sec ) = 0.510–9 sec–1

= 0.5 GHz = 500 MHz.

Draw a square wave clock and label its four main parts.

Two are signal levels and two are transitions between levels.

Method:

In order to answer this question, you must

i) Remember what the square–wave clock signal looks like.

ii) Remember the names of the parts of the square wave.

Answer:

Here is the diagram.

The names for the parts are: high (level), low (level),

rising edge, and falling edge.

The cycle time was not part of the question.

What is the difference between a clocked latch and a flip–flop?

Method:

To answer this question, one must recall the parts of the clock (discussed

above) and the basic definition of each of the two devices.

Answer:

Both the clocked latch and flip–flop are synchronous devices;

each is controlled by a clock signal and accepts input only

during a specific part of the clock.

A clocked latch is level triggered; it accepts input either when the clock

is low or when the clock is high.

A flip–flop is edge triggered; it accepts input either at a small time

around the rising edge of the clock or a small time around the trailing edge.

A JK flip–flop has a present state Q = 0.

What input is required if the next state is to be Q = 1?

Method:

To answer this one, you must recall the characteristic table for a JK flip–flop.

You must also understand what information a characteristic table

contains and how that information describes the activity of the flip–flop.

Answer:

The characteristic table for the JK flip–flop is as follows:

J K QNext

0 0 Q

0 1 0

1 0 1

1 1 Q’

The present state is Q = 0. The desired next state is QNext = 1.

Either of two inputs will do the job.

J = 1 K = 0 will force QNext = 1.

J = 1 K = 1 will force QNext = Q’ = 0’ = 1.

HINT: Also be able to answer this question for the D flip–flop.

A 1GB (230 byte) main memory is byte addressable.

This memory is built from modules and is 16–way, low–order interleaved.

a) How many address bits are required to address this memory?

b) How many memory modules are used in this memory?

c) How many address bits are used to select the module, and how many

address bits are used to select a byte within the selected module?

d) Which address bits select the module, and which go to every module?

e) If the cycle time for each module is 80 nanoseconds, what is the

effective cycle time for this memory?

Method:

This question has a number of parts. In order to answer this, you must know.

a) How the number of address bits determine the size of memory

that is addressable.

b) What it means for a memory to be N–way interleaved; here 16–way.

c) What it means for a memory to be low–order interleaved.

d) How low–order interleaving affects the cycle time.

Answer:

a) N bits in the address field will address 2N items.

This memory has 230 bytes, each of which is addressable.

This requires 30 address bits.

The actual number of address bits in the computer is not relevant here.

b) If a memory is N–way interleaved, it is built from N modules.

Here N = 16, so there are 16 memory modules in this memory.

It is almost always the case that N is a power of two; here N = 16 = 24.

c) There are 24 modules, so it requires 4 bits to select the module.

30 – 4 = 26, so 26 address bits go to each module to select

the byte within the module.

d) The 30 address bits are numbered 29 through 0.

By definition, low–order interleaving involves the use of the

low–order bits to select the module.

Here the four low–order bits select the module: A3A2A1A0.

The other 26 bits A29 through A4 select the byte within

the selected module.

e) For burst transfers, an N–way low–order interleaved memory

cuts the effective cycle time by a factor of N.

The module cycle time is 80 nanoseconds.

The effective memory cycle time is 80 / 16 = 5 nanoseconds.

NOTE: Other forms of memory interleaving do not display this speed–up.

For this reason, low–order interleaving is preferred.

This question concerns stacks. Consider the following sequence, where

each PUSH operation pushes the value onto the stack.

What value is POPped from the stack with the first POP?

PUSH 3

PUSH 5

PUSH 4

POP // What value is popped by this statement?

Method:

First, remember that a stack is a LIFO (Last In –First Out) data structure.

The details of stack implementation are important to CPSC 1302 and

CPSC 2108, but do not concern us for this course.

Answer:

The data structure is LIFO.

The last value PUSHed is 4. That is the value that is popped.

Here is more detail.

PUSH 3

TOP 3

PUSH 5

TOP 5

3

PUSH 4

TOP 4

5

3

POP // What value is popped by this statement?

List the basic data types used by the JVM for placing operands

onto the operand stack.

Method:

This depends on understanding the difference between the rich set of

types supported by the Java language and the much simpler set of

types supported by the Java Virtual Machine.

Answer:

There are only two types.

The 32–bit word

The 64–bit double word, which occupies two 32–bit

slots in each of the operand stack and local variable table.

Consider the following sequence of JVM operations.

What value is left on the top of the operand stack?

iconst_3

iconst_2

iconst_4

imul

iadd

Method:

This depends on understanding what each of the instructions does, especially

the arithmetic operators imul and iadd.

Answer:

Trace the operand stack through the execution of each instruction.

iconst_3 // Push the constant value 3 onto stack

Top 3

iconst_2 // Push the constant value 2 onto stack

Top 2

3

iconst_4 // Push the constant value 4 onto stack.

Top 4

2

3

imul // Pop two values, multiply, push result

Top 8

3

iadd // Pop two values, add, push result.

Top 11

Prior to the execution of the following fragment of JVM code,

the local variable array has the following status.

Location Value

0 15

1 22

2 67

Here is the fragment of JVM code. Specify the contents of the above

locations of the local variable array after this code is executed.

iload_0

iload_1

iadd

iconst_2

imul

istore_2

Method: This depends on understanding the differences between the

iconst_n, iload_n, and istore_n instructions.

Answer:

Trace the operand stack. At the start we have

Location 0: 15 Location 1: 22 Location 2: 67

iload_0 // Push the value in location 0

Top 15

iload_1 // Push the value in location 1

Top 22

15

iadd // Pop two, add, and push the sum

Top 37

iconst_2 // Push the constant value 2

Top 2

37

imul // Pop two, multiply, and push result

Top 74

istore_2 // Pop and store in array location 2

Location 0: 15 Location 1: 22 Location 2: 74

A computer memory system uses a main memory with 60 nanosecond

access time, fronted by a cache memory with 4 nanosecond access time. What is the

effective access time if

a) The hit ratio is 0.9?

b) The hit ratio is 0.99?

ANSWER: There is a problem with names here. For the cache scenario, we have

TP as the access time of the cache

TS as the access time of the primary memory.

The equation is TE = h4 + (1 – h)60.

a) h = 0.9 TE = 0.94 + (1 – 0.9)60 = 0.94 + 0.160 = 3.6 + 6.0 = 9.6

b) h = 0.99 TE = 0.994 + (1 – 0.99)60 = 0.994 + 0.0160 = 3.96 + 0.6 = 4.56

NOTE: Some students reversed the roles of primary and secondary memory.

The primary memory is always faster. The term “primary memory with

60 nanosecond access time” should have been “main memory with 60

nanosecond access time”, but that should not have caused confusion.