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CPU Design for Multiple Clock Cycles per instruction
{CPI > 1}
Be able to explain how an instruction is executed and the concept of datapaths and control
page 2
Where we are headed
• Single Cycle Problems:– clock cycle determined by instruction that takes the longest
time – what if we had a more complicated instruction like floating
point?– wasteful of area
• each functional unit is used only once per cycle (per instruction)• it may be possible to reduce functional units
• One Solution:– use a “smaller” cycle time– have different instructions take different numbers of cycles– a “multicycle” datapath
page 3
Multiple cycle data path
• Divide the instruction into components• Choose the clock cycle to accommodate the longest component
– We need some balance between the components to reduce wastage– Same approach carries over to pipeline architectures
• Every instruction divided into– Instruction fetch– Instruction decode and operand fetch– Execution, memory address computation or branch completion– Memory access or complete R-type instruction– Memory read completion
• Work towards fewer components– Must we have a PC - Adder and an ALU – what if these are in different cycles?– Single memory for instructions and data
• May need buffers (registers) for temp storage, e.g Instruction Register• Controls will be more complicated – determined by cycle and op code
page 4
• Finite state machines:– a set of states and – next state function (determined by current state and the input)– output function (determined by current state and possibly input)
– We’ll use a Moore machine (output based only on current state)
Review: finite state machines
Next-statefunction
Current state
Clock
Outputfunction
Nextstate
Outputs
Inputs
1998 Morgan Kaufmann Publishers
page 5
• Break up the instructions into steps, each step takes a cycle– balance the amount of work to be done– all cycles are of equal length– how to fix the length of a cycle?– restrict each cycle to use only one major functional unit
• At the end of a cycle– store values for use in later cycles (easiest thing to do)– introduce additional “internal” registers
Multicycle Approach
page 6
Multiple Cycle Approach
• Single memory – instruction + data• One ALU, instead of ALU + 2 Adders
– Eliminating adders saves cost – what are we adding?
• Add temp store registers at the functional unit output – save for use in later cycle– MDR, IR are added. Both values are indeed in the same clock cycle
– A, B, ALUOut are added
• Registers and multiplexers are less costly than adders• Overall savings!
page 7
Shiftleft 2
PC
Memory
MemData
Writedata
Mux
0
1
RegistersWriteregister
Writedata
Readdata 1
Readdata 2
Readregister 1
Readregister 2
Mux
0
1
Mux
0
1
4
Instruction[15–0]
Signextend
3216
Instruction[25–21]
Instruction[20–16]
Instruction[15–0]
Instructionregister
1 Mux
0
3
2
Mux
ALUresult
ALUZero
Memorydata
register
Instruction[15–11]
A
B
ALUOut
0
1
Address
Jump and Branch – PC update requires special consideration. 3 possibilities.• PC = PC + 4 during IF. Store directly into PC.• ALUOut contains the branch target when it is computed.• Pseudodirect address for jump instruction.
page 8
Control Signals
page 9
Controller and control lines
page 10
• Instruction Fetch
• Instruction Decode and Register Fetch
• Execution, Memory Address Computation, or Branch Completion
• Memory Access or R-type instruction completion
• Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
Five Execution Steps
1998 Morgan Kaufmann Publishers
page 11
• Use PC to get instruction and put it in the Instruction Register.• Increment the PC by 4 and put the result back in the PC.• Can be described succinctly using RTL "Register-Transfer
Language"IR <= Memory[PC];PC <= PC + 4;
Can we figure out the values of the control signals?– Assert MemRead & IRWrite, IorD=0 (PC is source address)
– PC+4: ALUSrcA=0; ALUSrcB=01; ALUOp=00
– Storing in PC: PCSource=00, Assert PCWrite
What is the advantage of updating the PC now?– Value computed in parallel with Instruction Access.
Step 1: Instruction Fetch
page 12
• Read registers rs and rt in case we need them
• Compute the branch address in case the instruction is a branch
{Potentially wasted effort vs saving cycles}
• RTL:A <= Reg[IR[25:21]];B <= Reg[IR[20:16]];ALUOut <=PC+(sign-extend(IR[15:0])<< 2);
• We aren't setting any control lines based on the instruction type – instruction is being decoded in the control logic – we do not know the type
before ID & RF starts
Step 2: Instruction Decode and Register Fetch
page 13
• ALU is performing one of three functions, based on instruction type
• Memory Reference:ALUOut <= A + sign-extend(IR[15:0]);
• R-type:ALUOut <= A op B;
• Branch:if (A==B) PC <= ALUOut;
• Jump:
PC <= PC[31:28]||(IR[25:0]<<2)
Step 3: Execution, Compute Effective Address or Branch Completion
page 14
• Loads and stores access memory
MDR <= Memory[ALUOut];orMemory[ALUOut] <= B;
• R-type instructions finish
Reg[IR[15:11]] <= ALUOut;
The write takes place at the end of the cycle on the falling edge
Step 4: R-type or memory-access
page 15
• Load
Reg[IR[20:16]]<= MDR;
What about all the other instructions?
Step 5: Write-back step
1998 Morgan Kaufmann Publishers
page 16
Summary:
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction for branches
Action for jumps
Instruction fetch IR <= Memory[PC]PC <= PC + 4
Instruction A <= Reg [IR[25:21]]decode/register fetch B <= Reg [IR[20:16]]
ALUOut <= PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut <= A op B ALUOut <= A + sign-extend if (A ==B) then PC <= PC [31:28] computation, branch/ (IR[15:0]) PC <= ALUOut ||(IR[25:0]<<2)jump completion
Memory access or R-type Reg [IR[15:11]] <= Load: MDR <= Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] <= B
Memory read completion Load: Reg[IR[20:16]] <= MDR
page 17
• How many cycles will it take to execute this code?
lw $t2, 0($t3)lw $t3, 4($t3)beq $t2, $t3, Label #assume notadd $t5, $t2, $t3sw $t5, 8($t3)
Label:...• What is going on during the 8th cycle of execution?• In what cycle does the actual addition of $t2 and $t3 take place?
Simple Questions
lw: 5 cycles; beq: 3 cycles; add: 4cycles; sw: 4 cycleslw: IF, ID, MemAddrCompute, MemAccess, WB
page 18
• Value of control signals is dependent upon:– what instruction is being executed– which step is being performed: clock cycle related
• Use the information we’ve accumulated to specify a finite state machine– specify the finite state machine graphically, or– use microprogramming
• Implementation can be derived from specification
Implementing the Control
page 19
High Level View of Control System
Fig 5.31/Third Edition
page 20
IF & ID cycles
Fig 5.32/Third Edition
page 21
FSM for Memory-Reference Instruction
Fig 5.33/Third Edition
page 22
R-type Instruction
Fig 5.34/Third Edition
page 23
Branch & Jump
Fig 5.36/Third Edition
page 24
How many state bits will we need?
Graphical Specification of FSM
PCWritePCSource = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond
PCSource = 01
ALUSrcA =1ALUSrcB = 00ALUOp= 10
RegDst = 1RegWrite
MemtoReg = 0
MemWriteIorD = 1
MemReadIorD = 1
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst = 0RegWrite
MemtoReg = 1
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
MemReadALUSrcA = 0
IorD = 0IRWrite
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
Instruction fetchInstruction decode/
register fetch
Jumpcompletion
BranchcompletionExecution
Memory addresscomputation
Memoryaccess
Memoryaccess R-type completion
Write-back step
(Op = 'LW') or (Op = 'SW') (Op = R-type)
(Op
= 'B
EQ')
(Op
= 'J
')
(Op = 'SW
')
(Op
= 'L
W')
4
01
9862
753
Start
1998 Morgan Kaufmann Publishers
page 25
• Implementation:
Finite State Machine for Control
PCWrite
PCWriteCond
IorD
MemtoReg
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
NS3NS2NS1NS0
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
State register
IRWrite
MemRead
MemWrite
Instruction registeropcode field
Outputs
Control logic
Inputs
1998 Morgan Kaufmann Publishers
page 26
PLA Implementation• If I picked a horizontal or vertical line could you explain it?
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
IorD
IRWrite
MemReadMemWrite
PCWritePCWriteCond
MemtoRegPCSource1
ALUOp1
ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0
ALUSrcB1ALUOp0
PCSource0
1998 Morgan Kaufmann Publishers
page 27
• ROM = "Read Only Memory"– values of memory locations are fixed ahead of time
• A ROM can be used to implement a truth table– if the address is m-bits, we can address 2m entries in the ROM.– our outputs are the bits of data that the address points to.
m is the "height", and n is the "width"
ROM Implementation
m n
0 0 0 0 0 1 10 0 1 1 1 0 00 1 0 1 1 0 00 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 11 1 0 0 1 1 01 1 1 0 1 1 1
1998 Morgan Kaufmann Publishers
page 28
• How many inputs are there?6 bits for opcode, 4 bits for state = 10 address
lines(i.e., 210 = 1024 different addresses)
• How many outputs are there?16 datapath-control outputs, 4 state bits = 20
outputs• ROM is 210 x 20 = 20K bits (and a rather unusual
size)• Rather wasteful, since for lots of the entries, the
outputs are the same
ROM Implementation
1998 Morgan Kaufmann Publishers
page 29
• Break up the table into two parts
— 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
— 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
— Total: 4.3K bits of ROM
• PLA is much smaller
— can share product terms
— only need entries that produce an active output
— can take into account don't cares
• Size is (#inputs #product-terms) + (#outputs #product-terms)
For this example = (10x17)+(20x17) = 460 PLA cells
• PLA cells usually about the size of a ROM cell (slightly bigger)
ROM vs PLA
1998 Morgan Kaufmann Publishers
page 30
Processor design review
• Single clock cycle instructions (CPI = 1)– Clock cycle is longer– Designing for the worst case
• Multiple clock cycles per instruction– Divided each instruction into components– Tried for balance among the functions– Better performance ?
• Some instructions take a little longer.
• Some instructions take fewer cycles than others.
• On the average we have improved performance
page 31
Design process
• Determine datapath requirements– Pick an instruction (sometimes one instruction can represent an entire class,
e.g. R-type)– Determine the datapath required for execution of the instruction– Determine the controls required for the instruction– Find the data path required for all the instructions– Find the shared path requirements
• One approach: develop an input – output matrix• Find destinations that have more than one input• Insert multiplexers where necessary
• Determine control requirements– CPI = 1
• Controls are controlled by opcode
– CPI > 1• Controls are controlled by opcode and system state• Finite State Machine
– Hardwired (PLA) or Software (Microprgrammed) implementation
page 32
Interrupts, exceptions
• Interrupt vs exception– Interrupt: External – I/O device request– Exception: Internal – OS calls, arithmetic overflow
• Interrupts are external hardware events– Raise an interrupt (hardware)– Wait to complete the current instruction– Determine the source of the interrupt– Save the return address– Transfer to relevant Interrupt Service Routine
• Save the registers that may change• Execute the program
– Can this be interrupted?
• Restore the registers• Return to execution of the program
page 33
Exceptions
• Exceptions are software driven– Overflow in an arithmetic instruction– Memory access yields an undefined instruction
• MIPS exception handling– Registers
• Stores address of the problem instruction in EPC – Exception PC
• Store the cause of the exception in the Cause Register– Cause low order bit = 0 (undefined instruction)– Cause low order bit = 1 (arithmetic overflow)
• Additional control signals – IntCause, EPCWrite and CauseWrite
– Transfer control to specified location in OS• OS terminates program or continues processing
page 34
Multicycle Datapath with Exception Handling
Fig 5.39/Third Edition
page 35
Exception handling
Fig 5.40/Third Edition