158 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 2 , FEBRUARY 1988

Critical Area and Critical Levels Calculation in 1.C. Yield Modeling

SOPHIE GANDEMER, BERNARD C. TREMINTIN, AND JEAN-JACQUES CHARLOT

Abstract-This paper proposes a method to determine the critical levels in I.C. yield modeling. As a mixed Poisson statistic appears to give the best fit to our data, we apply it a t each photomask level, and within a level we cut the total area into separate areas defined by their pattern width and spacing ranges. Taking into account the fact that the defect density distribution is a function of defect size, we show how to build a simple model starting from the area distribution per level calculated using a design rule checker (DRC) program and the defect distribution curves obtained by visual counting on a microscope. The method presented in this paper is an easy way to calculate the critical technological coefficients to be applied on a product and a given tech- nology. It could be easily extended to different yield equations without problem. As we used defect density with defect size distribution curves to determine the critical levels, it was important not to have variation of the critical level coefficients with defect density. The paper shows that for a very large range of defect density, the critical level coeffi- cients vary very slowly and enable the method to he applicable to different wafer fabrication environments.

I . INTRODUCTION REDICTION of integrated-circuit manufacturing yield P has become an economic necessity requiring ever more

precise models. In that attempt, the understanding of the level and area sensitivity to defect density and defect sizes appears very important. Usually yield models are derived from mixed Poisson statistics as described by Murphy [ 11. The major differences between models come from whether and how the defect density distribution takes into account defect clustering on wafers. The currently used model pa- rameters (susceptible area, mean defect density, and num- ber of critical level steps in a technology) are fitted to the yield data without precise attention to design rules or de- fect density distribution with defect size. This paper de- scribes a way to take into account the sensitivity of the layout of any circuit to the defect size in a given technol- ogy.

We develop our analysis from the following remarks:

1 ) It is possible to define a yield at every masking step;

2) At every masking step, the yield may be calculated the net yield is the product of step yields.

Manuscript received April 23, 1987; revised September 14, 1987. S . Gandemer is with Matra-Harris-Semiconducteurs, Route de Gachet,

BP 942, 44075 Nantes, France, and with the Ecole Nationale Suptrieure des TtlCcommunications, 46 rue Barrault, 75634 Paris Cedex 13, France.

B. C. Tremintin is with Matra-Harris-Semiconducteurs, Route de Gachet, BP 942, 44075 Nantes, France.

J . - J . Charlot is with the Ecole Nationale SupCrieure des TClCcommuni- cations, 46 rue Barrault, 75634 Paris Cedex 13, France.

IEEE Log Number 8718088.

with areas representing a partition of the total area; each area is defined by the patterns included in it: their width is comprised between two limits.

3 ) Small patterns are more sensitive to defects. 4) Defect density depends on defect size.

These remarks are developed in the following sections of the paper. In Section 11, we present the yield model that is going to be used; details on partitioned areas cal- culations at each level and critical coefficient calculations are given. Section I11 describes the experimental proce- dure we take for partitioned areas extraction and for de- fect counting at every level. In Section IV the defect counting and partitioned areas extraction are used for cal- culation on three different circuits.

11. THEORETICAL A. General Model Equations

Mixed Poisson statistics [ I ] are based on the fact that the defects are distributed according to some distribution functionf( A ) , where h is the defect density per unit area. The expression for the yield is given by the integral over the distribution

Y = J e - f ( ( X ) dX 0

where A is the die susceptible area.

defect density distribution Stapper [2] assumed the gamma approximation for the

where ab = X is the mean value of defect density and ab2 = var ( A ) is the defect density variance. Therefore, (1) can be written as

( 3 )

A large number of distribution functions can be fitted by (2) using a and b parameters. As we choose a = I and b = X, the distribution function becomes

f ( 4 = exp ( - W ) / X (4) which fits with the data measured on several levels on our wafers. Fig. 1 is an example of the defect density we have obtained on one specific level. In these conditions, the

0018-9383/88/0200-0158$01 .OO O 1988 IEEE

GANDEMER ef a / . : CRITICAL AREA AND LEVELS CALCULATION IN YIELD MODELING I59

D e f e c t Density

Fig. I . Experimental distribution of the defect density distribution expo- nential shape for one level.

yield equation becomes

( 5 ) 1

( 1 + A X ) ' Y = Equation (5) takes into account the clustering effect we have on our wafers and the yield degradation due to ran- dom defects. Other defects such as mask defects, scratches, misalignments, etc., have to be taken into ac- count through another yield equation that will give an overall yield equation

YO (1 + A X )

Y =

where Yo is the parametric yield and will not be consid- ered here. For each process masking step, ( 5 ) will be ap- plied to specific areas (as defined later) of every mask.

B. Partitioned Areas Calculations

Applying (5) to a specific level i will result in the fol- lowing equation:

(7) 1 y. =

(1 + A h i ) where is the yield at level i, A, is the mean defect den- sity at that level, and A is the susceptible chip area. The product A h , is the average number of defects at level i. In order to take into account the defect size distribution at any level, the mask surface is partitioned into areas that are sensitive to a minimal defect size: the partitioned area a,, is defined as the area where all pattern geometries are included between two limits of size. These calculations have been made for pattern widths as well as pattern spac- ings. Every area subcomponent arJ will be sensitive to a given defect density A,,, which depends on the minimum pattern size. Under these conditions, the average number of potentially fatal defects is given by

n

Ahi = c aSihsi s = I

with n

C asJ = A T (9) 5 = I

where AT is the chip area and the real defect density determined by defect counting on wafers. The level i yield can be expressed as

C. Critical Levels Calculation The defect size distribution usually found in the litera-

ture [2]-[4] appears on Fig. 2. Fig. 2(a) is the analytic curve representation while Fig. 2(b) is the discrete one. The discrete curve ranges are defined to be the same as the partitioned area ranges. In Fig. 3 the partition in dis- crete areas of an area subcomponent is shown as an ex- ample. On these figures, the mean defect density at one level is given by

Qi

hi = d i ( x ) dx = c d : (s ) . (11) S

The die area is given by

A T = 3 a , ( w ) dw = c a,(s) . (12) 0 s

Here, the discrete partition is made with the variable called s. In order to calculate the hSi defect density, we have to consider that a given area subcomponent will be sensitive to all defects the size of which starts from the minimum pattern dimension, which gives

n

A,; = c d,!(s). (13) S

Fig. 4 is the A,, representation. The important thing to notice here is the fact that the mean defect density on a given level is only applied on a reduced part of the mask patterns. At that step in the calculation, it would be pos- sible to implement a more accurate model, as is done in [6]. In that paper the calculation of the probability that a size x defect is killer on a multiple pattern of width x1 is given, The default probability for multiple patterns of several sizes is drawn in Fig. 5 in comparison with the step probability we used in our calculation (curve c com- pared to curves a and b ) . For an S ( x l , x2) area subcom- ponent, we should have used a trade-off between the prob- abilities for a conductor pattern of width x, and x 2 (curves a and b ) . Using curve c gives us a worst case solution but will simplify all the equations. It will lead us to the crit- ical coefficient calculation. Additionally, it will be pos- sible to show that these coefficients are not very sensitive to the defect density or to the default probability per pat- tern size we used. Critical coefficients are introduced in our equations as we want to be able to make calculations

160 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 2, FEBRUARY 1988

A d l l X ) / (a) (b) where AT is the total die area. Using (10) and (14) leads

to the ai equation

(15) )

d'ils)iph , log ( 1 + s:l C asiXsi

a. = > > log (1 + &hi) .

1 5 10 x I 1 2 n s D e f e c t size

(em) Fig. 2. Defect size distribution: (a) Analytic representation. (b) Discrete

representation.

' l i 5 10 w I 1 2 n s Width (em)

Fig. 3. Mask surface distribution: (a) Analytic representation. (b) Discrete representation.

Fig. 4. Distribution of defect density applicable to each area subcompo- nent.

F a u l t P r o b a b i l i t y

D e f e c t s i z e X

Fig. 5 . Fault probability functions: (a) Multipattern x , width fault proba- bility function. (b) Multipattern x 2 width fault probability function. (c) Step fault probability function.

with the total die area A,. Equations (7) and (10) give the yield per level

1 - - 1 y. = [ ( 1 + Ahi) n

1 + C asiXsi s = l

Under these conditions, it will be possible to calculate the die yield as the product of the yields per level

Another simple way to calculate the critical coefficients is to use the same mean defect density distribution at each level

/ 1 \ " I 1

s = I

where X is the mean defect density for a given process at each level and A, is the mean defect density value de- pending on defect size. Using (16) and (17) the die yield will be given by

/ 4 \ "

where

a = c ai. i

We will show in Section I11 that using (15) or (17) to calculate ai gives the same result since ai are slightly sen- sitive to the X i s variations. So it will be possible to cal- culate the critical coefficients using (15) and use them in (16) or (18) for yield calculation.

111. EXPERIMENTAL PROCEDURE A. Partitioned Area Calculations on Three Different Products

Area subcomponents have been distributed within each level so that patterns inside the former have the same size limits. Distribution calculations have been made for pat- tern width as well as spacing between patterns. The total mask surface is then partitioned into areas that are sensi- tive to a minimal size defect. We have divided the surface into S1, S2, S3, and S4 areas so that

S1 0.0 pm < x I 2.5 pm S2 2.5 pm < x I 5.0 pm S3 5.0 pm < x I 10.0 pm S4 10.0pm < x

Using a critical coefficient ai we express the level yield

(14)

S2 1s sensitive to defects greater than 2.5 pm, S3 to 5 pm, and S4 to 10 pm. We chose these limits to maintain a homogeneous defect number for each area subcompo- nent because of the 1 / x 3 distribution of defect density. It

1

GANDEMER er a / . : CRITICAL AREA AND LEVELS CALCULATION IN YIELD MODELING 161

I I I 0 I I I

Start ++ Undersize ++ Oversize ++ Subtraction di aqram 1 pm 1 pm from the start

diagram

Fig. 6 . Method for determining region width of less than 2 pm.

TABLE I DRC COMMANDS AND RESULTS OBTAINED ON POLY1 LEVEL FOR PATTERN SPACINGS

OUTPUT /FIG. I IREF. DRC CORWD I FILE i RESULTS I CREATED I INPUT LAYER

None I la i I [ POLY1 I The program uses I patterns I BULK i Total silicon area Total area i the POLYl layer I i 1 The pg oversizes I

SIZE POLYl BY 2.51 81 I POLYl patterns by I 2.5pm and stores I I 1 the results i n 81 I

None

I The pq undersizes 1 SIZE B1 BY -2.51 B2 I all B1 patterns by1

I 2.5pm and stores 1 I I the results in 82 I None

i NOT B2 POLYl I LS3

I I

The pg subtracts [ Nb of polygons [ POLY1 patterns I and area of I 7d from 82 patterns I spacings less I

I than 5pm I i

SIZE B2 BY 5 1 B 3

I all 8 2 patterns by None The pg oversizes

5pm and stores the results in 8 3 I i The pq undersizes I all 8 3 patterns by None 5pm and s t o r e s the1 results in 84 I

NOT BULK 8 4 I ZS1 I I

The pq subtracts Nb of polygons 82 patterns from I and area of spa-I 7c 84 patterns cings comprised I

I betw. 5 and 10pml The pg subtracts Nb of polygons 1 8 4 patterns from I and area of I BULK patterns I spacings greater1 7b

I I

I than 10pm I

is clear when considering, for example, a 5-pm defect within a 5-pm-wide line (or within a 5-pm spacing be- tween two lines) that a metal cut (or a bridging) may be created.

We use a design rule checker (DRC) program to parti- tion each level mask surface into more or less critical sur- faces. This program uses geometric mask information re- corded on a CALMA tape. We use UNDERSIZE and OVERSIZE functions and such logical program functions as AND and NOT.

A 1-pm UNDERSIZE makes a 1-pm side reduction on all masking level figures; thus, if a pattern is less than 2 pm wide, it disappears. Then a 1-pm OVERSIZE causes a 1-pm increase on all figure sides. All lines less than 2 pm wide have disappeared. By subtracting from the starting figure

we are left with a surface of lines less than 2 pm wide (Fig. 6 ) .

We begin with an OVERSIZE to carry out the same op- eration on spacings so that the patterns will be in contact if the spacings are too narrow. Next, using an UNDERSIZE, the narrow spacings are transformed into full lines.

The necessary DRC commands we have used and the results obtained at each step are given in Table I for pat- tern spacings and Table I1 for pattern widths. To illustrate this, patterns of four memory cells as represented in Fig. 7 for level POLYl will be treated as an example. The impact of the logical operations performed are shown on Fig. 7(b) to (d) for pattern spacings and Fig. 7(e) and (8) for pattern widths. Following the program execution in Table I or I1 shows that we begin by storing the circuit

162

SIZE POLYl BY -5

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35, NO. 2, FEBRUARY 1988

I t h e POLYl l a y e r p a t t e r n s

BULK T o t a l s i l i c o n a r e 2

The pq u n d e r s i z e s

by 5 p m and s t o r e s t h e r e s u l t s in A 1

The pg o v e r s i z e s

A 1 a l l POLYl p a t t e r n s

TABLE I1 DRC COMMANDS AND RESULTS OBTAINED ON POLY1 LEVEL FOR PATTERN WIDTHS

SIZE A 1 BY 5 I A2 I

DRC COHRAND RESULTS

a l l A 1 p a t t e r n s by 5 p m and s t o r e s t h e r e s u l t s i n A2

AND poLyl A2 i m1 1 The pq a d d s POLYl a n d A2 p a t t e r n s I I

i The pg s u b t r a c t s I A3 1 E W 1 p a t t e r n s f rom NOT POLYl Z W 1 I POLY1 p a t t e r n s

A4

A5

The pg u n d e r s i z e s a l l A3 p a t t e r n s by 2.5pm and s t o r e s t h e r e s u l t s i n A 4

The pq o v e r s i z e s a l l A 4 p a t t e r n s by 2.5pm and s t o r e s t h e r e s u l t s i n A 5

I Iw2 AND A3 A5 The pg a d d s A3 and A5 p a t t e r n s i The pg s u b t r a c t s 1 A3 p a t t e r n s

i NOT A3 ZW2 I CW3 1 ZW2 p a t t e r n s f rom

I I

OUTPUT

T o t a l a r e a

Nb o f p o l y g o n s a n d a r e a of I 7e l i n e s g r e a t e r o r ( e q u a l t o 10pm I

I

I None v None I

-----A- None

Nb o f p o l y g o n s

l i n e s c o m p r i s e d 1 betw 5 and 1 0 p m l

Nb of p o l y g o n s a n d a r e a of I 7 9 l i n e s l e s s t h a n I

and a r e a of I 7 f _____+__

5pm I

layout patterns (POLY 1 level on this example) taking into account the actual pattern dimensions on silicon (other- wise it will be necessary to size that level before the par- titioning). The silicon surface also has to be stored as a reference for the calculation of the less sensitive areas ( > 10 pm); this bulk silicon surface may be the die area or any specific area we are looking for (in this example it will be the area occupied by four memory cells).

The basic principle for each area subcomponent is that doing an UNDERSIZE followed by the same OVERSIZE makes the pattern widths smaller or equal to the double-sizing factor to disappear. And, doing an OVERSIZE followed by the same UNDERSIZE makes the pattern spacings smaller or equal to the double-sizing factor to be transformed into full lines. In order to select the proper areas, we start by the smaller patterns for spacings and the greater patterns for widths; at every step we eliminate the patterns from the files.

In Table I, the first sizing is performed on the POLYl level file, the second sizing is performed on the B2 file, which is the POLY 1 level with the spacings smaller than 5 pm transformed into full lines. In the logical operation sequence, the NOT is the subtraction of one level from another. That operation is used between B2 and POLY 1 , B4 and B2, and BULK and B4. The corresponding cre-

ated files C S1, C S2, and C S 3 are given in Fig. 7(b), (c), and (d), respectively. The program output gives di- rectly the number of polygons and the corresponding area, which is the interesting figure for us. The same calcula- tions are carried out for pattern widths as shown in Table 11. The area subcomponents C W1, C W2, and C W3 cre- ated are shown on Fig. 7(e), (f), and (g), respectively.

All these calculations have to be done at every level and for pattern widths and spacings. It is thus possible to par- tition the total surface of each level in order to compare them. The DRC program has been used to determine sur- faces on three different circuits. The circuits were fabri- cated using the following CMOS technologies:

1 . 2K X 8 Memory (2.5-pm technology, double poly, single metal)

2. 16K X 1 Memory (1.6-pm technology, double poly, single metal)

3. Microprocessor 80C5 1 ( 1.6-pm technology, sin- gle poly, single metal ).

B. Defect Counting

We have counted defects after each photolithography plus etch step and taken data from three products and technologies from two different manufacturing lines as

GANDEMER et a / . : CRITICAL AREA AND LEVELS CALCULATION IN YIELD MODELING 163

P- IMPLA~T:

NITRIDE :

P well area f o r implantation

Nitride mask etch

BURIED APS:

POLY2:

Buried contacts mask etch

Second polysilicon mask etch

PADS : Passivation layer mask etch

I I s4 I s3 I s2 S1

N+ IMP P+ IMP B.APS POLY2 CONT METAL PADS

94.19 % 97.48 % 94.26 % 78.38 % 89.29 % 29.83 %

100 %

AGN : i N field area definition f o r guard ring implantation

I PoLY1: I First polysilicon mask etch N+ IMPLAKT: i NMOS source/drain mask p+ IMPLANT: 1 PMOS source/drain mask

I

I

CONTACT: I Contacts opening mask etch METAL: 1 Metal interconnect mask

I etch

TABLE IV DIVISION OF 2K X 8 MEMORY MASKS INTO FOUR AREA SUBCOMPONENTS

I I s4 I s3 I 52 I s1

P- IMP NIT AGN POLY1 K+ IMP P+ IMP B .APS POLY2 CONT KETAL PADS

99.79 % 40.75 % 99.98 % 42.62 % 96.96 % 96.96 % 94.71 % 18.31 % 95.51 % 23.81 %

100 %

0.19 % 35.59 % 0.02 % 8.74 % 2.86 % 2.86 % 2.84 %

14.35 % 1.16 %

56.90 % 0 %

0.02 % 11.23 % 0 %

23.09 % 0.17 % 0.11 % 2.45 % 5.31 % 0.76 % 6.51 0 % %

0 % 4.43 % 0 % 5 . 5 4 % 0 % 0 % 0 % 2.03 % 1.91 %

12.11 % 0 %

D

m (d) (g)

Fig. 7. (a) POLYl level patterns for four memory cells: (b) Spacings greater than IO pm. (c) Spacings comprised between 5 and 10 pm. (d) Spacings less than 5 p n . (e) Widths greater than 10 pm. ( f ) Widths comprised between 5 and 10 p n . (g) Widths less than 5 p n .

0.54 % 32.05 % 0.94 %

13.71 % 3.77 % 1.48 % 1.02 % 4.52 % 5.82 % 6.90 % 0 %

0.04 % 11.75 % 0 %

31.44 % 1.61 % 0.70 % 3.03 % 9.69 % 2.30 % 45.68 % 0 %

0 % 18.26 % 0 %

15.36 % 0.41 % 0.24 % 1.67 % 7.42 % 2.59 %

11.59 % 0 % mentioned before. Table I11 describes our basic CMOS

process steps. Defect counting was done using dark field illumination on a microscope. Defects were counted on five dies (one in the center and four on a half wafer radius circle) for two wafers per lot, which gives 10 dies per level on each lot.

TABLE VI DIVISION OF MICROPROCESSOR MASKS INTO FOUR AREA SUBCOMPONENTS

IV. EXPERIMENTAL RESULTS AND DISCUSSIONS A . Partitioned Area Calculations on Three Different Products

The area subcomponents calculation results are given on Tables IV, V, and VI for the 2K X 8, 16K X 1 and 80C51 circuits, respectively. These results are given as a percentage of the total die area. The four partitioned areas

5 4 5 2 s1

2.22 % 16.59 % 0.17 %

21.12 % 2.00 % 1.59 % 6.53 % 19.12 % 0 %

0.01 % 5.18 % 0.2 % 9.81 % 0.07 % 0.44 % 0.48 %

42.52 % 0 %

0 % 2.21 % 0 % 8.82 % 0.01 % 0 % 2.41 % 9.58 % 0 %

91.77 % 75.95 % 99.62 % 59.68 % 97.92 % 97.97 % 90.59 % 35.32 %

100 %

N- IMF NIT. AG P POLY PROT. DEPL. CONT. METAL PADS

164

lpmtt2.5pm/ 2.5pm

GANDEMER et a / ' CRITICAL AREA AND LEVELS CALCULATION IN YIELD MODELING 165

TABLE IX LEVEL YIELD A N D CRITICAL COEFFICIENTS FOR 2K x 8 MEMORY

LEVEL

P- I n p

POLY1 N+ IUP P+ I n p B-APS POLY2

UETAL 0 . 8 0 1 0 . 4 0 1 0 . 9 0 7 I 0 . 1 7 6

TABLE X LEVEL YIELD A N D CRITICAL COEFFICIENTS FOR 16K x 1 MEMORY

I I

I LEVEL I Y I a N- I n p 0 . 9 4 3 0 . 1 6 1 NIT 0 . 8 5 6 I 0 . 4 2 7 AGP 0 . 9 4 3 I 0.161

P+ IUP 0 . 9 3 9 I 0 . 1 7 3 B.APS 0 . 9 3 0 I 0 . 1 9 9 POLY2 0 . 8 9 6 I 0 . 3 0 2 CONT 0 . 9 2 7 I 0 . 2 0 8 UETAL I 0.800 PADS 1- 0 . 9 4 3 I ::!ti -

n Y = 3 2 . 3 % 1 1 a = 3 . 1 0 I

TABLE XI LEVEL YIELD AND CRITICAL COEFFICIENTS FOR MICROPROCESSOR

1 I LEVEL I Y I OI

N- IMP1 0 . 8 8 0 0 . 1 8 7 NIT I 0 . 8 3 4 I 0.265 AGP I 0 . 8 8 0 I 0 . 1 8 7 POLY 0 . 7 7 8 I 0 . 3 6 6 PROT. I 0 . 8 7 9 1 0 . 1 8 8 DEPL. I 0 . 8 7 8 I 0 . 1 9 0

TABLE XI1

DENSITY CRITICAL COEFFICIENTS VERSUS PRODUCT TYPE AND VERSUS DEFECT

I 1 2Kx8 MEMORY 1 16Kx1 MEMORY IMICROPROCESSOR I oI I METAL-POLY1 I METAL 1 METAL

Xa 2 . 6 8 3 . 1 2 . 3 6 I Y I 2 2 . 7 % I 3 2 . 3 % I 1 9 . 9 % 1 NETAL;P:kYl METAL METAL

2 . 9 4 I 2 . 1 4 ," I 4 6 . 2 % I 5 5 . 8 % 4 2 . 6 % METAL-POLY1 I METAk5 1 METAL

2 . 3 8 2 . 0 5 5 9 . 4 % I 6 7 . 4 % I 55.9%

i METAL-POLY1 METAL i METAL 2 . 2 9 I 2 . 8 6 1 . 9 8 ," I 7 3 . 0 % 7 8 . 6 % I 7 0 . 1 %

------- >

x ( vm) Defect s i z e

x o

Fig. 10. Variation in X on defect size distribution.

Number I o f

x ( r m ) x o Defect size

Fig. 11. Variation in ,y on defect size distribution.

There are 11 technological levels for 2K X 8 and 16K

We note two interesting points:

1) The METAL level is the most critical for the three products (for the 2K x 8 memory, the POLY1 is equivalent).

2) The number of critical levels for a product is nearly constant (decreasing slightly) when the considered defect density is divided by 2, 3, or 5.

The first point confirms that the critical levels are de- fined first by the relative area of surface patterned on the chip and second by the pattern size. That is why contact level (which is considered critical for processing because of contact size) appears not very critical compared to metal level in our analysis: the relative area occupied by con- tacts is very small.

The second point shows that the critical coefficients de- termination are quasi independent of defect density, as we will see next.

X 1 memories and 9 for microprocessors.

D. Critical Coeficients Dependence on Defect Density and Defect Size

It is interesting to predict model responses to modifi- cations in distribution from a given situation where defect density X (x) is fixed. We will examine two cases corre- sponding to a variation in X and x. The idea here is to study model sensitivity with respect to X and x parame- ters.

The two cases for defect density distribution variations are represented in Figs. 10 and 11. The first figure cor- responds to an increase of defect density, the second one to a defect size repartition modification. As we start from circuit partitioning and defect density versus defect size

166 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 2, FEBRUARY 1988

repartition function to calculate the so-called critical coef- ficient a, we have calculated the maximum a, variation obtained in a given wafer fabrication environment. Tak- ing into account the /3 and y coefficients defined as A = /3 X and x = x/y (which is mathematically equivalent to X = y2) on Figs. 10 and 11 and introducing these two parameters in our ais calculation lead to the conclusion that a 15-percent maximum variation can be expected for current manufacturing environments. That remark per- mits one to apply the model to one product manufactured in different production lines.

V. CONCLUSION We have described a method for calculating critical

coefficients to be included in an I.C. yield model for each

Sophie Gandemer received the engineer degree from the Ecole Nationale SupCrieure des IngC- nieurs Electriciens de Grenoble, France, and the D.E.A. degree from the University of Grenoble in 1984. She received the Doctor degree in 1987 for her work on yield modeling.

She is currently working at Matra-Harris-Sem- iconducteurs in Nantes, France, and at the Ecole Nationale SupCrieure des TClCcommunications in Paris.

*

masking step. The yield model is a function of the chip Bernard C. Tremintin received the M S degree surface, of the defect density, and of a mathematical law. in electronics and the D E.A. degree in micro- The method relies on the partitioning for each level of electronics from the University of Paris XI-Orsay

in 1971 and 1972, respectively. total mask area into area subcomponents sensitive to a From 1973 to 1982, he worked at 1.B.M , Cor- minimal defect size using a design rule checker program. beil Essonnes, France, on reliability physics and Defect density with respect to size was experimentally de- failure analysis of Schottky diodes, on technology

development for analog circuits, and on device termined, and the selected mathematical law corre- characterization and modeling. In 1982, he joined sponded to our data. Yield per level Y, was determined by Matra-Harris-Semiconductcurs (M.H.S.) in applying the model to critical areas with their correspond- Nantes, France, where he successively worked as ing defect densities. ~h~ calculation of a, was carried out device characteristics group leader and manufacturing engineering man-

ager. He is today in a staff position at M.H.S. where he is involved in new using the equation Y, = 1 /( 1 + A T X ) a , where Y, is the i-level yield, AT the total chip area, and X the average value of defect density per level. We found that the re- sultant a, values were stable in a given environment what- ever the technology, the average defect density value, and the design rules. In conclusion, this method permits one to construct a predicting yield model for a given circuit in a given production line.

technologies development.

*

REFERENCES B. T . Murphy, Cost size optima for monolithic integrated circuits, Proc. IEEE, vol. 52, pp. 1537-1545, Dec. 1964. C. H. Stapper, Defect density distribution for LSI yield calcula- tions, IEEE Trans. Electron Devices, vol. ED-20, pp. 655-657, July 1973. A. V. Ferris-Prabhu, Role of defect size distribution in yield mod- eling, IEEE Trans. Electron Devices, vol. ED-32, pp. 1727-1736, 1985. C. H. Stapper, Modeling of integrated circuit defect sensitivities, I B M J . Res. Develop., vol. 27, no. 6 , pp. 549-557, 1983. - , Modeling of defects in integrated circuit photolithographic pat- terns, I B M J . Res. Develop., vol. 28, no. 4, pp. 461-475, 1984. A. V. Ferris-Prabhu, Modeling the critical area in yield forecasts, IEEE J. Solid-Stare Circuits, vol. SC-20, pp. 874-878, 1985.

Jean-Jacques Charlot received the Docteur 3bme Cycle degree in 1967 for his work on the thermal resistance of thynstors and the Docteur dEtat de- gree in 1973 for his work on the properties of plat- inum-doped silicon, both from the University of Pans XI, Orsay.

From 1974 to 1980, he successively was As- sistant Professor of Physics and Electronics at the University of Tunis, head of the teaching staff at the Institut National des Industries Ltgtres of Al- ger, and Professor of Electronics at the Ecole Nd-

tionale Suptrieure Polytechnique of YaoundC, Cameroon. In 1980, he joined the Ecole Nationale Suptrieure des TClCcommunications of Paris where he is Professor of Solid-State Electronics and Technology, assistant head of the Department of Electronics, and head of the research group working on modeling/characterization of semiconductor devices.