TRANSACTIONS ON EMERGING TELECOMMUNICATIONS TECHNOLOGIES
Trans. Emerging Tel. Tech. 2016; 00:1–13
DOI: 10.1002/ett
RESEARCH ARTICLE
Crystal-Free Network SynchronizationThomas Watteyne1,∗, Branko Kerkez2, Kris Pister3, Steven Glaser4
1 Inria, EVA team, Paris, France.2 Civil and Environmental Engineering, University of Michigan, Ann Arbor, USA.3 Electrical Engineering and Computer Science, University of California, Berkeley, USA.4 Civil and Environmental Engineering, University of California, Berkeley, USA.
ABSTRACT
The goal of the Smart Dust cubic-millimeter wireless sensor node seemsfinally within reach due to recent advances in
MEMS packaging, on-chip antennas, thin-film batteries, and radio design. A last hurdle is provided by the reliance of
Machine-to-Machine (M2M) low-power wireless devices on crystal oscillators for time-keeping. TDMA-based networks
depend on such crystal oscillators to facilitate network synchronization and efficient communication. Including a quartz
oscillator in a cubic-millimeter low-power wireless node presents complex and costly challenges. Simple resistive-
capacitive (RC) oscillators, which can be fabricated on silicon, provide an alternative option, but are known to experience
clock drift at magnitudes which make them an infeasible option for convectional synchronization approaches. This
article demonstrates, through implementation, that time slotted communication and frequency channel hopping can be
implemented on constrained wireless nodes without the use of a crystal clock source. We present a new synchronization
approach, which permits us to utilize high-drift, RC-oscillators to synchronize nodes within a network. We show that our
approach mitigates the large drift characteristics and frequency instabilities of an RC-oscillator, while effectively reducing
the overall clock drift to the equivalent of a 100 ppm crystal. Furthermore, we explore the implications of our results on
the realization of the System-on-Chip millimeter-cubed wireless sensor node. Copyright c© 2016 John Wiley & Sons, Ltd.
∗Correspondence
2 rue Simone Iff, 75012 Paris, France. E-Mail: [email protected].
1. INTRODUCTION
Motivated by the Smart Dust vision [1], the past decade
has seen a significant reduction in the size of low-
power wireless nodes. The goal of the cubic-millimeter
mote [2] appears to be within reach. The System-on-
Chip (SoC) node has been proposed [3] to address such
a small form-factor while providing reliable, low-power
operations. Such a solution envisions the ability to print all
the components of the sensor node, including the micro-
processor, radio and sensors, on one die of silicon.
The single chip mote is well within reach. Advances
in MEMS packaging [4, 5, 6] allow sensors and
other components to be bundled efficiently at small
scales. Crystal-free radios [7, 8, 9] are enabling
data transmission using silicon-based oscillators, thus
eliminating the need for external high-frequency clock
sources. On-chip antennas [10, 11] and thin-film battery
technology [12, 13] can further reduce the footprint and
power requirements of single-chip sensor nodes. A number
of compact platforms have already taken advantage of
these advances, showing that holistic and millimeter-scale
packages can be fabricated to include sensing, computation
and communication [14]. With many of the major barriers
removed, one of the lasts hurdles to the cubic-millimeter
motes relates to reliable clock sources and oscillator
design.
Copyright c© 2016 John Wiley & Sons, Ltd. 1
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Crystal-Free Network Synchronization T. Watteyne, B. Kerkez, K. Pister, S. Glaser
Figure 1. A system-on-chip mote demands the removal ofoscillator crystals, including a high frequency crystal for radiotransmissions, and a second crystal for TDMA communications.
Low-power wireless nodes often use external quartz
crystal oscillators as a time-keeping source (see Fig. 1).
The use of such crystals enables node-to-node synchro-
nization, network-wide time-stamping, time division mul-
tiple access (TDMA) communications, and frequency hop-
ping techniques. Including such a quartz oscillator in a
cubic-millimeter mote is both complex and costly. Alterna-
tively, it is much easier to use a simple resistive-capacitive
(RC) circuit as a clock source, as they can be printed
on-chip. Their output frequency, however, varies greatly
due to manufacturing processes, as well as environmen-
tal factors such as fluctuations in temperature and sup-
ply voltage. MEMS-based oscillators present yet another
option [15, 16]. These oscillators can be fabricated on-
chip, but currently do not provide high enough frequencies
to source radio transmissions, while also suffering from
high temperature drift, and long-term stability issues.
Rather than placing emphasis on the need for improved
physical components, this article shows that a system-level
approach can be used to conduct TDMA-based network
synchronization using simple RC-type oscillators. We
outline a synchronization technique to compensate for the
inherent drift and instabilities of RC-based oscillators. This
RC circuit thereby becomes an Ultra Low Power (ULP)
timer, replacing the quartz resonator (Fig. 1) that is used for
network synchronization. ULP timers are now capable of
operating in a sub-nW range [17], having the potential to
significantly reduce power consumption compared to even
some of the most power efficient crystal-based solution.
Coupled with advances in crystal-free radios, our approach
could be used to create a truly single-chip, crystal-free,
cubic-millimeter mote.
In this article, we experimentally validate our proposed
algorithms by operating a multi-node network on a
crystal-free TDMA schedule, while showing that time
synchronization can readily be implemented on low-end
nodes. To the best of our knowledge, this article is
the first to demonstrate synchronization with nodes not
equipped with a crystal oscillator. Through a technique
we call adaptive synchronization, we achieve
synchronization accuracies similar to the ones obtained
with a crystal time-source, while utilizing an on-chip
digital oscillator which has a drift four orders of magnitude
higher. We introduce novel synchronization ideas such as
synchronization bootstrapping, all of which
have been implemented on real-world hardware, and
which can be used directly along with existing TDMA
synchronization protocols and standards.
Section 2 reviews synchronization techniques, with
a particular emphasis on TDMA-based methods. To
motivate the problem, and to understand the limitations of
the clock sources at hand (in this case, digitally controlled
oscillators internal to a micro-controller), Section 3.2
analyzes measurements of inter-device variability, and
carries out a study of oscillator clock drift as a function
of temperature and supply voltage. Section 4 formalizes
the proposed crystal-free TDMA-based synchronization
method. The efficiency of this technique is verified
experimentally on low-end hardware, by analyzing the
performance of a multi-node deployment. Furthermore, in
Section 5.2, we present optional techniques to improve the
convergence speed ofadaptive synchronization
and to decrease the power consumption of network nodes.
Section 8 concludes this article and outlines the future
steps necessary for the realization of the millimeter-cubed
sensor node.
2. RELATED WORK
The vast majority of communicating entities contain a
clock source, which ticks at a certain frequency. For
two such entities, the process of synchronization involves
aligning the phase and the period of their clocks. Once
this is achieved, the two devices effectively share the
same sense of time, and can more effectively coordinate
future tasks, including synchronizing communications.
Environmental fluctuations or imperfections in the clock
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DOI: 10.1002/ett
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T. Watteyne, B. Kerkez, K. Pister, S. Glaser Crystal-Free Network Synchronization
timeMaster
+/-30us
+/-30us
+/-30us
+/-30us
+/-30us
+/-60us
+/-60us
+/-60us
+/-60us+/-60us
+/-60us
+/-60us
+/-60us
Figure 2. A Directed Acyclic Graph centered at a time mastercan be used to distribute timing information in a multi-hoptopology. Every node elects a time parent to which it keeps
synchronized.
construction cause one of the clocks to tick faster than the
other. Even if this difference in clock frequency is small,
it eventually causes the two clocks to fall out of phase,
widening the synchronization error, and thus requiring re-
synchronization. The acceptable error is governed by an
application, from seconds (e.g. a wrist watch) to nano-
seconds (e.g. time-of-flight localization).
In the case of a low-power wireless network,
network-wide synchronization is often used for clock
dissemination, which builds a common time base
upon which to time-stamp data. Typical multi-hop
implementations use a Directed Acyclic Graph centered at
a time master. As depicted in Fig. 2, each node elects a
time parent to which it synchronizes. This also means that,
the more hops a node is from the time master, the higher
its absolute synchronization error.
The following sections detail the most common
techniques used to synchronize two clocks: one-way, two-
way, and slot-based synchronization. In all cases, we
assume the two entities wishing to synchronize are able to
send information to one another. The methods are different
in the overhead required for implementation.
2.1. One-way Synchronization
In most low-power wireless deployments, a synchroniza-
tion error of tens to hundreds of micro-seconds is accept-
able. Such an error can be achieved via one-way synchro-
nization (Fig. 3), a method which relies on accurate time-
stamping of transmitted packets.
node B
T1T2
node A
{T1}
Figure 3. One-way synchronization.
In Fig. 3, nodeB is desynchronized. Its clock is set
to T2, and it is synchronizing off nodeA, the time
master, whose clock is set toT1. Node A periodically
transmits synchronization packets to its neighbors, thereby
advertising its time to other nodes (here, nodeB). The
last bytes of a synchronization packet contain a time-stamp
field, which, prior to the transmission of the packet is set
to an error code. NodeA then sends that packet, including
the error code, to its radio chip, and instructs the radio
to send the packet. As soon as the first byte leaves the
radio, an interrupt line goes high, alerting nodeA’s micro-
controller, which timestamps this instance asT1. While
the packet is still leaving the radio, the micro-controller
replaces the error code byT1. As soon as nodeB receives
the packet, it timestampsT2 and uses (1) to determine its
synchronization error.
error = T2− T1 (1)
This technique requires the packet to be long enough to
ensure the micro-controller has enough time to overwrite
the error code before the packet is completely transmitted.
If, for some reason, this is not the case, nodeB
receives the error code, thus instructing it to ignore the
synchronization request. This one-way synchronization
technique is used by the Flooding Time Synchronization
Protocol (FTSP) [18].
2.2. Two-way Synchronization
Traditional computer networks use the Network Time
Protocol (NTP) [19] to synchronize system clocks. NTP
follows a generalized client-server architecture, where
client computers contact time servers to ask for the time.
Clients typically re-contact the server at regular intervals.
In the wired Internet, round-trip delays of hundred of
milliseconds are commonplace, so by the time the server’s
response reaches the client, time has passed and the time-
stamp becomes inaccurate.
To cancel the effect of non-negligible propagation
delays, NTP uses a technique known as “two-way
synchronization”. The same method can be implemented
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Crystal-Free Network Synchronization T. Watteyne, B. Kerkez, K. Pister, S. Glaser
node B
T1
T2
T3
T4
node A
{T2,T3}
Figure 4. Two-way synchronization is used to evaluate the offsetbetween two clocks when the propagation delay is not negligible,
see (2).
in low-power wireless, and is illustrated in Fig. 4. Node
B is synchronizing to nodeA. Two-way synchronization
relies on the ability to accurately time-stamp transmission
and reception instants of packets. NodeB begins by
transmitting a packet to nodeA, noting at what timeT1 it
did so. NodeA time-stamps the reception of this packet at
T2, and replies with an acknowledgment packet containing
T2, as well asT3, the time at which the reply was
transmitted. At reception, nodeB timestamps the arrival
of the reply asT4, and uses (2) to re-align its clock by
computing the propagation delay and the synchronization
error between its clock and that of nodeA.
{
delay = (T4−T1)−(T3−T2)2
error = (T2−T1)+(T3−T4)2
(2)
While NTP version 4 [19] can theoretically achieve
micro-second accuracy, it is often limited by potential
software delays. This is mitigated by theIEEE1588
standard [20], which is based on the same two-way
synchronization method, but implemented in hardware.
This causes any delays introduced by network elements to
be largely deterministic. [21] presents an implementation
of this standard, with experimental results indicating
synchronization errors on the order to tens of nano-
seconds.
Very tight synchronization is also being used in low-
power wireless for Radio-Frequency Time-of-Flight (ToF)
ranging. [22] presents a prototype radio which uses the
equivalent of two-way synchronization to measure the time
it takes for an wireless signal to travel between two radios.
Because its takes that signal only 1 ns to travel 30 cm,
extremely tight synchronization is required to achieve good
range measurements.
2.3. Slot-based Synchronization
Since clock drift causes low-power wireless nodes
to de-synchronize, it may appear that that network-
wide synchronization may not be energy-efficient, and
that the overhead associated with synchronization adds
unnecessary complexity to the wireless node firmware.
However, a robust synchronization procedure, coupled
with a well-designed communication schedule, can play a
significant role in the reduction of the radio duty cycle, and
thus directly facilitates lower energy consumption [23]. A
synchronization error of tens to hundreds of micro-seconds
is acceptable for use within low-power wireless [24].
Combined with the fact that propagation delays are almost
negligible in wireless systems, this implies that two-way
synchronization is not required, and a simpler one-way
synchronization scheme can be employed.
Time-Division Multiple Access (TDMA) is a synchro-
nization technique that relies on an agreed-upon transmis-
sion schedule between network nodes (Fig. 5). Time is
sliced up into timeslots of equal length; a constant number
of slots make up a slot frame which repeats indefinitely
over time. Once synchronized, network node pairs are
scheduled to exchange communications at a specified time
slot, and channel offset (frequency channel) within the
repeating slot frame. A major requirement stipulates that
no two node pairs can communicate during the same time
slot and on the channel offset, thus ensuring collision-free
communication.
One-way synchronization can be significantly simpli-
fied if the network operates in such a time-slotted manner.
Instead of exchanging explicit timestamps, all nodes agree
that during a scheduled transmission any packet will be
transmitted exactlytsTxOffset (a duration) after the
beginning of a slot (Fig. 5). Every packet is thereby
implicitly timestamped as being senttsTxOffset after
the beginning of the slot. In Fig. 5, nodeB is synchronizing
to its time parentA by timestamping received packet
and comparing this timestamp to the expected TX Offset.
This allows the computation of the synchronization error
computed using (1). NodeB then re-synchronizes by
offsetting the phase of its slot frame (Fig. 6) to match that
of nodeA. Provided the schedule is built correctly, TDMA
can significantly increase the throughput of a network,
while reducing energy consumption and packet collision
rate [23].
4 Trans. Emerging Tel. Tech. 2016; 00:1–13 c© 2016 John Wiley & Sons, Ltd.
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T. Watteyne, B. Kerkez, K. Pister, S. Glaser Crystal-Free Network Synchronization
Figure 5. Slot-based communication splits time into repeatingframes, which repeat indefinitely. Nodes are scheduled tocommunicate at specific slots and frequency channels withinthe frame. All packets are transmitted exactly “TX Offset” afterthe beginning of a slot. A node synchronizes to its time parentby time-stamping arriving packets and comparing them to theexpected value TX Offset. In the event that two nodes areslightly de-synchronized, a “guard time” is used to turn on areceiving node’s radio before the expected arrival of a packet
to ensure that an incoming transmission is not missed.
Clock drift error
Node A
Node B
Node A
Node B
b) Adapting the slot phase
a) Desynchornized slot frameSlot
Figure 6. During slot-based synchronization, a node offsets thephase of its timeslot to match that of its time parent.
A number of standards for low-power and highly reli-
able low-power wireless have emerged around TDMA-
based communication. The HART Communication Foun-
dation standardizes embedded networking solutions for
industrial applications. Their wireless extension,Wire-
lessHART [25], uses a central controller to schedule com-
munications. A major benefit of such a slotted schedule
is the ability to channel hop, changing frequency channels
for each transited packet, thus significantly mitigating the
effect of multi-path fading and external interference [26].
WirelessHART uses IEEE802.15.4 radios to evenly hop
over 15 frequency channels in the 2.4 GHz band. A very
similar TDMA-based standard,ISA100.11a [27], has also
been developed by the the ISA100 Wireless Compliance
Institute. Finally, theIEEE802.15.4e [28] task group has
standardized “Time Synchronized Channel Hopping” as a
MAC protocol enhancement in IEEE802.15.4.
3. HARDWARE CONSIDERATIONS
3.1. Clock Stability and Timestamping
A robust implementation of Time Synchronized Channel
Hopping demands reliable hardware resources to ensure
accurate time-stamping of packets. Once synchronized,
nodes require a stable low-power clock to ensure that they
stay synchronized to their time parent, while being able to
keep the majority of resources (micro-controller and radio)
powered off to conserve energy. The stability of a clock
is quantified by its drift, typically measured in parts-per-
million (ppm), and is the difference in frequency relative
to another clock source. For example, a drift of 10 ppm,
indicates that every 1 s, two clocks will move 10µs apart.
Crystal oscillators rely on a piece of crystal, typically
quartz, resonating at a given frequency. The quality of the
cut of that crystal impacts its drift. For typical low-power
wireless nodes, low power crystal oscillators operate at
32768 Hz, with crystals exhibiting a drift of 10-30 ppm.
In a TDMA-based network, these crystals are used to
time-stamp packets by incrementing a counter internal to
the micro-controller at each clock tick. An interrupt is
triggered at the reception of a radio packet, and the current
value of the counter (e.g. a 16-bit timestamp) is stored
in memory. The accuracy of the timestamp depends on
the frequency of the clock driving the counter. A 32 kHz
crystal, for example, is accurate to within1/32768 ≃
30µs. This offers an adequate trade-off between low-
power operation and time-stamping accuracy. Digitally
controlled, RC-type oscillators, which can be fabricated
within the micro-controller, often oscillate at higher
frequencies. Such oscillators exhibit significantly higher
drift, and are much more susceptible to fluctuations in
temperature and voltage. We show here, however, that
it is possible to effectively synchronize a TDMA-based
network using those low-end RC-based oscillators.
3.2. Preliminary Measurements
All of the methods in this article have been implemented on
on the eZ430-RF2500 platform [29], a low-cost wireless
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Crystal-Free Network Synchronization T. Watteyne, B. Kerkez, K. Pister, S. Glaser
node containing an MSP430 [30] 16-bit 16MHz micro-
controller and a CC2500 [31] radio. This platform was
chosen to showcase the ability to implement TDMA-based
networking on low-end, resource-limited, out-of-the-box
hardware, thus acknowledging that most platforms can
provide the same capabilities. The micro-controller only
has 1 kB of RAM memory (10’s kB is typical) and 32 kB of
flash (100’s kB is typical). A digital bus allows the micro-
controller to load packets into, and receive packets from
the radio. The platform allows an interrupt to be enabled to
signal the beginning of a received packet.
The MSP430 micro-controller features a 16 MHz
Digitally Controlled Oscillator (DCO), implemented as
a ring oscillator. It also contains a 12 kHz Very Low-
power Oscillator (VLO) [30]. The eZ430-RF2500 does
not have a low-power, on-board 32 kHz crystal. The
CC2500 radio chip is driven by a 26 MHz crystal oscillator.
For comparison purposes, the radio is programmed to
output a divided version of its crystal output. Using
a Agilent 53131A Universal Counter, the inter-device
frequency variation, as well as variation over a range of
temperature and voltages were monitored for the DCO,
VLO, and crystal∗. In each case, the frequency variation
was quantified in parts-per-million (ppm).
Fig. 7 shows the variation of output frequency for
11 different eZ430-RF2500 boards, at a steady ambient
temperature of 25 C, and a constant input voltage of 3.6 V.
The crystal oscillator exhibited the smallest drift (7 ppm),
providing a timer accuracy well suited for conventional
synchronization protocols. The VLO showed significant
inter-device drift, at an average of 145000 ppm, with a
frequencies varying between 11 kHz and 12.5 kHz. The
DCO offered a 10-15 fold improvement over the VLO,
but inter-device frequency still varied between 995 kHz to
1005 kHz.
Fig. 8 shows the effect of supply voltage on clock
frequency, for a given eZ430-RF2500 board at a constant
temperature. The crystal oscillator remains extremely
stable over the supply voltage range, with an average drift
less than 1 ppm, while the VLO and DCO drifts by tens of
thousands of ppm.
The third experiment investigates oscillator stability
in regard to temperature fluctuations. An eZ430-RF2500
∗ For most 32 kHz crystals, these values are readily available from manufacturerdata sheets.
10.5
11.0
11.5
12.0
12.5
13.0
1 2 3 4 5 6 7 8 9 10 11
VLO
(kH
z) theoretical
145460 ppm
0.990
0.995
1.000
1.005
1.010
1 2 3 4 5 6 7 8 9 10 11
DC
O (
MH
z)
theoretical 11164 ppm
135.4150
135.4155
135.4160
135.4165
135.4170
1 2 3 4 5 6 7 8 9 10 11
crys
tal (
kHz)
mote ID
theoretical
7 ppm
Figure 7. Variation of the clock frequencies over a set ofdifferent motes. Temperature is kept constant at 25 C, voltage
at 3.6 V.
10.5
11.0
11.5
12.0
12.5
VLO
(kH
z)
theoretical
62833 ppm
0.9960.9981.0001.0021.0041.0061.0081.0101.0121.014
DC
O (
MH
z)
theoretical
13395 ppm
135.4160
135.4165
135.4170
135.4175
135.4180
135.4185
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
crys
tal (
kHz)
Vcc (V)
theoretical 1 ppm
Figure 8. Variation of the clock frequencies over a range ofsupply voltages Vcc. Temperature is kept constant at 25 C.
board is mounted on top of a heating/chilling plate, and
the temperature is varied from -5 C to 50 C, while the
voltage is kept at a constant 3.6 V. Similarly to previous
cases, Fig. 9 shows that the crystal remains much more
stable relative to the VCO and DLO.
The above measurements further validate why crystals
remain the dominant clock sources for low-power wireless
synchronization applications.While digitally-controlled
oscillators such as the DCO and the VLO of the MSP430
exhibit a drift that is orders of magnitude worse than
a crystal oscillator, this article introduces techniques
to permit such clock-sources to be utilized for effective
TDMA-based network.
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T. Watteyne, B. Kerkez, K. Pister, S. Glaser Crystal-Free Network Synchronization
10.5
11.0
11.5
12.0
12.5
13.0
VLO
(kH
z) theoretical
138300 ppm
0.9930.9940.9950.9960.9970.9980.9991.0001.0011.0021.003
DC
O (
MH
z) theoretical
5083 ppm
135.2000135.4000135.6000135.8000136.0000136.2000136.4000
-15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
crys
tal (
kHz)
temperature (C)
theoretical
280 ppm
Figure 9. Variation of the clock frequency over a range oftemperatures. Supply voltage is kept constant at 3.6V.
Clock drift error
Node A
Node B
Node A
Node B
b) Adapting the slot phase
Node A
Node B
c) Adapting the slot duration
a) Desynchornized slot frameSlot
�requency drift error
Figure 10. Unlike in conventional TDMA synchronization (seeFig. 6), adaptive synchronization involves changing both the slotphase (b) as well as the slot duration (c) to account for unstable
clock sources.
4. PROBLEM DEFINITION
The major challenge associated with utilizing inaccurate,
high-drift clock sources for TDMA-based synchronization
relates to the instability of the clock’s frequency (frequency
drift). Crystal-free nodes are unaware of the relative speed
at which their clocks operate. For example, as seen in
the previous section, it is entirely feasible that for one
node 1000 clock ticks translate to 9 ms, while for another
node it might take 11 ms. Such specifications make
the tight time structure required for conventional slotted
communications infeasible. Thus, as depicted in Fig. 10
(a) and (b), if the frequencies of two nodes are not tuned
correctly, only adapting the slot phase is not sufficient.
In our proposed adaptive synchronization approach, the
nodes also adapt their slot duration to account for
frequency drift of the their clocks (see Fig. 10 (c)).
5. PROPOSED METHOD
We assume the presence of a time master node in the
network, against whom other nodes synchronize (possibly
using a structure as in Fig. 2). The network is assumed
to run a slotted protocol, in our case equivalent to
IEEE802.15.4 TSCH. This section describes the proposed
adaptive synchronization procedure, along with several
enhancements which can be further implemented to
achieve more robust performance.
5.1. Core Algorithm
Adaptive synchronization is built upon the TDMA-based
architecture described in Section 2.3. The core of the
algorithm is a controller which timestamps received
packets and adjustsslotDuration andtsTxOffset
durations to mitigate a node’s clock and frequency drift. A
slot resembles that of Fig. 5. As detailed in Section 2.3,
every packet is sent exactlytsTxOffset after the
beginning of a slot. Adaptive synchronization timestamps
the received packets to tune the following values:
• tsTxOffset, the duration between the start of the
slot and the moment the packet leaves the radio,
in clock ticks. This value is used to compute the
synchronization error and to re-align a node’s slot
frame to a time-parent;
• slotDuration, the duration of a single slot, in
clock ticks. VaryingslotDuration changes the
length of the entire slotframe, and thus is used to
correct the effects of frequency drift between two
nodes (see Fig. 10 (b) and (c)).
Adapting the value oftsTxOffset follows the
principle described in Section 2.3, i.e. using one-way
synchronization (1) to re-align a nodes’ slotframe to that
of its time parent. If required, this synchronization error
is then also used to tuneslotDuration. As shown in
Fig. 10 (b), if a synchronizing node’sslotDuration
is not correct, at the next synchronization opportunity, it
adjusts its slot phase to match that of its parent. Adjusting
the phase consists of either delaying or bringing forward
the beginning of the current slot (effectively delaying or
moving forward the entire slot frame).
Adaptive synchronization increments a counter by
1 each time phase is delayed, and decrements it by
1 when brought forward. During this process, it also
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keeps of the previous synchronization errors in an array
PreviousErrors (in the form of a circular buffer). Once
the synchronization counter reaches a value ofsyncthresh,
the node calculates itsslotDuration error using (3).
errorSlotDuration =average(PreviousErrors)
Num of Slots in Slot Frame
(3)
(3) is derived assuming a node communicates exactly
once every slot frame with its time parent. This can,
however, be generalized to compute the slot duration
error given any communications schedule. Once the error
is computed, (3) is used to updateslotDuration,
and the syncthresh counter is then reset. Adjusting
slotDuration also requires the adjustment of the
tsTxOffset duration. For ease of implementation, our
specific instance of the algorithm defines a constant ratio
betweenslotDuration and tsTxOffset. In our
implementation, this ratio is 5. This means that, if a node
decides to increaseslotDuration by 5, it has to also
increasetsTxOffset by 1. A 10 msslotDuration
thus gives atsTxOffset of 2 ms, which corresponds
to the IEEE802.15.4e standard. This constant ratio is not
required, and the algorithm can be configured to deal with
an arbitrarytsTxOffset within a slot.
Our implementation defines the constantsyncthresh =
20. This value could potentially be parameterized through
the physical properties of the oscillator. For example,
the Allan Deviation [32] of an oscillator could
be used to evaluate its frequency stability and to
quantify its noise properties. A node could compare these
values to a online computation ofAllan Deviation
to detect significant frequency drift, and adjust the
slotDuration accordingly. Such optimizations are,
however, beyond the scope of this article.
5.2. Additional Techniques
The methods presented in Section 5.1 are the basics
of adaptive synchronization. This section introduces a
number of additional techniques that can be used to
increase the synchronization speed and lower node power
consumption.
5.2.1. Tuning tsTxDelay
tsTxDelay is the duration between the moment the
micro-controller tells the radio to send the packet, and the
moment the first byte of the packet leaves the radio. On
the CC2500, this take a constant duration of 235µs [31].
Nevertheless, when using low-power oscillators, a node
cannot know the frequency of its clock, and can thus not
convert this duration to a number of clock ticks. Adaptive
synchronization therefore timestamps, through an interrupt
form the radio, when the first packet byte leaves the
antenna. It then compares this value withtsTxOffset
and adjuststsTxDelay such that the edge rises exactly
tsTxOffset clock ticks after the beginning of the slot.
5.2.2. Synchronization Bootstrapping
In accordance with the IEEE802.15.4 TSCH standard,
when a node first attempts to join a network, it
synchronizes by listening for enhanced beacon packets
from nearby neighbors. Timing information about these
packets is then used in conjunction with the adaptive
approach in Section 4 to synchronize to the network. This
process can be relatively slow, especially when a node
and its time parent are operating at significantly different
frequencies, as is the case when using digitally controlled
oscillator clocks.
In our proposed bootstrapping approach, when a
node attempts to join the network, it waits until it
hearstwo beacons from the same time parent. Per the
IEEE802.15.4 TSCH standard, each transmitted beacons
contains a reference to the index of the slot it was
transmitted in. This reference is known as the “absolute
slot number” (asn). It is a counter that keeps track of
all slots throughout the lifetime of the network, even
if the overall slot frame repeats indefinitely. When the
timestamps andasns of each advertisement packet are
recorded, as depicted in Fig. 11, the node can derive a good
estimate of its initialslotDuration using (4).
SlotDurationinitial =timestamp2− timestamp1
(asn2− asn1)(4)
5.2.3. Consecutive Beacon Slots
A slight extension to the bootstrapping technique
described in the previous section involves a time parent
transmitting consecutive beacons. A node joining the
network hears immediate back-to-back beacons, allowing
it to calibrate its initialslotDuration faster (using
(4)). Provided that a node hears both beacons, this
8 Trans. Emerging Tel. Tech. 2016; 00:1–13 c© 2016 John Wiley & Sons, Ltd.
DOI: 10.1002/ett
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T. Watteyne, B. Kerkez, K. Pister, S. Glaser Crystal-Free Network Synchronization
105 105106 107 108 109 110 111 112 113asn: 104
timestamp2 - timestamp1 (clock ticks)
tim
esta
mp2
Node A's
activity
Node B's
timestamping
activity
asn1 asn2
asn2-asn1 (slots)
tim
esta
mp1
Figure 11. Bootstrapping involves measuring the number ofclock ticks between the reception of two advertising packets to
calibrate the initial slotDuration.
approach allows for near-immediate calibration of its
slotDuration faster, requiring only the duration of two
slots (20 ms). The phase of its slot frame can then be
aligned with that of the time parent, after which the node
uses adaptive synchronization to stay synchronized. An
implemented version of this modified schedule is shown
in Fig. 12.
6. IMPLEMENTATION
Adaptive synchronization (including all the additional
techniques described in Section 5.2) is implemented on
the eZ430-RF2500 platform. The implementation uses the
MSP430’s DCO clock while providing a slot length of
10 ms. The source code†, consisting of 973 lines of C
code, was developed using IAR Embedded Workbench
IDE 5.10.4. To link the micro-controller to the radio, we
utilized SPI drivers from Texas Instruments‡, and modified
the readily-available CC2500 drivers. The binary for the
MSP430f2274 micro-controller has a memory footprint of
6532 B of flash memory and 383 B of RAM. Given the
relatively low resources available on the eZ430-RF2500,
our implementation still occupies only a fifth of the
available flash and a third of the RAM, thus leaving further
room for routing and applications.
Fig. 12 shows an oscilloscope-generated snapshot for
a simple network of two synchronized nodes, which are
running the full adaptive synchronization implementation.
NodeA is the time master. The activity of each of the node
is indicated by four digital signals:
• slotFrame toggles when a new slotframe begins;
† As an online addition to this article, the complete source code is available underthe OpenBSD license on the first author’s website.‡ http://focus.ti.com/docs/toolsw/folders/print/simpliciti.html
-20 0 20 40 60 80 100
time (ms)
slot 0 slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8
slotFrame
slot
packet
radio
slotFrame
slot
packet
radio
ADV ADV TX RX OFF OFF OFF OFF OFF
ADV ADV RX TX OFF OFF OFF OFF OFF
node
Bno
de A
Figure 12. Oscilloscope recording of the fully implementedadaptive synchronization procedure. Node A is the time parent.
• slot toggles at each new slot. Each slots is 10 ms
long;
• radio is high whenever the radio chip is on, either
transmitting or in listening mode;
• packet is connected to the interrupt line between
the CC2500 and the MSP430. It is high whenever
bytes are being sent of received by the radio. We
use the low-to-high transition of this line to measure
synchronization error.
Fig. 12 furthermore indicates a sample schedule used by
both nodes:
• Slots 0 and 1 are beacon slots. In those slots,
each node either transmits a beacon, or listens.
An beacon contains enough information for a new
node to join the network. In this case, nodeA
transmits in both slots, while nodeB listens.
This demonstrates the consecutive beacon feature
described in Section 5.2.3.
• Slot 2 is a dedicated slot for nodeB to send
information to nodeA. The first pulse corresponds
to the data message sent fromB to A. The second
pulse in the same slot is the acknowledgment sent
fromA to B;
• Slot 3 is a dedicated slot for nodeA to send
information to nodeB. In this case, nodeA has no
packet to transmit, thus keeping its radio off. Node
A listens for 2 ms, and switches off its radio as it
received nothing.
• Slots 4 through 8 are OFF, the two nodes do not
exchange any packets, and their radios remain off.
A 10-node network was deployed in a large office
setting over a span of 30 h to evaluate the synchronization
algorithm. This deployment also enabled the use of
Trans. Emerging Tel. Tech. 2016; 00:1–13 c© 2016 John Wiley & Sons, Ltd. 9DOI: 10.1002/ett
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Crystal-Free Network Synchronization T. Watteyne, B. Kerkez, K. Pister, S. Glaser
-60
-55
-50
-45
-40
-35
-30
-25
2.4 2.41 2.42 2.43 2.44 2.45 2.46 2.47 2.48
frequency (GHz)
ch.11ch.12
ch.13ch.14
ch.15ch.16
ch.17ch.18
ch.19ch.20
ch.21ch.22
ch.23ch.24
ch.25ch.26
Figure 13. Frequency spectrum recording of a 10-node networkrunning adaptive synchronization, showing the use 16 different
channels for communication.
channel hopping, as described in IEEE802.15.4 TSCH.
Fig. 13 shows a frequency spectrum analysis of
16 frequencies along the 2.4 GHz band, indicating that
the 10 node network effectively utilize all 16 channels
for packet transmission. To our knowledge, this is the
first such implementation of time synchronized channel
hopping which does not rely on a crystal time source.
7. EXPERIMENTAL RESULTS
7.1. Impact of Temperature
To demonstrate the adaptive nature of the proposed
method, the synchronization error,slotDuration and
tsTxDelay are recorded, as a node synchronized to a
time parent. The result is shown in Fig. 14. At about
40 s into the synchronization, an industrial hot-air gun
is briefly used to heat up the synchronized node. In
accordance with Fig. 9, this causes the node’s internal
RC-oscillator to resonate at a higher frequency, thus
effectively reducing the duration of its slots. The algorithm
responds by increasing the node’sslotDuration,
successfully mitigating the frequency drift error induced
by the fluctuation in temperature. The detailed rate-of-
change of temperature is not recorded, but it can be seen
that the algorithm adapts theslotDuration within less
than a second of the occurrence of the event, thus providing
an initial evaluation of the rapid convergence properties of
the proposed approach.
7.2. Long-term Deployment
Fig. 15 displays the temporal behavior of the multi-node
deployment described in Section 6, plotting the average
slotDuration of nodes in the network over a 30 h
period. The figure also shows the spread (one standard
-20
-10
0
10
20
40130
40150
40170
switching on hot airgun
1098
1099
1100
0
40000
1094
1095
20 30 40 50 60 70
Num
ber
of
clo
ck t
icks
Figure 14. Recorded values of synchronization parameters ofadaptive channel hopping while a node is being subjectedto temperature fluctuations. The synchronized node reacts byadapting its slotDuration accordingly. The time parent is notsynchronizing to another node, and therefore does not compute
a synchronization error, or update its slotDuration.
deviation) ofslotDuration among the nodes. High-
frequency fluctuations are apparent in the mean, indicating
that the nodes often adjusted theirslotDuration to
mitigate frequency drift error. Furthermore, a downward
trend can be seen over the 30 h period, showing that
the average network-wideslotDuration adaptively
lowers to retain synchronization to the time parent. A
potential cause of this phenomenon is an increase in the
time parent’s clock frequency. During the experiment, the
time parent was physically connected to a computer for
data-logging purposes. This could have potentially led to
the heating up of the mote due to heat expelled by the
computer, thus causing the time parent’s clock frequency
to increase in accordance with Fig. 9. Further experiments
are required to validate this claim.
7.3. Synchronization Accuracy
Due to clock drift, nodes in a TDMA-based setting need
to re-synchronize regularly to reset their slot phase. The
frequency at which this is required to occur is linearly
proportional to the drift of the clock. For example, to
retain a low radio duty cycle, the IEEE802.15.4 TSCH
standard permits a node to be de-synchronized by at most
1 ms. If clock has drift of 10 ppm, after 100 s it will
become de-synchronized by 1 ms. In the case of slotted
10 Trans. Emerging Tel. Tech. 2016; 00:1–13 c© 2016 John Wiley & Sons, Ltd.
DOI: 10.1002/ett
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T. Watteyne, B. Kerkez, K. Pister, S. Glaser Crystal-Free Network Synchronization
0 5 10 15 20 2539.2
39.25
39.3
39.35
39.4
39.45
Slo
t Dur
atio
n x
1000
(cl
ock
ticks
)
Time (hours)
Figure 15. Average slotDuration for a multi-node networkover time. The gray area reflects one standard deviation around
the mean.
communications, resynchronization thus needs to occur at
least every 100 s. Similarly, if a clock drifts at 100 ppm,
resynchronization needs to occur at least every 10 s to
retain IEEE802.15.4 TSCH specified synchronization to
the network.
A shown in previous sections, the very large clock
drift and frequency instability exhibited by the MSP430’s
DCO can effectively be compensated in software through
adaptive synchronization. Even when compensated, the
resulting system still experiences some clock drift.
Evaluating this resulting drift can be accomplished by
forcing the motes to resynchronize at a specific period.
Clock drift can then be measured for a number of
such periods to characterize the drift behavior of the
proposed approach. In our experiment, this is achieved
by varying the length of the slot frame and forcing
motes to synchronize once per slot frame. An Agilent
53131A Universal Counter is used to evaluate the relative
phase between the start of consecutive slot frames. The
minimum, maximum, and mean of the phase offset are
recorded to evaluate the effects of the resynchronization
period (see Fig. 16). The results are also compared to the
drift of a theoretical 100 ppm crystal oscillator.
Fig. 16 shows that the software compensation offered
by adaptive synchronization mitigates the large drift
characteristics, and frequency instabilities of the MSP430
DCO, effectively reducing the overall drift to the
equivalent of a 100 ppm crystal. In our particular
implementation, nodes utilizing adaptive synchronization
should resynchronize at least every 10 s to meet the 1 ms
synchronization error permitted by IEEE802.15.4 TSCH.
Depending on the bandwidth requirements of a given
-250
-200
-150
-100
-50
0
50
100
150
200
250
0 200 400 600 800 1000 1200
sync
hron
izat
ion
erro
r (u
s)
resynchronization period (ms)
max
min
mean
standard dev.100ppm drift
Figure 16. Synchronization error as a function of theresynchronization period (length of the slot frame). 68% of the
measurements fall with the shaded area.
application, it is reasonable to assume that the majority
of this resynchronization can be accomplished through
the timestamping of data packets, which need to be
transmitted, in any case, as part of general network traffic.
Results obtained from data in Fig. 12 indicate that the
process of resynchronizing consumes 810µs of radio-on
time at the transmitter, 2.55 ms at the receiver. For the
eZ430-RF2500 platform, keeping two nodes synchronized
thus translates into a overhead radio duty cycle of
0.0168%, assuming a 10 s synchronization period.
8. CONCLUSIONS
This article demonstrates that time slotted commutation
and frequency channel hopping can be implemented on
low-end low-power wireless nodes without the use of accu-
rate crystal clock sources. We have presented a system-
level solution to facilitate network-wide synchronization
even when high-drift digital oscillators are used as time
sources. Combined with a crystal-free radio [9], currently
available fabrication methods could then be used to fabri-
cate an entire mote onto a single silicon die, thus facilitat-
ing the greater vision of the millimeter-cubed SoC “Smart
Dust” node. Our solution was implemented on the eZ430-
RF2500 platform to motivate the ability to implement
TDMA-based crystal-free communications on many other
platforms. Superior oscillators and hardware is available,
and thus have the potential to perform even better when
compared to our example implementation.
Trans. Emerging Tel. Tech. 2016; 00:1–13 c© 2016 John Wiley & Sons, Ltd. 11DOI: 10.1002/ett
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Crystal-Free Network Synchronization T. Watteyne, B. Kerkez, K. Pister, S. Glaser
While our motivation was driven by a SoC mote
solution, the implications of this method for power
consumption could be significant. It is reasonable to
suggest that in a large number of TDMA-based networks,
the crystal time-source presents a major source of power
consumption. To ensure synchronization, these crystals
are fully powered throughout the entire lifetime of the
deployment. Thus, coupled with our proposed method,
the use of a sub-nW oscillator [17], when compared to
today’s major low-power crystals, could reduce the amount
of power required for time-keeping by at least an order
of magnitude. Our future work intends to explore the
implementation of such oscillators for low-power wireless
synchronization. Furthermore, we intend to analyze the
detailed convergence properties of our approach over a
broader set of experiments. The ability to use physical
oscillator properties, such as the Allan deviation [32], will
also be investigated to guide a more robust detection of
oscillator frequency drift.
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