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CS 152 Computer Architecture and Engineering Lecture 9 ...cs152/sp16/...2/24/2016 CS152, Spring 2016...

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2/24/2016 CS152, Spring 2016 CS 152 Computer Architecture and Engineering Lecture 9 - Virtual Memory Dr. George Michelogiannakis EECS, University of California at Berkeley CRD, Lawrence Berkeley National Laboratory http://inst.eecs.berkeley.edu/~cs152
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Page 1: CS 152 Computer Architecture and Engineering Lecture 9 ...cs152/sp16/...2/24/2016 CS152, Spring 2016 Last time in Lecture 9 Protection and translation required for multiprogramming

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CS 152 Computer Architecture and Engineering

Lecture 9 - Virtual Memory

Dr. George MichelogiannakisEECS, University of California at Berkeley

CRD, Lawrence Berkeley National Laboratory

http://inst.eecs.berkeley.edu/~cs152

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Administrivia

PS2 and lab 2 due Wednesday next week (March 2nd)

Quiz 2 is on Monday March 7th

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Last time in Lecture 9

Protection and translation required for multiprogramming– Base and bounds was early simple scheme

Page-based translation and protection avoids need for memory compaction, easy allocation by OS

– But need to indirect in large page table on every access

Can use multi-level page table to hold translation/protection information, but implies multiple memory accesses per reference

Can use “translation lookaside buffer” (TLB) to cache address translations (sometimes known as address translation cache)

– Still have to walk page tables on TLB miss, can be hardware or software talk

Virtual memory uses DRAM as a “cache” of disk memory, allows very cheap main memory

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Question of the Day

How would you design a TLB prefetcher?

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Memory Management

Can separate into orthogonal functions:– Translation (mapping of virtual address to physical address)

– Protection (permission to access word in memory)

– Virtual memory (transparent extension of memory space using slower disk or flash storage)

But most modern systems provide support for all the above functions with a single page-based system

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Modern Virtual Memory SystemsIllusion of a large, private, uniform store

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Protection & Privacyseveral users, each with their private address space and one or more shared address spaces

page table <-> name space

Demand PagingProvides the ability to run programs larger than the primary memory

Hides differences in machine configurations

The price is address translation on each memory reference

OS

useri

PrimaryMemory

SecondaryStorage

VA PAmapping

TLB

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Hierarchical Page Table

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Level 1 Page Table

Level 2

Page Tables

Data Pages

page in primary memory page in secondary memory

Root of CurrentPage Table

p1

offset

p2

Virtual Address

(Processor Register)

PTE of a nonexistent page

p1 p2 offset

01112212231

10-bitL1 index

10-bit L2 index

Ph

ysic

al M

emo

ry

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Page-Based Virtual-Memory Machine(Hardware Page-Table Walk)

Assumes page tables held in untranslated physical memory

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PCInst. TLB

Inst. Cache D Decode E M

Data Cache W+

Page Fault?

Protection violation?

Page Fault?

Protection violation?

Data TLB

Main Memory (DRAM)

Memory ControllerPhysical Address

Physical Address

Physical Address

Physical Address

Page-Table Base Register

Virtual Address Physical

Address

Virtual Address

Hardware Page Table Walker

Miss? Miss?

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Address Translation:putting it all together

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Virtual Address

TLBLookup

Page TableWalk

Update TLBPage Fault(OS loads page)

ProtectionCheck

PhysicalAddress(to cache)

miss hit

the page is

memory memory denied permitted

ProtectionFault

hardwarehardware or softwaresoftware

SEGFAULTWhere?

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Page Fault Handler

When the referenced page is not in DRAM:– The missing page is located (or created)

– It is brought in from disk, and page table is updated

• Another job may be run on the CPU while the first job waits for the requested page to be read from disk

• Could be different thread of the same address space

– If no free pages are left, a page is swapped out

• Pseudo-LRU replacement policy, implemented in software

Since it takes a long time to transfer a page (msecs), page faults are handled completely in software by the OS

– Untranslated addressing mode is essential to allow kernel to access page tables

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Handling VM-related exceptions

Handling a TLB miss needs a hardware or software mechanism to refill TLB

Handling a page fault (e.g., page is on disk) needs a restartableexception so software handler can resume after retrieving page

– Precise exceptions are easy to restart

– Can be imprecise but restartable, but this complicates OS software

Handling protection violation may abort process– But often handled the same as a page fault

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PCInstTLB

Inst. Cache D Decode E M

Data TLB

Data Cache W+

TLB miss? Page Fault?Protection violation?

TLB miss? Page Fault?Protection violation?

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Address Translation in CPU Pipeline

Need to cope with additional latency of TLB:– slow down the clock?

– pipeline the TLB and cache access?

– virtual address caches

– parallel TLB/cache access

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PCInstTLB

Inst. Cache D Decode E M

Data TLB

Data Cache W+

TLB miss? Page Fault?Protection violation?

TLB miss? Page Fault?Protection violation?

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Virtual-Address Caches

one-step process in case of a hit (+)

cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-)

aliasing problems due to the sharing of pages (-)

maintaining cache coherence (-) (see later in course)

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CPUPhysicalCache

TLBPrimaryMemory

VA PA PA

Alternative: place the cache before the TLB

CPUVA (StrongARM)Virtual

Cache

PATLB

PrimaryMemory

VA

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Virtually Addressed Cache(Virtual Index/Virtual Tag)

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PC

Inst. TLB

Inst. Cache D Decode E M

Data Cache W+

Data TLB

Main Memory (DRAM)

Memory Controller

Physical Address

Instruction dataPhysical Address

Physical Address

Page-Table BaseRegister

Virtual Address

Virtual Address

Hardware Page Table Walker

Miss?Miss?

Translate on miss

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Question

What is the benefit of separating instruction and data TLBs?

And the downside?

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Aliasing in Virtual-Address Caches

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VA1

VA2

Page Table

Data Pages

PA

VA1

VA2

1st Copy of Data at PA

2nd Copy of Data at PA

Tag Data

Two virtual pages share one physical page

Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other!

General Solution: Prevent aliases coexisting in cache

Software (i.e., OS) solution for direct-mapped cache

VAs of shared pages must agree in cache index bits; this ensures all VAs accessing same PA will conflict in direct-mapped cache (early SPARCs)

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Question

How can we parallelize TLB and cache access?

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Cache

TLB

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Concurrent Access to TLB & Cache(Virtual Index/Physical Tag)

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Index L is available without consulting the TLB=>cache and TLB accesses can begin simultaneously!

Tag comparison is made after both accesses are completed

Cases: L + b = k, L + b < k, L + b > k

VPN L b

TLBDirect-map Cache

2L blocks2b-byte blockPPN Page Offset

=hit?

DataPhysical TagTag

VA

PA

VirtualIndex

k

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Virtual-Index Physical-Tag Caches: Associative Organization

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How does this scheme scale to larger caches?

VPN a L = k-b b

TLBDirect-map

2L blocks

PPN Page Offset

=hit?

Data

Phy.Tag

Tag

VA

PA

VirtualIndex

kDirect-map

2L blocks

2a

=2a

After the PPN is known, 2a physical tags are compared

What about fully-set associative?

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Question

Does virtual tag, physical index make sense?

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Concurrent Access to TLB & Large L1The problem with L1 > Page size

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Can VA1 and VA2 both map to PA ?

VPN a Page Offset b

TLB

PPN Page Offset b

Tag

VA

PA

Virtual IndexL1 PA cacheDirect-map

= hit?

PPNa Data

PPNa Data

VA1

VA2

If they differ in the lower ‘a’ bits alone, and share a physical page.

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A solution via Second Level Cache

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Usually a common L2 cache backs up both Instruction and Data L1 caches

L2 is “inclusive” of both Instruction and Data caches• Inclusive means L2 has copy of any line in either L1

CPU

L1 Data Cache

L1 Instruction

Cache Unified L2 Cache

RF Memory

Memory

Memory

Memory

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Anti-Aliasing Using L2 [MIPS R10000,1996]

Suppose VA1 and VA2 both map to PA and

VA1 is already in L1, L2 (VA1 VA2)

After VA2 is resolved to PA, a collision will be detected in L2 (L2 is in physical space).

VA1 will be purged from L1 and L2, and VA2 will be loaded no aliasing !

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VPN a Page Offset b

TLB

PPN Page Offset b

Tag

VA

PA

Virtual IndexL1 PA cacheDirect-map

= hit?

PPNa Data

PPNa Data

VA1

VA2

Direct-Mapped L2

PA a1 Data

PPN

into L2 tag

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Anti-Aliasing using L2 for a VirtuallyAddressed L1

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VPN Page Offset b

TLB

PPN Page Offset b

Tag

VA

PA

VirtualIndex & Tag

PhysicalIndex & Tag

L1 VA Cache

L2 PA Cache L2 “contains” L1

PA VA1 Data

VA1 Data

VA2 Data

“Virtual Tag”

Physically-addressed L2 can also be used to avoid aliases in virtually-addressed L1

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Atlas Revisited

One PAR for each physical page

PAR’s contain the VPN’s of the pages resident in primary memory

Advantage: The size is proportional to the size of the primary memory

What is the disadvantage ?

How does this work with caches?– Is a TLB necessary?

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VPN

PAR’s

PPN

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Hashed Page Table:Approximating Associative Addressing

Hashed Page Table is typically 2 to 3 times larger than the number of PPN’s to reduce collision probability. What does this mean?

It can also contain DPN’s for some non-resident pages (not common)

If a translation cannot be resolved in this table then the software consults a data structure that has an entry for every existing page (e.g., full page table)

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hashOffset

Base of Table

+PA of PTE

PrimaryMemory

VPN PID PPN

Page Table

VPN d Virtual Address

VPN PID DPN

VPN PID

PID

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Power PC: Hashed Page Table

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Each hash table slot has 8 PTE's <VPN,PPN> that are searched sequentially

If the first hash slot fails, an alternate hash function is used to look in another slot

All these steps are done in hardware!

Hashed Table is typically 2 to 3 times larger than the number of physical pages

The full backup Page Table is managed in software

Base of Table

hashOffset +

PA of Slot

PrimaryMemory

VPN PPN

Page TableVPN d 80-bit VA

VPN

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VM features track historical uses: Bare machine, only physical addresses

– One program owned entire machine

Batch-style multiprogramming– Several programs sharing CPU while waiting for I/O– Base & bound: translation and protection between programs (supports

swapping entire programs but not demand-paged virtual memory)– Problem with external fragmentation (holes in memory), needed occasional

memory defragmentation as new jobs arrived

Time sharing– More interactive programs, waiting for user. Also, more jobs/second.– Motivated move to fixed-size page translation and protection, no external

fragmentation (but now internal fragmentation, wasted bytes in page)– Motivated adoption of virtual memory to allow more jobs to share limited

physical memory resources while holding working set in memory

Virtual Machine Monitors– Run multiple operating systems on one machine– Idea from 1970s IBM mainframes, now common on laptops

• e.g., run Windows on top of Mac OS X– Hardware support for two levels of translation/protection

• Guest OS virtual -> Guest OS physical -> Host machine physical

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Virtual Memory Use Today - 1

Servers/desktops/laptops/smartphones have full demand-paged virtual memory

– Portability between machines with different memory sizes

– Protection between multiple users or multiple tasks

– Share small physical memory among active tasks

– Simplifies implementation of some OS features

Vector supercomputers have translation and protection butrarely complete demand-paging

(Older Crays: base&bound, Japanese & Cray X1/X2: pages)– Don’t waste expensive CPU time thrashing to disk (make jobs fit in memory)

– Mostly run in batch mode (run set of jobs that fits in memory)

– Difficult to implement restartable vector instructions

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Virtual Memory Use Today - 2

Most embedded processors and DSPs provide physical addressing only

– Can’t afford area/speed/power budget for virtual memory support

– Often there is no secondary storage to swap to!

– Programs custom written for particular memory configuration in product

– Difficult to implement restartable instructions for exposed architectures

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Question of the Day

How would you design a TLB prefetcher?

31

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Acknowledgements

These slides contain material developed and copyright by:– Arvind (MIT)

– Krste Asanovic (MIT/UCB)

– Joel Emer (Intel/MIT)

– James Hoe (CMU)

– John Kubiatowicz (UCB)

– David Patterson (UCB)

MIT material derived from course 6.823

UCB material derived from course CS252

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