CS 152 Computer Architecture and Engineering Lecture …cs152/sp05/lecnotes/lec6-2.pdf · Computer...

UC Regents Spring 2005 © UCBCS 152 L12: VLSI II

2005-2-24John Lazzaro

(www.cs.berkeley.edu/~lazzaro)

CS 152 Computer Architecture and Engineering

Lecture 12 – VLSI II

www-inst.eecs.berkeley.edu/~cs152/

TAs: Ted Hong and David Marquardt


Last Time: Device Physics IntroductionWafer cross-section

n+

p-

Wafer doped p-type

n+ region

p- region At V = 0, “hill” too high for electrons to diffuse up.

V

Cathode: -

+

-

Anode: +

no carriers

depletion region

For holes, going “downhill” is hard. V controls hill.

electron

energy

depletion region


Today: Memory Core Cells ...

Transistor wrap-up: Fabrication, p-FETs, device model equations.

DRAM: 1 Transistor + 1 Capacitor


Fabrication


Mask set for an n-Fet ...

p-

n+

Vd = 1V

n+

Vs = 0Vdielectric

Vg = 1V

#1: n+ diffusionTop-down view:

Masks

#3: diff contact#2: poly (gate)

#4: metal

How does a fab use a mask set to make an IC?

Vg

Vd

Vs

Ids I ⋲ µA


Start with an un-doped wafer ...

Steps

p-

#1: dope wafer p-

#5: place positive poly mask and

expose with UV.

UV hardens exposed resist. A wafer wash leaves only hard resist.

#2: grow gate oxide

oxide

#3: grow undoped polysilicon

#4: spin on photoresist


Wet etch to remove unmasked ...

p-

oxide

HF acid etches through poly and oxide, but not hardened resist.

p-

oxideAfter etch and resist removal


Use diffusion mask to implant n-type

p-

oxide

accelerated donor atoms

n+ n+

Notice how donor atoms are blocked by gate and do not enter channel.

Thus, the channel is “self-aligned”,precise mask alignment is not needed!


Metallization completes device

p-

oxiden+ n+

Grow a thick oxide on topof the wafer.

p-

oxiden+ n+

Mask and etch to make contact holes

p-

oxiden+ n+

Put a layer of metal on chip.Be sure to fill in the holes!


Final product ...

Top-down view:

p-

oxiden+ n+

Vd Vs “The planar process”

Jean Hoerni,Fairchild Semiconductor1958


p-channel Transistors


p-Fet: Change polarity of everything

n-wellp+

Vwell = Vs = 1V

p+

Vd = 0Vdielectric

Vg = 0VI ⋲ µA

p-

New “n-well” mask

Vg

Vs

Vd

Isd

“Mobility” of holes is slowerthan electrons.

p-Fets drive less current than n-Fets, all else being equal


Device Equations


Recall: Our old “switch” model ...

A “on” p-FET fillsup the capacitor

with charge.

1/28/04 ©UCB Spring 2004CS152 / Kubiatowicz

Lec3.29

Delay Model:

CMOS


Lec3.30

Review: General C/L Cell Delay Model

° Combinational Cell (symbol) is fully specified by:• functional (input -> output) behavior

- truth-table, logic equation, VHDL

• load factor of each input

• critical propagation delay from each input to each output for each transition

- THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load

° Linear model composes

Cout

Vout

Cout

Delay

Va -> Vout

XX

X

X

X

X

Ccritical

delay per unit load

A

B

X

.

.

.

Combinational

Logic Cell

Internal Delay


Lec3.31

Basic Technology: CMOS

° CMOS: Complementary Metal Oxide Semiconductor• NMOS (N-Type Metal Oxide Semiconductor) transistors

• PMOS (P-Type Metal Oxide Semiconductor) transistors

° NMOS Transistor• Apply a HIGH (Vdd) to its gate

turns the transistor into a “conductor”

• Apply a LOW (GND) to its gateshuts off the conduction path

° PMOS Transistor• Apply a HIGH (Vdd) to its gate

shuts off the conduction path

• Apply a LOW (GND) to its gateturns the transistor into a “conductor”

Vdd = 5V

GND = 0v

Vdd = 5V

GND = 0v


Lec3.32

Basic Components: CMOS Inverter

Vdd

Circuit

° Inverter Operation

OutIn

SymbolPMOS

NMOS

In Out

Vdd

Open

Charge

VoutVdd

Vdd

Out

Open

Discharge

Vin

Vdd

Vdd

A “on” n-FET empties the

bucket.


Lec3.29

Delay Model:

CMOS


Lec3.30

Review: General C/L Cell Delay Model

° Combinational Cell (symbol) is fully specified by:• functional (input -> output) behavior

- truth-table, logic equation, VHDL

• load factor of each input

• critical propagation delay from each input to each output for each transition

- THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load

° Linear model composes

Cout

Vout

Cout

Delay

Va -> Vout

XX

X

X

X

X

Ccritical

delay per unit load

A

B

X

.

.

.

Combinational

Logic Cell

Internal Delay


Lec3.31

Basic Technology: CMOS

° CMOS: Complementary Metal Oxide Semiconductor• NMOS (N-Type Metal Oxide Semiconductor) transistors

• PMOS (P-Type Metal Oxide Semiconductor) transistors

° NMOS Transistor• Apply a HIGH (Vdd) to its gate

turns the transistor into a “conductor”

• Apply a LOW (GND) to its gateshuts off the conduction path

° PMOS Transistor• Apply a HIGH (Vdd) to its gate

shuts off the conduction path

• Apply a LOW (GND) to its gateturns the transistor into a “conductor”

Vdd = 5V

GND = 0v

Vdd = 5V

GND = 0v


Lec3.32

Basic Components: CMOS Inverter

Vdd

Circuit

° Inverter Operation

OutIn

SymbolPMOS

NMOS

In Out

Vdd

Open

Charge

VoutVdd

Vdd

Out

Open

Discharge

Vin

Vdd

Vdd

!"#$%&'())* ++,!-.)'/ 012-)34$5$%& 67&1'-)

!"#$%&'(#)*(+,%-$*".(/0

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“1”

“0”Time

Water level

!"#$%&'())* ++,!-.)'/ 012-)34$5$%& 67&1'-)

!"#$%&'(#)*(+,%-$*".(/0

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“0”

“1”

TimeWater level

We begin by modeling transistors that are “off”


Recall: Why diode current is I = exp(V) ...Wafer cross-section

n+

p-

Wafer doped p-type

n+ region

p- region At V = 0, “hill” too high for electrons to diffuse up.

V

Cathode: -

+

-

Anode: +

no carriers

depletion region

For holes, going “downhill” is hard. V controls hill.

electron

energy

depletion region


A simple model for “off” transistor ...

p-n+

Vd = 1V

n+

Vs = Vsub = 0Vdielectric

Vg = 0.2V

Vg

Vd

VsIds I ⋲ nA

n+ regionelectron

energy

n+ region

Current flows when electrons diffuse to the “gate wall” top

# electrons that reach top goes up as wall comesdown, implies Ids ~ exp(Vg)

Ids = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]

Io ~100fA, Vo = kT/q = 25mV, κ = 0.7

Vg exponential dependence

⋲1 if Vds > 70mV


----------

p-n+

Vd = 2V

n+dielectric

Vg = 1V+++++++++----------

A simple model for “on” transistor ...

Vs = Vsub = 0VI ⋲ µA Vg

Vd

VsIds

Ids = (carriers in channel) / (transit time)Q = CV f(length, velocity)

Ids = [(µεW)/(LD)] [Vgs -Vth] [Vds]

If Vds > Vgs - Vth, channel physics change :

Ids = [(µεW)/(2LD)] [Vgs -Vth]^2 W = transistor width, L = length,

D = capacitor plate distance µ is velocity, ε is C dilectric constant


Admin: Testing and Interfaces on Friday

Homework 1: due Friday 3/4Midterm 1: Thurs 3/17, 6PM to 9PM


Dynamic Memory (DRAM)


Recall: Capacitors in action

I = 0

Because the dielectric is an insulator, and does not conduct.

After circuit “settles” ...

Q = C V = C * 1.5 Volts (D cell)

Q: Charge stored on capacitorC: The capacitance of the device: function of device shape and type of dielectric.

+++ +++

--- ---

After battery is removed: +++ +++

--- ---Still, Q = C * 1.5 VoltsCapacitor “remembers” charge

1.5V


DRAM cell: 1 transistor, 1 capacitorVdd

Capacitor

“Word Line”“Bit Line”

p-

oxiden+ n+

oxide------

“Bit Line”

Word Line and Vdd run on “z-axis”

Word Line

Vdd

“Bit Line”

Vdd

Diode leakagecurrent.

Why Vcap values start out at ground.

Vcap


A 4 x 4 DRAM array (16 bits) ....


Invented after SRAM, by Robert Dennard

www.FreePatentsOnline.com




DRAM Circuit Challenge #1: Writing

Vdd

Vdd - Vth. Bad, we store less charge. Why do we not get Vdd?

VddVdd

Ids = [(µεW)/(2LD)] [Vgs -Vth]^2 , but “turns off” when Vgs <= Vth!

Vgs

Vc

Vgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops!


DRAM Challenge #2: Destructive Reads

Vdd

Bit Line

0 -> Vdd Vc -> 0

+++++++

+++++++ (stored charge from cell)

Word Line

Raising the word line removes the charge from every cell it connects too!

Must write back after each read.

Vgs

(initializedto a low voltage)


DRAM Circuit Challenge #3a: Sensing

Assume Ccell = 1 fF

Word line may have 2000 nFet drains,assume word line C of 100 fF, or 100*Ccell.

Ccell holds Q = Ccell*(Vdd-Vth)

When we dump this charge onto the word line, what voltage do we see?

dV = [Ccell*(Vdd-Vth)] / [100*Ccell]

dV = (Vdd-Vth) / 100 ⋲ tens of millivolts! In practice, scale array to get a 60mV signal.


DRAM Circuit Challenge #3b: Sensing

Compare the word line against the voltage on a “dummy” world line.

How do we reliably sense a 60mV signal?

[...]

“Dummy” word line.Cells hold no charge.

?-+Word line to sense

Dummy word line

“sense amp”


DRAM Challenge #4: Leakage ...

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Parasitic currents leak away charge.

Diode leakage ...

Solution: “Refresh”, by reading cells at regular intervals (tens of milliseconds)


DRAM Challenge #5: Cosmic Rays ...

Vdd

Bit Line+++++++

Word Line

p-

oxiden+ n+

oxide------

Cosmic ray hit.

Solution: Store extra bits to detect and correct random bit flips (ECC).

Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge!


DRAM Challenge 6: Yield

Solution: add extra word lines (i.e. 80 when you only need 64). During testing, find the bad word lines, and use high current to burn away “fuses” put on chip to remove them.

If one bit is bad, do we throw chip away?

[...]

Extra word lines.Used for “sparing”.


DRAM Challenge 7: Scaling

Each generation of IC technology, we shrink width and length of cell.

As will Q = Ccell*(Vdd-Vth)

As will voltage to be sensed on word line.

Recall: dV = [Ccell*(Vdd-Vth)] / [100*Ccell]

Solution: Constant Innovation of Cell Capacitors!

If we keep the same cell layout, Ccell will shrink too!


Poly-diffusion Ccell is ancient historyVdd

Capacitor

“Word Line”“Bit Line”

p-

oxiden+ n+

oxide------

“Bit Line”

Word Line and Vdd run on “z-axis”

Word Line

Vdd

“Bit Line”


Modern cells: “trench” capacitors


Modern cells: “stacked” capacitors


Lectures: Coming up next ...

Transistor equations, basic memory circuits.

Memory array structures and interfaces.

The memory hierarchy

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