CS 162Discussion Section

Week 6

Administrivia

• Project 2 Deadlines– Initial Design Due: 3/1– Review Due: 3/5– Code Due: 3/15

Project 2 Overview

• Part I – Implement file system calls– like create, open, read, write, close etc.

• Part II – Implement support for multiprogramming– Play with allocating memory, virtual memory

• Part III – Implement system calls– like exec, join and exit

• Part IV – Implement lottery scheduling

Recap

Why do we have a virtual address space?

Recap

How is a virtual address translated into a physical address?

Recap

Why do we have multiple levels of page tables?

What is the size of the page table in a 64bit system if each

page is 4K in size? – 16 PB

How many levels would you need if you had 1024 entry

page tables?

TLB

• Caching Applied to Address Translation

Caching

• caching is to store copies of data at places that can be accessed more quickly than accessing the original.

• Locality:– Temporal locality• Example: recently accessed files

– Spatial locality• Example: ls command

Memory Hierarchy

Image Source: http://www.sal.ksu.edu/faculty/tim/ossg/

Issues in Caching

• Cache Hit• Cache Miss• effective access time is defined with the

following equation:

T = P(cache hit)*(cost of hit) + P(cache miss)*(cost of miss)

Problem

What is the effective access time for TLB with 80% hit rate, 20ns TLB access time and 100 ns Memory access time (assume two-level page table that is not in L2 cache)?

Is there any way to make the page table smaller?

Linear inverted page tables

Hashed inverted page table

Hashed inverted page table

Design Issues in Caching

• The design of a caching mechanism needs to answer the following questions:

– How is a cache entry lookup performed? – If the data is not in the cache, which cache entry

should be replaced? – How does the cache copy maintain consistency with

the real version of data?

Types of Cache

• Direct Mapped Cache• Fully Associative Cache• N way Set Associative Cache

2-Way Associative Cache in TLB