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CS 3330: SEQ part 2 15 September 2016 1
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CS 3330: SEQ part 2
15 September 2016
1
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Recall: Timing
clock signalcomputecompute compute compute
compute new values between rising edges
registers, memories change at rising edges
register
nextvalue
currentvalue
DataMem.
address
next value(if writing)
current value(if reading)
2
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Recall: Computing components
MUX
abcd
output
select
ALU A OP B
A
B
MUXes — switches, select one of several inputs asoutput based on select signal.ALU — does the primary ‘math’ for instructions
3
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Recall: Stages
fetch — read instruction memory, split instruction
decode — read register file
execute — arithmetic (including of addresses)
memory — read or write data memory
write back — write to register file
PC update — compute next value of PC
4
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SEQ: Instruction Fetch
read instruction memory at PCsplit into seperate wires:
icode:ifun — opcoderA, rB — register numbersvalC — call target or mov displacement
compute next instruction address:valP — PC + (instr length)
5
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SEQ: Instruction Decode
read registersvalA, valB — register values
6
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SEQ: srcA, srcB
always read rA, rB?Problems:
push rApopcallret
extra signals: srcA, srcB — computed input register
MUX controlled by icode
7
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SEQ: Possible registers to readinstruction srcA srcBhalt, nop, jCC, irmovq none nonecmovCC, rrmovq rA nonemrmovq none rBrmmovq, OPq rA rBcall, ret none? %rsppushq, popq rA %rsp
MUX srcB
rB
%rsp
(none) F
logic functionicode
8
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SEQ: Possible registers to readinstruction srcA srcBhalt, nop, jCC, irmovq none nonecmovCC, rrmovq rA nonemrmovq none rBrmmovq, OPq rA rBcall, ret none? %rsppushq, popq rA %rsp
MUX srcB
rB
%rsp
(none) F
logic functionicode
8
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SEQ: Execute
perform ALU operation (add, sub, xor, neq)valE — ALU output
read prior condition codesCnd — condition codes based on ifun (instruction typefor jCC/cmovCC)
write new condition codes
9
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SEQ: ALU operations?
ALU inputs always valA, valB (register values)?no, inputs from instruction: (Displacement + rB)
MUX aluBvalBvalC
mrmovqrmmovq
no, constants: (rsp +/- 8)pushqpopqcallret
extra signals: aluA, aluBcomputed ALU input values
10
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SEQ: Memory
read or write data memoryvalM — value read from memory (if any)
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SEQ: Control Signals for Memory
read/write — write enable?Addr — address
mostly ALU outputtricky cases: popq, ret
Data — value to writemostly valBtricky cases: call, push
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SEQ: Write back
write registers
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SEQ: Control Signals for WB
two write inputs — two needed by popqvalM (memory output), valE (ALU output)
two register numbersdstM, dstE
write disable — use dummy register number 0xF
MUX dstErBF
%rsp
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SEQ: Update PC
choose value for PC next cycle (input to PCregister)
usually valP (following instruction)exceptions: call, jCC, ret
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A Starting Circuit
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
16
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A Starting Circuit
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
16
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A Starting Circuit
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
16
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Circuit: Setting MUXes
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
8
9
PC+2
M[PC+1]
8
9
R[8]
R[9]
aluA + aluB
M[PC+2]
add
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select when running addq %r8, %r9?Four MUXes — PC, dstM, dstE, aluAExercise: what do they select for rmmovq?
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Circuit: Setting MUXes
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
8
9
PC+2
M[PC+1]
8
9
R[8]
R[9]
aluA + aluB
M[PC+2]
add
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select when running addq %r8, %r9?
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select for rmmovq?
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Circuit: Setting MUXes
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
8
9
PC+2
M[PC+1]
8
9
R[8]
R[9]
aluA + aluB
M[PC+2]
add
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select when running addq %r8, %r9?
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select for rmmovq?
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Circuit: Setting MUXes
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
8
9
PC+2
M[PC+1]
8
9
R[8]
R[9]
aluA + aluB
M[PC+2]
add
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select when running addq %r8, %r9?
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select for rmmovq?
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Circuit: Setting MUXes
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
8
9
PC+2
M[PC+1]
8
9
R[8]
R[9]
aluA + aluB
M[PC+2]
add
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select when running addq %r8, %r9?
Four MUXes — PC, dstM, dstE, aluAExercise: what do they select for rmmovq?
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
00
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
00
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
00
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
00
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enough
pushq — no way to use rspcall —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enough
pushq — no way to use rsp
call —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enough
pushq — no way to use rspStep 1: add mux on srcB, dstEStep 2: add to aluA mux (allow constant)
call —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspStep 1: add mux on srcB, dstEStep 2: add to aluA mux (allow constant)
call —no way to connect PC to data memory
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspStep 1: add mux on srcB, dstEStep 2: add to aluA mux (allow constant)
call —no way to connect PC to data memoryadd mux on data memory data in (allow PC)
%rsp
%rsp8
rB%rsp
8
18
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Circuit: Incomplete (1)
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB
rrmovq, irmovq, mrmovq, rmmovq, jmp, call, pushq, retHow many of the above instructions can the above circuit not run?(Ignore undrawn mux selector inputs.)
rrmovq — no way to connect R[rA] to register file inputOption 1: mux on line to next R[dstE]Option 2: mux on input to aluB
0
0
irmovq — originally, no way to connect V to register file inputadding mux on aluB already enoughpushq — no way to use rspStep 1: add mux on srcB, dstEStep 2: add to aluA mux (allow constant)
call —no way to connect PC to data memoryadd mux on data memory data in (allow PC)
%rsp
%rsp8
rB%rsp
8
18
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Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
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Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?
Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
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Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?
Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
![Page 39: CS 3330: SEQ part 2 · 2016. 9. 15. · extra signals: aluA, aluB computed ALU input values 10. SEQ: Memory ... [PC+1] 8 9 R[8] R[9] aluA + aluB M[PC+2] add Four MUXes — PC, dstM,](https://reader034.documents.pub/reader034/viewer/2022052102/603d27029076482d05337594/html5/thumbnails/39.jpg)
Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?
Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.
What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
![Page 40: CS 3330: SEQ part 2 · 2016. 9. 15. · extra signals: aluA, aluB computed ALU input values 10. SEQ: Memory ... [PC+1] 8 9 R[8] R[9] aluA + aluB M[PC+2] add Four MUXes — PC, dstM,](https://reader034.documents.pub/reader034/viewer/2022052102/603d27029076482d05337594/html5/thumbnails/40.jpg)
Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.
What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
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Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.
What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
![Page 42: CS 3330: SEQ part 2 · 2016. 9. 15. · extra signals: aluA, aluB computed ALU input values 10. SEQ: Memory ... [PC+1] 8 9 R[8] R[9] aluA + aluB M[PC+2] add Four MUXes — PC, dstM,](https://reader034.documents.pub/reader034/viewer/2022052102/603d27029076482d05337594/html5/thumbnails/42.jpg)
Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
![Page 43: CS 3330: SEQ part 2 · 2016. 9. 15. · extra signals: aluA, aluB computed ALU input values 10. SEQ: Memory ... [PC+1] 8 9 R[8] R[9] aluA + aluB M[PC+2] add Four MUXes — PC, dstM,](https://reader034.documents.pub/reader034/viewer/2022052102/603d27029076482d05337594/html5/thumbnails/43.jpg)
Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
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Circuit: More complete
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
Seven MUXes — PC, srcB, dstM, dstE, aluA, aluB, data memory inSelectors for pushq?Instructions not covered: ret, popq, cmovCC, jCCMissing condition codes for cmovCC, jCC.What’s wrong with this implementation of popq?How could it be fixed?
add
What do we need to add for ret?
19
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Circuit
PC
Instr.Mem.
register filesrcAsrcBdstMdstE
next R[dstM]next R[dstE]
R[srcA]R[srcB]
ZF/SF
data mem.
0xF
0xF
rA
ALUaluA
aluBvalE
Data in
Addr inData out
write?
functionof opcode
add/subxor/and(functionof instr.)
instr.length+
rB%rsp
8
%rsp
%rsp0
20
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Stages: pushq/popq
stage pushq popq
fetch icode : ifun←M1[PC]rA : rB←M1[PC + 1]valP← PC + 2
icode : ifun←M1[PC]rA : rB←M1[PC + 1]valP← PC + 2
decode valA← R[rA]valB← R[%rsp]
valA← R[%rsp]valB← R[%rsp]
execute valE← valB + (−8) valE← valB + 8
memory M8[valE]← valA valM←M8[ valA ]
write back R[%rsp]← valE R[%rsp]← valER[rA]← valM
PC update PC← valP PC← valP21
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Stages: pushq/popq
stage pushq popq
fetch icode : ifun←M1[PC]rA : rB←M1[PC + 1]valP← PC + 2
icode : ifun←M1[PC]rA : rB←M1[PC + 1]valP← PC + 2
decode valA← R[rA]valB← R[%rsp]
valA← R[%rsp]valB← R[%rsp]
execute valE← valB + (−8) valE← valB + 8
memory M8[valE]← valA valM←M8[ valA ]
write back R[%rsp]← valE R[%rsp]← valER[rA]← valM
PC update PC← valP PC← valP21
![Page 48: CS 3330: SEQ part 2 · 2016. 9. 15. · extra signals: aluA, aluB computed ALU input values 10. SEQ: Memory ... [PC+1] 8 9 R[8] R[9] aluA + aluB M[PC+2] add Four MUXes — PC, dstM,](https://reader034.documents.pub/reader034/viewer/2022052102/603d27029076482d05337594/html5/thumbnails/48.jpg)
Conditional movs
absoluteValueJumps:andq %rdi, %rdijge same ; if rdi >= 0, goto sameirmovq $0, %rax ; rax <− 0subq %rdi, %rax ; rax <− rax (0) − rdiret
same: rrmovq %rdi, %raxret
absoluteValueCMov:irmovq $0, %raxsubq %rdi, %rax ; rax <− −rdiandq %rdi, %rdicmovge %rdi, %rax ; if (rdi > 0) rax <− rdiret
22
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Using condition codes: cmov
(always) 1(le) SF | ZF
(l) SF
cc(from instr)
rB0xF dstENOT
23
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Systematic constructionMUX OPq ret callq pushq …next PC PC + len memory out from instr PC + len …srcB rB — — %rsp …
24
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Summary
each instruction takes one cycle
divided into stages for design convenience
read values from previous cycle
send new values to state components
control what is sent with MUXes
25
