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CS61C:GreatIdeasinComputerArchitectureIntroductiontoAssemblyLanguageand
RISC-VInstructionSetArchitectureInstructors:
Krste Asanović &RandyH.Katzhttp://inst.eecs.Berkeley.edu/~cs61c
9/7/17 Fall2017- Lecture#5 1
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 2
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 3
LevelsofRepresentation/Interpretation
lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)
HighLevelLanguageProgram(e.g.,C)
AssemblyLanguageProgram(e.g.,RISC-V)
MachineLanguageProgram(RISC-V)
HardwareArchitectureDescription(e.g.,blockdiagrams)
Compiler
Assembler
MachineInterpretation
temp=v[k];v[k]=v[k+1];v[k+1]=temp;
0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111
ArchitectureImplementation
Anythingcanberepresentedasanumber,
i.e.,dataorinstructions
LogicCircuitDescription(CircuitSchematicDiagrams)
9/7/17 4
InstructionSetArchitecture(ISA)• JobofaCPU(CentralProcessingUnit,akaCore):execute
instructions• Instructions:CPU’sprimitivesoperations
– Likeasentence:operations(verbs)appliedtooperands(objects)processedinsequence…
– Withadditionaloperationstochangethesequence• CPUsbelongto“families,”eachimplementingitsownsetof
instructions• CPU’sparticularsetofinstructionsimplementsanInstructionSet
Architecture (ISA)– Examples:ARM,Intelx86,MIPS,RISC-V,IBM/MotorolaPowerPC(old
Mac),IntelIA64,...59/7/17
AssemblyLanguage High-LevelLanguage69/7/17
AssemblyLanguage High-LevelLanguage79/7/17
InstructionSetArchitectures• Earlytrend:addmoreinstructionstonewCPUsforelaborateoperations– VAXarchitecturehadaninstructiontomultiplypolynomials!
• RISCphilosophy(Cocke IBM,PattersonUCB,HennessyStanford,1980s)– ReducedInstructionSetComputing– Keeptheinstructionsetsmallandsimple,inordertobuildfasthardware
– Letsoftwaredocomplicatedoperationsbycomposingsimplerones
89/7/17
RISC-VGreenCard(intextbook)
99/7/17http://inst.eecs.berkeley.edu/~cs61c/resources/RISCV_Green_Sheet.pdf
InspiredbytheIBM360
“GreenCard”
109/7/17
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 11
WhatisRISC-V?• FifthgenerationofRISCdesignfromUCBerkeley• Ahigh-quality,license-free,royalty-freeRISCISAspecification• Experiencingrapiduptakeinbothindustryandacademia• Bothproprietaryandopen-sourcecoreimplementations• Supportedbygrowingsharedsoftwareecosystem• Appropriateforalllevelsofcomputingsystem,from
microcontrollerstosupercomputers– 32-bit,64-bit,and128-bitvariants(we’reusing32-bitinclass,textbook
uses64-bit)• Standardmaintainedbynon-profitRISC-VFoundation
129/7/17
FoundationMembers(60+)
13
Rumble Development
Platinum:
Gold,Silver,Auditors:
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 14
AssemblyVariables:Registers• UnlikeHLLlikeCorJava,assemblydoesnothave
variablesasyouknowandlovethem– Moreprimitive,closerwhatsimplehardwarecandirectly
support• Assemblyoperandsareobjectscalledregisters
– Limitednumberofspecialplacestoholdvalues,builtdirectlyintothehardware
– Operationscanonlybeperformedonthese!• Benefit:Sinceregistersaredirectlyinhardware,theyare
veryfast(fasterthan1ns- lighttravels1footin1ns!!!)
9/7/17 15
Processor
Control
Datapath
RegistersliveinsidetheProcessor
16
PC
RegistersArithmetic&LogicUnit
(ALU)
Memory Input
Output
Bytes
Enable?Read/Write
Address
WriteData
ReadData
Processor-MemoryInterface I/O-MemoryInterfaces
Program
Data
CS61c
NumberofRISC-VRegisters• Drawback:Sinceregistersareinhardware,therearealimited
numberofthem– Solution:RISC-Vcodemustbecarefullywrittentoefficientlyuseregisters
• 32registersinRISC-V,referredtobynumberx0 – x31– Registersarealsogivensymbolicnames,describedlater– Why32?Smallerisfaster,buttoosmallisbad.Goldilocksprinciple(“This
porridgeistoohot;Thisporridgeistoocold;thisporridgeisjustright”)• EachRISC-Vregisteris32bitswide(RV32 variantofRISC-VISA)
– Groupsof32bitscalledaword inRISC-VISA– P&HCoD textbookusesthe64-bitvariantRV64(explaindifferenceslater)
• x0 isspecial,alwaysholdsvaluezero– Soreallyonly31registersabletoholdvariablevalues
9/7/17 17
C,JavaVariablesvs.Registers• InC(andmostHLLs):
– Variablesdeclaredandgivenatype• Example: int fahr, celsius;
char a, b, c, d, e;
– EachvariablecanONLYrepresentavalueofthetypeitwasdeclared(e.g.,cannotmixandmatchint andchar variables)
• InAssemblyLanguage:– Registershavenotype;– Operation determineshowregistercontentsareinterpreted
9/7/17 18
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 19
RISC-VInstructionAssemblySyntax• Instructionshaveanopcode andoperands•E.g.,add x1, x2, x3 # x1 = x2 + x3
9/7/17 20
Operationcode(opcode)Destinationregister Secondoperandregister
Firstoperandregister
#isassemblycommentsyntax
AdditionandSubtractionofIntegers• AdditioninAssembly
– Example: add x1,x2,x3 (inRISC-V)– Equivalentto: a=b+c (inC)whereCvariables⇔ RISC-Vregistersare:
a⇔ x1,b⇔ x2,c⇔ x3• SubtractioninAssembly
– Example: sub x3,x4,x5 (inRISC-V)– Equivalentto: d=e- f (inC)whereCvariables⇔ RISC-Vregistersare:
d⇔ x3,e⇔ x4,f⇔ x5
9/7/17 21
AdditionandSubtractionofIntegersExample1
• HowtodothefollowingCstatement?a=b+c+d- e;
• Breakintomultipleinstructionsadd x10, x1, x2 # a_temp = b + cadd x10, x10, x3 # a_temp = a_temp + dsub x10, x10, x4 # a = a_temp - e
• AsinglelineofCmayturnintoseveralRISC-Vinstructions
9/7/17 22
Immediates• Immediates arenumericalconstants• Theyappearoftenincode,sotherearespecialinstructions
forthem• AddImmediate:
addi x3,x4,-10 (inRISC-V)f=g- 10 (inC)
whereRISC-Vregistersx3,x4 areassociatedwithCvariablesf,g• Syntaxsimilartoadd instruction,exceptthatlastargumentis
anumberinsteadofaregisteradd x3,x4,x0 (inRISC-V)f=g (inC)
9/7/17 23
Processor
Control
Datapath
DataTransfer:LoadfromandStoreto memory
PC
RegistersArithmetic&LogicUnit
(ALU)
Memory Input
Output
Bytes
Enable?Read/Write
AddressWriteData=StoretomemoryReadData=Loadfrommemory
Processor-MemoryInterface I/O-MemoryInterfaces
Program
Data
9/7/17 24
MuchlargerplaceToholdvalues,but
slowerthanregisters!
FastbutlimitedplaceToholdvalues
0123…
MemoryAddressesareinBytes• Datatypicallysmallerthan32bits,butrarelysmallerthan8bits
(e.g.,chartype)–worksfineifeverythingisamultipleof8bits• 8bitchunkiscalledabyte
(1word=4bytes)• Memoryaddressesarereally
inbytes,notwords• Wordaddressesare4bytes
apart– Wordaddressissameasaddressof
rightmostbyte– least-significantbyte(i.e.Little-endianconvention)
9/7/1725
Least-significantbyteinaword
04812…
15913…
261014…
371115…
3124 2316 158 70Least-significantbytegetsthesmallestaddress
Transferfrom MemorytoRegister• Ccode
int A[100];g = h + A[3];
• UsingLoadWord(lw)inRISC-V:lw x10,12(x13) #Reg x10getsA[3]add x11,x12,x10 #g=h+A[3]
Note: x13 – baseregister(pointertoA[0])12 – offsetinbytes
Offsetmustbeaconstantknownatassemblytime
9/7/17 26
TransferfromRegisterto Memory• Ccode
int A[100];A[10] = h + A[3];
• UsingStoreWord(sw)inRISC-V:lw x10,12(x13) #Tempreg x10getsA[3]add x10,x12,x10 #Tempreg x10getsh+A[3]sw x10,40(x13) #A[10]=h+A[3]
Note: x13 – baseregister(pointer)12,40 – offsetsinbytes
x13+12andx13+40mustbemultiplesof4
9/7/17 27
Loading and Storing Bytes• Inadditiontoworddatatransfers
(lw,sw),RISC-Vhasbytedatatransfers:– loadbyte:lb– storebyte:sb
• Sameformataslw,sw• E.g.,lb x10,3(x11)
– contentsofmemorylocationwithaddress=sumof“3”+contentsofregisterx11 iscopiedtothelowbytepositionofregisterx10.
28
byteloaded
zzz zzzzx
…is copied to “sign-extend”This bit
xxxx xxxx xxxx xxxx xxxx xxxxx10:
9/7/17
Yourturn
29
Answer x12
RED 0x5
GREEN 0xf
ORANGE 0x3
0xffffffff
addi x11,x0,0x3f5sw x11,0(x5)lb x12,1(x5)
Yourturn
30
Answer x12
RED 0x5
GREEN 0xf
ORANGE 0x3
0xffffffff
addi x11,x0,0x3f5sw x11,0(x5)lb x12,1(x5)
SpeedofRegistersvs.Memory• Giventhat
– Registers:32words(128Bytes)– Memory(DRAM):Billionsofbytes(2GBto8GBonlaptop)
• andphysicsdictates…– Smallerisfaster
• HowmuchfasterareregistersthanDRAM??• About100-500timesfaster!
– intermsoflatencyofoneaccess
319/7/17
Administrivia• HW#0duetomorrownight!• HW#1willbepublishedsoon
– Two-partCprogrammingassignment
• SmallGroupTutoringsignupswillbeoutrightaftertoday’slecture
• ThreeweekstoMidterm#1!
329/7/17
Break!
9/7/17 33
RISC-VLogicalInstructions
Logical operationsC
operatorsJava
operatorsRISC-V
instructionsBit-by-bit AND & & andBit-by-bit OR | | orBit-by-bit XOR ^ ^ xorShift left logical << << sllShift right logical >> >> srl
• Usefultooperateonfieldsofbitswithinaword− e.g.,characterswithinaword(8bits)
• Operationstopack/unpackbitsintowords• Calledlogicaloperations
9/7/17 34
Logical Shifting• ShiftLeftLogical:slli x11,x12,2 #x11=x12<<2
– Storeinx11 thevaluefromx12 shifted2bitstotheleft(theyfalloffend),inserting0’s onright;<<inC
Before:00000002hex00000000000000000000000000000010twoAfter: 00000008hex00000000000000000000000000001000two
Whatarithmeticeffectdoesshiftlefthave?
• ShiftRightLogical:srli isoppositeshift;>>–Zerobitsinsertedatleftofword,rightbitsshiftedoffend
9/7/17 35
ArithmeticShifting• Shiftrightarithmetic(srai)movesn bitstotheright(inserthigh-ordersignbitintoemptybits)
• Forexample,ifregisterx10contained11111111111111111111111111100111two=-25ten
• Ifexecutesra x10,x10,4,resultis:11111111111111111111111111111110two=-2ten
• Unfortunately,thisisNOTsameasdividingby2n− Failsforoddnegativenumbers− Carithmeticsemanticsisthatdivisionshouldroundtowards0
9/7/17 36
ComputerDecisionMaking• Basedoncomputation,dosomethingdifferent• Inprogramminglanguages:if-statement
• RISC-V:if-statementinstructionisbeq register1,register2,L1
means:gotostatementlabeledL1if(valueinregister1)==(valueinregister2)….otherwise,gotonextstatement
• beq standsforbranchifequal• Otherinstruction:bne forbranchifnotequal
9/7/17 37
TypesofBranches• Branch – changeofcontrolflow
• ConditionalBranch – changecontrolflowdependingonoutcomeofcomparison– branchifequal(beq)orbranchifnot equal(bne)– Alsobranchiflessthan(blt)andbranchifgreaterthanorequal
(bge)
• UnconditionalBranch – alwaysbranch– aRISC-Vinstructionforthis:jump(j)
9/7/17 38
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 39
Exampleif Statement• Assumingtranslationsbelow,compileif block
f→x10 g→x11 h→x12i →x13 j→x14
if (i == j) bne x13,x14,Exitf = g + h; add x10,x11,x12
Exit:• Mayneedtonegatebranchcondition9/7/17 40
Exampleif-else Statement• Assumingtranslationsbelow,compile
f→x10 g→x11 h→x12i →x13 j→x14
if (i == j) bne x13,x14,Else f = g + h; add x10,x11,x12
else j Exit f = g – h; Else: sub x10,x11,x12
Exit: 9/7/17 41
Magnitude Compares in RISC-V• Untilnow,we’veonlytestedequalities(==and!=inC);
Generalprogramsneedtotest<and>aswell.• RISC-Vmagnitude-comparebranches:
“BranchonLessThan”Syntax:blt reg1,reg2, labelMeaning: if(reg1<reg2)//treatregistersassignedintegers
goto label;• “BranchonLessThanUnsigned”
Syntax:bltu reg1,reg2, labelMeaning: if(reg1<reg2) //treatregistersasunsignedintegers
goto label;
9/7/17 42
CLoopMappedtoRISC-VAssemblyint A[20];int sum = 0;for (int i=0; i<20; i++)
sum += A[i];
add x9, x8, x0 # x9=&A[0]add x10, x0, x0 # sum=0add x11, x0, x0 # i=0Loop:
lw x12, 0(x9) # x12=A[i]add x10,x10,x12 # sum+=addi x9,x9,4 # &A[i++]addi x11,x11,1 # i++addi x13,x0,20 # x13=20blt x11,x13,Loop
43
Outline• AssemblyLanguage• RISC-VArchitecture• Registersvs.Variables• RISC-VInstructions• C-to-RISC-VPatterns• AndinConclusion…
9/7/17 44
InConclusion,…• Instructionsetarchitecture(ISA)specifiesthesetof
commands(instructions)acomputercanexecute• Hardwareregistersprovideafewveryfastvariablesfor
instructionstooperateon• RISC-VISArequiressoftwaretobreakcomplexoperationsinto
astringofsimpleinstructions,butenablesfaster,simplehardware
• Assemblycodeishuman-readableversionofcomputer’snativemachinecode,convertedtobinarybyanassembler
45