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CS 61C L34 Single Cycle CPU Control I (1) Garcia, Spring 2004 © UCB
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures
Lecture 34 – Single Cycle CPU Control I
2004-04-16
10.5 Quake?! NBC movie on May 3rd. Truth
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w/a strong temblor every few decades or less”
cnn.com/2004/TECH/science/04/14/san.andreas.awakens.ap
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CS 61C L34 Single Cycle CPU Control I (2) Garcia, Spring 2004 © UCB
Anatomy Review: 5 components of any Computer
Personal Computer
Processor
Computer
Control(“brain”)
Datapath(“brawn”)
Memory
(where programs, data live whenrunning)
Devices
Input
Output
Keyboard, Mouse
Display, Printer
Disk (where programs, data live whennot running)
Yesterday(& finish up)
Today
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CS 61C L34 Single Cycle CPU Control I (3) Garcia, Spring 2004 © UCB
Review: How to Design a Processor: step-by-step
• 1. Analyze instruction set architecture (ISA) => datapath requirements
• meaning of each instruction is given by the register transfers
• datapath must include storage element for ISA registers
• datapath must support each register transfer• 2. Select set of datapath components and establish clocking methodology
• 3. Assemble datapath meeting requirements• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
• 5. Assemble the control logic
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CS 61C L34 Single Cycle CPU Control I (4) Garcia, Spring 2004 © UCB
Register-Register Timing: One complete cycle
32Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
Clk
PC
Rs, Rt, Rd,Op, Func
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busA, BRegister File Access TimeOld Value New Value
busWALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
Register WriteOccurs Here
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CS 61C L34 Single Cycle CPU Control I (5) Garcia, Spring 2004 © UCB
3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]
32
Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs
ZeroE
xt
Mu
x
RtRdRegDst
Mux
3216imm16
ALUSrc
AL
U
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd?
immediate
016 1531
16 bits16 bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rt?
• Already defined 32-bit MUX; Zero Ext?
What about Rt register read??
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CS 61C L34 Single Cycle CPU Control I (6) Garcia, Spring 2004 © UCB
3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRd
RegDst
Exten
der
Mu
x
Mux
3216
imm16
ALUSrc
ExtOp
Clk
Data InWrEn
32
Adr
DataMemory
32
AL
U
MemWr Mu
x
W_Src
??
Rt?
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CS 61C L34 Single Cycle CPU Control I (7) Garcia, Spring 2004 © UCB
3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrcExtOp
Clk
Data InWrEn
32Adr
DataMemory
MemWr
AL
U
32
Mu
x
W_Src
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CS 61C L34 Single Cycle CPU Control I (8) Garcia, Spring 2004 © UCB
3f: The Branch Instruction
• beq rs, rt, imm16• mem[PC] Fetch the instruction from memory
• Equal = R[rs] == R[rt] Calculate the branch condition
• if (Equal) Calculate the next instruction’s address- PC = PC + 4 + ( SignExt(imm16) x 4 )
else- PC = PC + 4
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
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CS 61C L34 Single Cycle CPU Control I (9) Garcia, Spring 2004 © UCB
Datapath for Branch Operations• beq rs, rt, imm16
Datapath generates condition (equal)
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
imm16
PC
Clk
00
Ad
der
Mu
x
Ad
der
4nPC_sel
Clk
busW
RegWr
32
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs Rt
Eq
ual
?
Cond
PC
Ext
Inst Address
• Already MUX, adder, sign extend, zero
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CS 61C L34 Single Cycle CPU Control I (10) Garcia, Spring 2004 © UCB
Putting it All Together:A Single Cycle Datapath
imm
16
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_sel
PC
Ext
Adr
InstMemory
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CS 61C L34 Single Cycle CPU Control I (11) Garcia, Spring 2004 © UCB
An Abstract View of the Implementation
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
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CS 61C L34 Single Cycle CPU Control I (12) Garcia, Spring 2004 © UCB
An Abstract View of the Critical Path Critical Path (Load Operation) =
Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write
Clk
5
Rw Ra Rb32 32-bitRegisters
RdA
LU
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
16Imm
32
323232
A
B
Nex
t A
dd
ress
• This affects how much you can overclock your PC!
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CS 61C L34 Single Cycle CPU Control I (13) Garcia, Spring 2004 © UCB
An Abstract View of the Implementation
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
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CS 61C L34 Single Cycle CPU Control I (14) Garcia, Spring 2004 © UCB
Recap: A Single Cycle Datapath• Rs, Rt, Rd, Imed16 connected to datapath• We have everything except control signals
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrc
ExtOp
Mu
x
MemtoReg
Clk
Data InWrEn
32Adr
DataMemory
32
MemWrA
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
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CS 61C L34 Single Cycle CPU Control I (15) Garcia, Spring 2004 © UCB
Recap: Meaning of the Control Signals• nPC_MUX_sel: 0 PC <– PC + 4
1 PC <– PC + 4 + {SignExt(Im16) , 00 }
• Later in lecture: higher-level connection between mux and branch cond
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_MUX_sel
PC
Ext
imm
16
“n”=next
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CS 61C L34 Single Cycle CPU Control I (16) Garcia, Spring 2004 © UCB
Recap: Meaning of the Control Signals• ExtOp: “zero”, “sign”
• ALUsrc: 0 regB; 1 immed
• ALUctr: “add”, “sub”, “or”
° MemWr: 1 write memory° MemtoReg: 0 ALU; 1 Mem° RegDst: 0 “rt”; 1 “rd”° RegWr: 1 write register
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWr
AL
U
Equal
0
1
0
1
01
=
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CS 61C L34 Single Cycle CPU Control I (17) Garcia, Spring 2004 © UCB
Administrivia
• Final Exam will be here! (2050 VLSB)•Sat, 2004-05-22, 12:30–3:30pm
• Take EECS Survey this week! (results will be presented to Faculty; you CAN make a difference in your education & undergraduate experience)•http://eecssurvey.berkeley.edu
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CS 61C L34 Single Cycle CPU Control I (18) Garcia, Spring 2004 © UCB
RTL: The Add Instruction
add rd, rs, rt•MEM[PC] Fetch the instruction
from memory
•R[rd] = R[rs] + R[rt] The actual operation
•PC = PC + 4 Calculate the next instruction’s address
op rs rt rd shamt funct
061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
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CS 61C L34 Single Cycle CPU Control I (19) Garcia, Spring 2004 © UCB
Instruction Fetch Unit at the Beginning of Add• Fetch the instruction from Instruction memory: Instruction = MEM[PC]
• same for all instructions
PC
Ext
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_MUX_sel
imm
16Instruction<31:0>
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CS 61C L34 Single Cycle CPU Control I (20) Garcia, Spring 2004 © UCB
The Single Cycle Datapath during Add
32
ALUctr = Add
Clk
busW
RegWr = 1
32
32
busA
32
busB
55 5
Rw Ra Rb
32 32-bitRegisters
Rs
Rt
Rt
RdRegDst = 1
Exten
der
Mu
x
Mux
3216imm16
ALUSrc = 0
ExtOp = x
Mu
x
MemtoReg = 0
Clk
Data InWrEn
32
Adr
DataMemory
32
MemWr = 0A
LU
InstructionFetch Unit
Clk
Zero
Instruction<31:0>• R[rd] = R[rs] + R[rt]
0
1
0
1
01<
21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
op rs rt rd shamt funct
061116212631
nPC_sel= +4
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CS 61C L34 Single Cycle CPU Control I (21) Garcia, Spring 2004 © UCB
Instruction Fetch Unit at the End of Add• PC = PC + 4
• This is the same for all instructions except: Branch and Jump
Adr
InstMemory
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_MUX_sel
imm
16Instruction<31:0>
0
1
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CS 61C L34 Single Cycle CPU Control I (23) Garcia, Spring 2004 © UCB
°5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock
methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to
determine setting of control points that effects the register transfer.
• 5. Assemble the control logic
°Control is the hard part°MIPS makes that easier
• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates
Summary: Single cycle datapath
Control
Datapath
Memory
ProcessorInput
Output
