CS152 / Fall 2002 Lec 1.1

Computer Organization

Lecture 1

Course Introductionand the

Five Components of a Computer

Modified From the Lectures of Randy H. KatzUC Berkeley

Lec 1.2

Lecture Overview Intro to Computer Architecture (30 minutes)

Administrative Matters (5 minutes)

Course Style, Philosophy and Structure (15 min)

Break (5 min)

Organization and Anatomy of a Computer (25 min)

Lec 1.3

What is “Computer Architecture”?Computer Architecture =

Instruction Set Architecture +

Machine Organization + …

Lec 1.4

Instruction Set Architecture(subset of Computer Architecture)

“ ... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.”

– Amdahl, Blaaw, and Brooks, 1964

SOFTWARESOFTWARE• Organization of Programmable Storage

• Data Types & Data Structures: Encodings & Representations

• Instruction Set

• Instruction Formats

• Modes of Addressing and Accessing Data Items and Instructions

• Exceptional Conditions

Lec 1.5

Computer Architecture’s Changing Definition 1950s to 1960s Computer Architecture Course

• Computer Arithmetic

1970s to mid 1980s Computer Architecture Course

• Instruction Set Design, especially ISA appropriate for compilers

1990s Computer Architecture Course• Design of CPU, memory system, I/O system, Multi-

processors, Networks

2000s Computer Architecture Course: • Special purpose architectures, Functionally

reconfigurable, Special considerations for low power/mobile processing

Lec 1.6

The Instruction Set: a Critical Interface

instruction set

software

hardware

Lec 1.7

Example ISAs (Instruction Set Architectures) Digital Alpha (v1, v3) 1992-

97

HP PA-RISC (v1.1, v2.0) 1986-96

Sun Sparc (v8, v9) 1987-95

SGI MIPS (MIPS I, II, III, IV, V) 1986-96

Intel (8086,80286,80386, 1978-00

80486,Pentium, MMX, ...)Itanium/I64 2002-

Lec 1.8

MIPS R3000 Instruction Set Architecture(Summary) Instruction Categories

• Load/Store

• Computational

• Jump and Branch

• Floating Point

- coprocessor

• Memory Management

• Special

R0 - R31

PCHI

LO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Q: How many already familiar with MIPS ISA?

Lec 1.9

Organization Capabilities & performance

characteristics of principal functional units

• (e.g., Registers, ALU, Shifters, Logic Units, ...)

Ways in which these components are interconnected

Information flows between components

Logic and means by which suchinformation flow is controlled

Choreography of FUs to realize the ISA

Register Transfer Level (RTL) Description

Logic Designer's View

ISA Level

FUs & Interconnect

Lec 1.10

The Big Picture Since 1946 all computers have had 5

components

Control

Datapath

Memory

Processor

Input

Output

Lec 1.11

Example Organization TI SuperSPARCtm TMS390Z50 in Sun

SPARCstation20

Floating-point Unit

Integer Unit

InstCache

RefMMU

DataCache

StoreBuffer

Bus Interface

SuperSPARC

L2$

CC

MBus Module

MBus

L64852 MBus controlM-S Adapter

SBus

DRAM Controller

SBusDMA

SCSIEthernet

STDIO

serialkbdmouseaudioRTCBoot PROMFloppy

SBusCards

Lec 1.12

What is “Computer Architecture”?

Coordination of many levels of abstraction

Under a rapidly changing set of forces

Design, Measurement, and Evaluation

I/O systemInstr. Set Proc.

Compiler

OperatingSystem

Application

Digital DesignCircuit Design

Instruction Set Architecture

Firmware

Datapath & Control

Layout

Lec 1.13

Forces on Computer Architecture

ComputerArchitecture

Technology ProgrammingLanguages

OperatingSystems

History

Applications

Cleverness

Lec 1.14

i4004

i8086

i80386

Pentium

i80486

i80286

SU MIPS

R3010

R4400

R10000

1000

10000

100000

1000000

10000000

100000000

1965 1970 1975 1980 1985 1990 1995 2000 2005Transistors

i80x86

M68K

MIPS

Alpha

Technology

In ~1985 the single-chip processor (32-bit) and the single-board computer emerged

• workstations, personal computers, multiprocessors have been riding this wave since

In the 2002+ timeframe, these may well look like mainframes compared to single-chip computers (maybe 2 chips)

DRAM

Year Size

1980 64 Kb

1983 256 Kb

1986 1 Mb

1989 4 Mb

1992 16 Mb

1996 64 Mb

1999 256 Mb

2002 1 Gb

uP-Name

Microprocessor Logic DensityDRAM chip capacity

Lec 1.15

Technology Trends Imply Dramatic Change Processor

• Logic capacity: about 30% per year

• Clock rate: about 20% per year

Memory• DRAM capacity: about 60% per year (4x every 3

years)

• Memory speed: about 10% per year

• Cost per bit: improves about 25% per year

Disk• Capacity: about 60% per year

• Total data use: 100% per 9 months!

Network Bandwidth• Bandwidth increasing more than 100% per year!

Lec 1.16

Performance Trends

Microprocessors

Minicomputers

MainframesSupercomputers

1995

Year

19901970 1975 1980 1985

Lo

g o

f P

erfo

rma

nce

Lec 1.17

Applications and Languages

CAD, CAM, CAE, . . .

Lotus, DOS, . . .

Multimedia, . . .

The Web, . . .

JAVA, . . .

The Net => ubiquitous computing

???

Lec 1.18

Computers in the News: Sony Playstation 2000

As reported in Microprocessor Report, Vol 13, No. 5:• Emotion Engine: 6.2 GFLOPS, 75 million polygons per second

• Graphics Synthesizer: 2.4 Billion pixels per second

• Claim: Toy Story realism brought to games!

Lec 1.19

Where are We Going??

CS152Fall ’02

µProc60%/yr.(2X/1.5yr)

DRAM9%/yr.(2X/10 yrs)

1

10

100

1000

198

0 198

1 198

3 198

4 198

5 198

6 198

7 198

8 198

9 199

0 199

1 199

2 199

3 199

4 199

5 199

6 199

7 199

8 199

9 200

0

DRAM

CPU

198

2

Processor-MemoryPerformance Gap:(grows 50% / year)

Per

form

ance

Time

“Moore’s Law”

34-b it A LU

LO register(16x2 bits)

Load

HI

Cle

arH

I

Load

LO

M ultiplicandRegister

S h iftA ll

LoadM p

Extra

2 bits

3 232

LO [1 :0 ]

Result[H I] Result[LO]

32 32

Prev

LO[1]

Booth

Encoder E N C [0 ]

E N C [2 ]

"LO

[0]"

Con trolLog ic

InputM ultiplier

32

S ub /A dd

2

34

34

32

InputM ultiplicand

32=>34sig nEx

34

34x2 M U X

32=>34sig nEx

<<13 4

E N C [1 ]

M ulti x2 /x1

2

2HI register(16x2 bits)

2

01

3 4 ArithmeticSingle/multicycleDatapaths

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

IFetchDcd Exec Mem WB

Pipelining

Memory Systems

I/O

Lec 1.20

CS152: Course ContentComputer Architecture and Engineering

Instruction Set Design Computer Organization

Interfaces Hardware Components

Compiler/System View Logic Designer’s View

“Building Architect” “Construction Engineer”

Lec 1.21

CS 152: So What's In It For Me?

In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary.

• Insight into fast/slow operations that are easy/hard to implementation hardware

• Out-of-order execution and branch prediction

Experience with the design process in the context of a large complex (hardware) design.

• Functional Spec --> Control & Datapath --> Physical implementation

• Modern CAD tools

Designer's "Conceptual" toolbox

Lec 1.22

Conceptual Tool Box? Evaluation Techniques

Levels of translation (e.g., Compilation)

Levels of Interpretation (e.g., Microprogramming)

Hierarchy (e.g, registers, cache, mem, disk,tape)

Pipelining and Parallelism

Static / Dynamic Scheduling

Indirection and Address Translation

Synchronous and Asynchronous Control Transfer

Timing, Clocking, and Latching

CAD Programs, Hardware Description Languages, Simulation

Physical Building Blocks (e.g., CLA)

Understanding Technology Trends

Lec 1.23

Course Structure

Lectures (rough breakdown):• Review: 2 weeks on ISA, arithmetic• 1 1/2 weeks on technology, HDL, and arithmetic• 3 1/2 weeks on standard proc. design and pipelining• 2 weeks on memory and caches• 1 1/2 weeks on Memory and I/O• 2 weeks on special topics: low power, network as the

backplane, edge processors• 2 weeks exams, presentations

Design Intensive Class --- 100 hours per semester per studentMIPS Instruction Set ---> Standard-Cell implementation

Modern CAD System :Schematic capture and Simulation

Design Description Computer-based "breadboard"

• Behavior over time

• Before construction

Lec 1.24

Course Administration Instructor: Fu-Chiung Cheng

(fccheng@ttu.edu.tw) A5-707 Office

Hours(Tentative): Wens 11:00-12:00

TAs: TBA

Materials: http://www.cse.ttu.edu.tw/~cheng/courses/comporg.htm

Text: Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, 2nd Ed., 1998.

Hennessy and Patterson, Computer Architecture, A Quant-itative Approach, 3rd Ed., 2003. (recommended as an advanced reference)

Lec 1.25

Grading 4 Tests 40%

1 Midterm exam 25% (chap 1~4)

1 Final exam 30% (chap 1-8)

Participation in class 5%

Lec 1.26

Instructors’ Goals Show you how to understand modern computer

architecture in its rapidly changing form

Show you how to design by leading you through the process on challenging design problems

Learn how to test things

NOT to talk at you

So ...• ask questions

• come to office hours

• find me in the lab

• ...

Lec 1.27

Levels of Representation (61C Review)

High Level Language Program

Assembly Language Program

Machine Language Program

Control Signal Specification

Compiler

Assembler

Machine Interpretation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

lw$15, 0($2)lw$16, 4($2)sw $16,

0($2)sw $15,

4($2)0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

°°

ALUOP[0:3] <= InstReg[9:11] & MASK

Lec 1.28

Execution Cycle

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction

Obtain instruction from program storage

Determine required actions and instruction size

Locate and obtain operand data

Compute result value or status

Deposit results in storage for later use

Determine successor instruction

Lec 1.29

It’s All About CommunicationProc

CachesBusses

Memory

I/O Devices:

Controllers

adapters

DisksDisplaysKeyboards

Networks

All have interfaces & organizations

Um…. It’s the network stupid???!

Pentium III Chipset

Lec 1.30

Summary All computers consist of five components

• Processor: (1) datapath and (2) control

• (3) Memory

• (4) Input devices and (5) Output devices

Not all “memory” are created equally• Cache: fast (expensive) memory are placed closer to

the processor

• Main memory: less expensive memory--we can have more

Interfaces are where the problems are - between functional units and between the computer and the outside world

Need to design against constraints of performance, power, area and cost