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CS184b: Computer Architecture (Abstractions and Optimizations)

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CS184b: Computer Architecture (Abstractions and Optimizations). Day 16: May 12, 2003 Dataflow. Today. Dataflow Model Dataflow Basics Examples Basic Architecture Requirements. Functional. What is a functional language? What is a functional routine? Functional - PowerPoint PPT Presentation
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Caltech CS184 Spring2003 -- DeHon 1 CS184b: Computer Architecture (Abstractions and Optimizations) Day 16: May 12, 2003 Dataflow
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Page 1: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon1

CS184b:Computer Architecture

(Abstractions and Optimizations)

Day 16: May 12, 2003

Dataflow

Page 2: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon2

Today

• Dataflow Model

• Dataflow Basics

• Examples

• Basic Architecture Requirements

Page 3: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon3

Functional

• What is a functional language?

• What is a functional routine?

• Functional– Like a mathematical function– Given same inputs, always returns same

outputs– No state– No side effects

Page 4: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon4

Functional

Functional:

• F(x) = x * x;

• (define (f x) (* x x))

• int f(int x) { return(x * x); }

Page 5: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon5

Non-Functional

Non-functional:

• (define counter 0)

(define (next-number!)

(set! counter (+ counter 1))

counter)

• static int counter=0;

int increment () { return(++counter); }

Page 6: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon6

Dataflow

• Model of computation

• Contrast with Control flow

Page 7: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon7

Dataflow / Control Flow

Dataflow• Program is a graph

of operators• Operator consumes

tokens and produces tokens

• All operators run concurrently

Control flow• Program is a

sequence of operations

• Operator reads inputs and writes outputs into common store

• One operator runs at a time – Defines successor

Page 8: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon8

Token

• Data value with presence indication

Page 9: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon9

Operator

• Takes in one or more inputs

• Computes on the inputs

• Produces a result

• Logically self-timed– “Fires” only when input set present– Signals availability of output

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Caltech CS184 Spring2003 -- DeHon10

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Caltech CS184 Spring2003 -- DeHon11

Dataflow Graph

• Represents – computation sub-blocks– linkage

• Abstractly– controlled by data presence

Page 12: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon12

Dataflow Graph Example

Page 13: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon13

Straight-line Code

• Easily constructed into DAG– Same DAG saw before– No need to linearize

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Caltech CS184 Spring2003 -- DeHon14

Dataflow Graph

• Real problem is a graph

Day4

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Caltech CS184 Spring2003 -- DeHon15

Task Has Parallelism

MPY R3,R2,R2 MPY R4,R2,R5

MPY R3,R6,R3 ADD R4,R4,R7

ADD R4,R3,R4

Day4

Page 16: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon16

DF Exposes Freedom

• Exploit dynamic ordering of data arrival

• Saw aggressive control flow implementations had to exploit– Scoreboarding– OO issue

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Caltech CS184 Spring2003 -- DeHon17

Data Dependence

• Add Two Operators– Switch– Select

Page 18: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon18

Switch

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Caltech CS184 Spring2003 -- DeHon19

Select

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Caltech CS184 Spring2003 -- DeHon20

Constructing If-Then-Else

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Caltech CS184 Spring2003 -- DeHon21

Looping

• For (i=0;i<Limit;i++)

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Caltech CS184 Spring2003 -- DeHon22

Dataflow Graph

• Computation itself may construct / unfold parallelism– Loops– Procedure calls

• Semantics: create a new subgraph– Start as new thread– …procedures unfold as tree / dag– Not as a linear stack

– …examples shortly…

Page 23: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon23

Key Element of DF Control

• Synchronization on Data Presence

• Constructs:– Futures (language level)– I-structures (data structure)– Full-empty bits (implementation technique)

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Caltech CS184 Spring2003 -- DeHon24

I-Structure

• Array/object with full-empty bits on each field

• Allocated empty• Fill in value as compute• Strict access on empty

– Queue requester in structure– Send value to requester when written and

becomes full

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Caltech CS184 Spring2003 -- DeHon25

I-Structure

• Allows efficient “functional” updates to aggregate structures

• Can pass around pointers to objects

• Preserve ordering/determinacy

• E.g. arrays

Page 26: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon26

Future

• Future is a promise

• An indication that a value will be computed– And a handle for getting a handle on it

• Sometimes used as program construct

Page 27: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon27

Future

• Future computation immediately returns a future

• Future is a handle/pointer to result

• (define (vmult a b)

(cons (future (* (first a) (first b)))

(dot (rest a) (rest b))))

• [Version for wrighton on next slide]

Page 28: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon28

DF V-Mult product in C/Java

int [] vmult (int [] a, int [] b){

// consistency check on a.length, b.lengthint [] res = new int[a.length];for (int i=0;i<res.length;i++)

future res[i]=a[i]*b[i];– return (res);

}// assume int [] is an I-Structure

Page 29: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon29

I-Structure V-Mult Example

Two errors inthis version:1) fencepost on value for i2) Not delivering i to i-store

Page 30: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon30

I-Structure V-Mult Example

Correcteddataflow

Page 31: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon31

I-Structure V-Mult Example

N.B. this and remainder still have two errors.

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Caltech CS184 Spring2003 -- DeHon32

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon33

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon34

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon35

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon36

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon37

I-Structure V-Mult Example

Page 38: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon38

I-Structure V-Mult Example

Page 39: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon39

I-Structure V-Mult Example

Page 40: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon40

I-Structure V-Mult Example

Page 41: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon41

I-Structure V-Mult Example

Page 42: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon42

I-Structure V-Mult Example

Page 43: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon43

I-Structure V-Mult Example

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Caltech CS184 Spring2003 -- DeHon44

Fib(define (fib n)

(if (< n 2) 1 (+ (future (fib (- n 1))) (future (fib (- n 2))))))

int fib(int n) { if (n<2) return(1); else return ((future)fib(n-1) + (future)fib(n-2));}

Page 45: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon45

Fibonacci Example

Page 46: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon46

Fibonacci Example

Page 47: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon47

Fibonacci Example

Page 48: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon48

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon49

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon50

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon51

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon52

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon53

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon54

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon55

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon56

Fibonacci Example

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Caltech CS184 Spring2003 -- DeHon57

Futures

• Safe with functional routines– Create dataflow– In functional language, can wrap futures

around everything • Don’t need explicit future construct• Safe to put it anywhere

– Anywhere compiler deems worthwhile

• Can introduce non-determinacy with side-effecting routines– Not clear when operation completes

Page 58: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon58

Future/Side-Effect hazard

(define (decrement! a b) (set! a (- a b)) a)(print (* (future (decrement! c d)) (future (decrement! d e))))

int decrement (int &a, int &b) { *a=*a-*b; return(*a);}printf(“%d %d”,

(future)decrement(&c,&d),(future)decrement(&d,&e));

Page 59: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon59

Architecture Mechanisms?

• Thread spawn– Preferably lightweight

• Full/empty bits

• Pure functional dataflow– May exploit common namespace – Not need memory coherence in pure

functional values never change

Page 60: CS184b: Computer Architecture (Abstractions and Optimizations)

Caltech CS184 Spring2003 -- DeHon60

Big Ideas

• Model• Expose Parallelism

– Can have model that admits parallelism– Can have dynamic (hardware)

representation with parallelism exposed

• Tolerate latency with parallelism• Primitives

– Thread spawn– Synchronization: full/empty


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