CS1Q Computer SystemsLecture 12

Simon Gay

Lecture 12 CS1Q Computer Systems - Simon Gay

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Design of Sequential CircuitsThe systematic design of sequential circuits is not part of the syllabusof the course, so this lecture is for general interest. You are notexpected to know the material in this lecture for the exam.

By looking at design techniques for sequential circuits, we cancomplete the link between finite state machines and digital circuits.

Two examples:

1. a system which produces a sequence of outputs, driven by a clock2. the accepting finite state machine from Lecture 13 Slide 31.

Lecture 12 CS1Q Computer Systems - Simon Gay

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The Prime Number MachineThe first example is a circuit which outputs the sequence2, 3, 5, 7, 11, 13 as 4 bit binary numbers. The circuit will be driven bya clock, so that each clock pulse causes the output to change to the nextnumber in the sequence, returning to 2 after 13.

The sequence of outputs in binary is0010, 0011, 0101, 0111, 1011, 1101

There are two possible approaches to the design, and we will look atthem both.

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignIdea: store the output word in a 4 bit register.

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignIdea: store the output word in a 4 bit register.

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignAssume that we have a 4 bit register as a standard component.At each clock pulse, the values of the inputs D3,D2,D1,D0 are storedin the register, replacing the previous stored values. The outputsQ3,Q2,Q1,Q0 are the stored values. The Reset input sets the storedvalue to 0000, asynchronously.

Q3 Q2 Q1 Q0

D3 D2 D1 D0ResetClock

This register can be built from four D flipflops with reset inputs.

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignThe Reset input will set the stored value to 0000, but this is not one ofthe numbers in the sequence. Suppose we want Reset to make theoutput be 0010. A simple solution is to invert the Q1 output.

Q3 Q2 Q1 Q0

D3 D2 D1 D0ResetClock

not

outputThis means that the sequence ofvalues for Q3,Q2,Q1,Q0 is

0000, 0001, 0111, 0101, 1001, 1111

Lecture 12 CS1Q Computer Systems - Simon Gay

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Q3Q2Q1Q0D3D2D1D00 0 0 0 0 0 0 10 0 0 1 0 1 1 10 0 1 0 X X X X0 0 1 10 1 0 00 1 0 1 1 0 0 10 1 1 00 1 1 1 0 1 0 1

PNM First DesignAll we need to do now is design a combinational circuit which inputsQ3,Q2,Q1,Q0 and outputs D3,D2,D1,D0 (these are the values whichwill be stored in the register at the next clock cycle).

Q3Q2Q1Q0D3D2D1D01 0 0 01 0 0 1 1 1 1 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1 0 0 0 0

X X X X

X X X XX X X X

X X X X

X X X XX X X XX X X XX X X XX X X X

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignKarnaugh maps are a convenient way of handling the don’t care (X)values. Leaving the X squares blank, we can cover the 1s withrectangles which may also contain blank squares.

Karnaugh map for D3:

00 1 1

0 0

Q3 Q3

Q1

Q1

Q2 Q2Q2

Q0

Q0

Q0

)( 3213 QQQD

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignKarnaugh maps are a convenient way of handling the don’t care (X)values. Leaving the X squares blank, we can cover the 1s withrectangles which may also contain blank squares.

Karnaugh map for D2:

01 0 1

1 0

Q3 Q3

Q2 Q2Q2

Q0

Q0

31202 QQQQD Q0Q1

Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignKarnaugh maps are a convenient way of handling the don’t care (X)values. Leaving the X squares blank, we can cover the 1s withrectangles which may also contain blank squares.

Karnaugh map for D1:

01 0 1

0 0

Q3 Q3

Q2 Q2Q2

Q0

Q0

201 QQD Q0Q1

Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignKarnaugh maps are a convenient way of handling the don’t care (X)values. Leaving the X squares blank, we can cover the 1s withrectangles which may also contain blank squares.

Karnaugh map for D0:

11 1 1

1 0

Q3 Q3

Q2 Q2Q2

Q0

Q0

310 QQD Q0Q1

Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM First DesignWe end up with the following design (exercise: complete the circuit).

Q3 Q2 Q1 Q0

D3 D2 D1 D0ResetClock

combinational circuit

not

output

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second DesignThe first design works but has a couple of undesirable features:

• a 4 bit register is used, but there are only 6 states and therefore only 3 bits of storage should be necessary• it seems to be a fluke that the “Reset problem” can be solved so easily; this technique might be hard to generalise

The idea for the second design is to assume that we have a 3 bitcounter as a standard component. It has a clock input and anasynchronous reset input.

Q2 Q1 Q0Reset

Clock

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second DesignAssuming that we make use of states 0 to 5 (i.e. 000 to 101) of thecounter, we need a circuit to calculate the outputs P3,P2,P1,P0according to this truth table:

Q2Q1Q0P3 P2 P1 P00 0 0 0 0 1 00 0 1 0 0 1 10 1 0 0 1 0 10 1 11 0 01 0 1 1 1 0 11 1 01 1 1 X X X X

X X X X

1 0 1 10 1 1 1

Easy to design the circuit forP3,P2,P1,P0 (exercise).

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second Design

Karnaugh map for P3:

0 0 10 0 1

Q1

Q2Q2Q0

Q0

23 QP

Q1Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second Design

Karnaugh map for P2:

0 1 00 1 1

Q1

Q2Q22012 QQQP

Q1Q1

Q0

Q0

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second Design

Karnaugh map for P1:

1 0 11 1 0

Q1

Q2Q210201 QQQQP

Q1Q1

Q0

Q0

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second Design

Karnaugh map for P0:

0 1 11 1 1

Q1

Q2Q22100 QQQP

Q1Q1

Q0

Q0

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second DesignStates 110 and 111 are not needed. We would like the counter toadvance from state 101 to state 000.

This can be achieved by connecting the Reset input to a small circuitwhich will activate Reset when the state reaches 110.

If Reset is active high, then we can use 012 QQQR

If Reset is active low, then we need 012 QQQR

Lecture 12 CS1Q Computer Systems - Simon Gay

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PNM Second Design

reset circuit

Q2 Q1 Q0Reset

Clock

output circuit

P0P1P2

Exercise: complete the circuit.

Lecture 12 CS1Q Computer Systems - Simon Gay

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Accepting FSMRecall the transition diagram for the FSM which accepts binarysequences of the form 10101…01.

1

0

0 1

0,1

initial accepting0100

10

We’ll use the first design technique from the Prime Number Machine.

Lecture 12 CS1Q Computer Systems - Simon Gay

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Accepting FSMThere are 3 states so we need 2 bits of state information. We’ll use a2 bit register with outputs (stored values) Q1,Q0 and inputs D1,D0.

There is another input: the current bit from the sequence. Call this I.

At each clock cycle, D1,D0 (which willbe the next state) are calculated fromQ1,Q0 and I. Here is the truth table:

Q1Q0 I D1D00 0 0 1 00 0 1 0 10 1 0 0 00 1 11 0 01 0 1 1 01 1 01 1 1 X X

X X

1 01 0Exercise: work out formulae for D1,D0

as usual.

Lecture 12 CS1Q Computer Systems - Simon Gay

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Accepting FSM

Karnaugh map for D1:

1 1 1 00 1

Q1

IIQ0

Q0

IQIQQD 0011

Q1Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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Accepting FSM

Karnaugh map for D0:

0 0 0 10 0

Q1

IIQ0

Q0

IQQD 100

Q1Q1

Lecture 12 CS1Q Computer Systems - Simon Gay

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Accepting FSMThe final step is to add an output which will indicate whether or notthe FSM is in an accepting state.

As the accepting state is state 01, we have 01QQAccept

Q1 Q0

D1 D0ResetClock

combinational circuit

Accept

I