CS311-Computer OrganizationInput Output SystemsLecture 11 - 1 Lecture 11 Input Output Systems.

CS311-Computer Organization Input Output Systems Lecture 11 - 1

Lecture 11Lecture 11

Input Output SystemsInput Output SystemsLecture 11Lecture 11

Input Output SystemsInput Output Systems


Lecture 11:Lecture 11:Input/Output SystemInput/Output System

Lecture 11:Lecture 11:Input/Output SystemInput/Output System

In this lecture, we will study– Differences between I/O devices and memory– Basic I/O and I/O system with I/O controller– Bus– Protocol– Bus arbitration– I/O Interface– I/O Controller

» DMA, Channel– I/O System

» Memory mapped I/O» CPU controlled I/O» DMA controlled I/O» Channel controlled I/O» I/O Processor


I/O Device and MemoryI/O Device and MemoryI/O Device and MemoryI/O Device and Memory

• Input: Memory <= Input Device• Output: Output Device => Memory• Difference between I/O device and memory

– Operating Speed» In general, speed of I/O devices is slow than memory

– Unit of information» Memory: Word» I/O Device: Byte

– Autonomy» Memory is synchronized to CPU clock» I/O devices usually operate asynchronously since they are inherently

slow and distance apart from memory(sending CPU clock is expensive)

– Error rate» Error rate of I/O Device is much higher than memory


Input Output ControlInput Output ControlInput Output ControlInput Output Control

• I/O device controller– Controls the functions of I/O device – Sometimes it is integrated into the I/O device– e.g. Disk Controller

» Moves head to the desired location on the disk surface» Activates the head to read/write access» Sometimes one controller controls many disk drives

• I/O controller– Controls the data moves during I/O

» Notify an I/O device to initiate the operation and notify the completion of I/O operation to CPU

» Establish a connection between memory and an I/O device for data move» Checking the status of I/O operation» Access memory

– e.g. CPU, DMA controller, Channel controller, I/O processor, Front end processor


Basic I/O SystemBasic I/O SystemBasic I/O SystemBasic I/O System

Function of I/O Control is included in CPU

I/O Bus

CPU

Memory

MemoryBus

I/O Controller

I/0Device

I/O DevController

Interface

I/0Device

I/0Device

I/0Device

I/O DevController

I/O DevController

Interface Interface . . .


I/O System with I/O I/O System with I/O ControllerController

I/O System with I/O I/O System with I/O ControllerController

Memory

CPU

MemoryBus

I/OController I/O Bus

Interface

I/O DevController

I/ODev

Interface

I/O DevController

I/ODev

Interface

I/O DevController

I/ODev

I/ODev

I/OController

Interface

I/O DevController

I/ODev

Interface

I/O DevController

I/ODev

Interface

I/O DevController

I/ODev

I/ODev

I/O Bus


BusBusBusBus

Device Device Device Device...

BusDevice– Master Device» Acquires the right to use the bus» Performs control operation for actual data transmission

– Slave Device» Perform data transmit operation required by the master device

– In an instance when a data transmission takes place, one device is the master, and another is the slave. But the roles of device may change.– Some device can be a master in one instance and a slave in other instance


Bus ComponentsBus ComponentsBus ComponentsBus Components

• Data Bus• Address Bus• Control Bus

– Master sends Control signals and receives status signals

Control Bus

Address Bus

Data Bus

Master SlaveIn an economical system,One bus can be multiplexedto send Data and Address


Input Output BusInput Output BusInput Output BusInput Output Bus

Independent I/O Bus Memory-I/O Common Bus

I/ODev

I/ODev

I/ODev

...

CPU

Memory

Memory Bus

I/O Bus

CPU

MemoryI/ODev

I/ODev

I/ODev

Memory-I/O Common Bus


ProtocolProtocolProtocolProtocol

Protocol

Communication between devices with widely different characteristics require a communication rule called Protocol

– Synchronous Protocol– Asynchronous protocol


Synchronous ProtocolSynchronous ProtocolSynchronous ProtocolSynchronous Protocol

Synchronous Protocol– Master and Slave devices operate in a synchronized fashion– Information(bit, character, block) is synchronized with the clock pulse– Two different methods

» Master sends the clock pulse to the slave with the information> Suitable for short distance

» Master and Slave both have the synchronized clock pulse generators which are periodically synchronized> Suitable for long distance communications

Clock Pulse

Address

Data

R/WWAIT

Start Reading Read Complete


Asynchronous Protocol:Asynchronous Protocol:Serial TransmissionSerial Transmission

Asynchronous Protocol:Asynchronous Protocol:Serial TransmissionSerial Transmission

Asynchronous Serial Transmission Protocol

No transmissionStart Bit

More than 1 Stop BitsData Bits

0 1 0 1 1 1 0 0 1 1 1 ...

– Master and Slave devices must know » Number of bits in a unit of information(byte)» Transmission rate: bit/sec(Baud rate)


Asynchronous Protocol:Asynchronous Protocol:Parallel Transmission - Handshaking ProtocolParallel Transmission - Handshaking Protocol


Request Acknowledge

Req

Ack

Address Address Next Address

Data Data Next Data

R/W W Next R/W

Asynchronous Parallel Write Transmission

1

2

3

45




Asynchronous Parallel Read Transmission

Req

Ack

Address Address Next Address

Data Data Next Data

R/W R Next R/W

1

4

2

35


Bus ArbiterBus ArbiterBus ArbiterBus Arbiter

Bus Arbitration• In one instance, allow only one master to use the bus• Provides the fairness of the bus use amongst the devices

– e.g. priority

• 3 bus signals– Bus Request(BR): bus master sends BR to get the right to use the bus

– Bus Grant(BG): bus arbiter sends BG to requesting bus master as an authorization of the right to use the bus» A requestor amongst other requestors based on the established fairness rule(e.g.,

priority)

– Bus Busy(BB): the requestor who has the right to use the bus sends BB to notify that bus is in use

• 3 different bus arbiter structures– Centralized Parallel Arbitration

– Serial Arbitration or Daisy Chain arbitration

– Polling Arbitration


Centralized Parallel Centralized Parallel ArbitrationArbitration

Centralized Parallel Centralized Parallel ArbitrationArbitration

Device 0 Device 1 Device n-1. . .

Data Bus

BR BB BG BR BB BG BR BB BG

Bus Arbiter(Arbitration Algorithm)


Daisy Chain ArbitrationDaisy Chain ArbitrationDaisy Chain ArbitrationDaisy Chain Arbitration

Device 1BGi BGo

Device nBGi BGo

Data Bus

...

• Low priority device may have a danger of starvation• Serial with daisy chain: when there is a failure in the device in the middle of

the chain, or broken connection between BGi and BGo, the devices beyond the failing device cannot use the bus

BG

BR

BB

Bus Arbiter

Bus Priority(Arbitration Algorithm)

Device 0BGi BGo

Device 0BGi BGo


Polling ArbitrationPolling ArbitrationPolling ArbitrationPolling Arbitration

BR

BB

Polling Count

Bus Arbiter

When a bus requesting device gets its device number through polling count, it send BB to arbiter and use the bus.

Bus granting time may be too long.

Data Bus

Polling Count Order is the Priority order

Device 0 Device 1 . . . Device n


Input Output InterfaceInput Output InterfaceInput Output InterfaceInput Output Interface

Function of the I/O Interface• Recognizing address(device address or device code sent

by I/O instruction)• Resolving the characteristic differences between I/O

devices and Memory(CPU, I/O Controller)– Speed– Unit of information– Autonomy

» Highly functional I/O controllers» DMA, Channel, IOP, FEP

– Error rate


I/O Interface:I/O Interface:

Recognizing Device CodeRecognizing Device CodeI/O Interface:I/O Interface:

Recognizing Device CodeRecognizing Device Code

• Since there are many I/O devices, a unique device code is assigned to each device. It is received by the interface via address bus.

• In each interface, there is a device code decoder

Address Bus101101

1

DEV SEL

Device 101101 Interface

DEV SEL

0

Device 111111 Interface



Resolving Speed DifferenceResolving Speed DifferenceI/O Interface:I/O Interface:

Resolving Speed DifferenceResolving Speed Difference• Data Buffer and its associated flag• Receiving data from a slower device - Input

– Faster device cannot take away data in its own speed, it must wait until data is ready to be taken away

– When can it take away?– When the slower device puts the data in the Data Buffer, it

sets the Flag.– Data can be taken away from the data buffer when the Flag is

set and reset after the data is taken away for the next data input

Data Buffer

Flag

InputDevice

Input

Data Buffer

Flag

OutputDevice

Output• Sending data to a slower device - Output

– Faster device cannot send data in its own speed, it must wait until data is taken by the slower device

– Flag is set by the output device after the data in the Data Buffer is output so that the next data to be output

can be stored in the Data Buffer– New data can be stored in the Data Buffer only when the

Flag is set


I/O Interface:I/O Interface: Resolving Information Unit Resolving Information Unit

DifferenceDifference

I/O Interface:I/O Interface: Resolving Information Unit Resolving Information Unit

DifferenceDifference• Bit <=> Byte

• Data Buffer

– Input Data Buffer

» Serial-in Parallel-out

– Output Data Buffer

» Parallel-in Serial-out

Input Dev

Output Dev

Input to Memory(or CPU) in parallel

Output from Memory(or CPU)

Clock

Bit Counter

Flag

Set when 7



Resolving High Error RateResolving High Error RateI/O Interface:I/O Interface:

Resolving High Error RateResolving High Error Rate

• Parity bit– Even parity(even number of 1’s in data bits + parity bit)

1 0 1 1 1 0 1 10 0 1 1 0 1 1 0

1 0 1 1 1 0 1 00 0 1 1 0 1 1 1

– Odd parity(odd number of 1’s in data bits + parity bit)

• Echo Back• Retry and Timeout• EDC/ECC


Parity Generator/CheckerParity Generator/CheckerParity Generator/CheckerParity Generator/Checker

b0b1b2b3b4b5b6 b7

OddParity

EvenParity

Parity bit generator

EvenParityError

OddParityError

Parity checker


Input Output ControllerInput Output ControllerInput Output ControllerInput Output Controller

• Functions of I/O Controller– Establishing a connection between I/O Controller and

Memory – Storing Memory Address, Direction of data

transmission, and Data for memory access– Memory access– Establishing connection between I/O Interface and I/O

Controller– Data exchange with I/O device– Notify CPU of completion of I/O operation


DMAC as an I/O ControllerDMAC as an I/O ControllerDMAC as an I/O ControllerDMAC as an I/O Controller

CPU initialize DMAC I/O Device Address Function(R/W) Memory Starting Address Number of wordsI/O Dev to M connection for Cycle Steal by I/O Dev sends DMAR to DMAC DMAC sends MCR to CPU CPU sends MCG to DMAC DMAC send DMAG to I/O Dev DMAC send Addr and Func to M

A DMA input/output transfers a block, a contiguous words, of data(block)

MCR: Memory Cycle RequestMCG: Memory Cycle GrantDMAR: DMA RequestDMAG: DMA Grant

MCRMCGINT

DMARDMAG

I/O Dev

. . .

I/O Bus

data

DataBus

MemoryBus

AddrBus

ControlBus

R/W ADR DATA

CPU

Memory

DMAC


DMAC:DMAC:

Cycle StealCycle StealDMAC:DMAC:

Cycle StealCycle Steal

• CPU is continuously accessing memory, i.e., using memory cycles during program execution

• When a MCR is received, CPU gives the next memory cycle to DMAC so that the requesting I/O Device can use the memory cycle without significant delay that may cause lost data

CPU FET EXE FET EXE FET EXE FET EXE FET . . .M Cycle

DMAR

Interrupt

DMAC DMAC

FET EXE FET EXE FET …

Interrupt Routine

DMAR


DMAC:DMAC:

Data Buffer LogicData Buffer LogicDMAC:DMAC:

Data Buffer LogicData Buffer Logic

LDB/RDB LDB for output RDB for input Resets Byte CounterData Buffer Buffer Full when 4B Byte Counter = 3 SL for input from I/O bus SR for output to I/O bus

I/O Data Bus(8)Interface

MemoryData Buffer(32)8

Byte Counter

Control Logic

CPU

F

Memory Data Bus(32)Memory Control Bus

Data Buffer Logic

SL 8

=3Reset

I/O Data(32)

LDB/RDB

R/W MCR MCG

Input

Clock

OutputSR 8

Memory Bus


DMAC:DMAC:

Address Buffer and Address Buffer and Byte Counter LogicByte Counter Logic

DMAC:DMAC:

Address Buffer and Address Buffer and Byte Counter LogicByte Counter Logic

Receiving MCG form CPU, either RDB to move Data Buffer to M, or LDB to move M to Data BufferWhen a word in the block is done for input/output, Increment the address Decrement the word counterWhen WC = 0 Implies Completion of I/O Request Interrupt CPU

Address Buffer

Word Counter

Word Counter Logic

Address Buffer Logic

Memory

CPU

Control Logic

+1

-1

=0

INT

LDB/RDB

MCG


Channel ControllerChannel ControllerChannel ControllerChannel Controller

A channel Input/Output command transfers multiple blocks of data

CPU

Memory

Channel

Channel

I/O DC

I/O I/O

I/O

I/O I/O

Fixed Channel

CPU

Memory

Channel

Channel

Channel

I/O

I/O

I/O

Variable Channel


Selector and Multiplexer ChannelSelector and Multiplexer ChannelSelector and Multiplexer ChannelSelector and Multiplexer Channel

• Selector Channel– A channel dedicated to an I/O device usually for a high speed device

• Multiplexer Channel– A channel is time shared by several sub-channels, where a sub-channel s

erves for a slow I/O device. Thus a multiplexer channel serves several slow devices in the time multiplexed fashion

MultiplexerChannel

Sub-channel

Sub-channel

Sub-channel

I/O

I/O

I/O


Memory Mapped I/OMemory Mapped I/OMemory Mapped I/OMemory Mapped I/O

Input/Output Instruction No particular I/O instruction Use Load/Store instructions

When 9 <X<100 Load R, X for input Store R, X for output

Address Space Memory Space01

910 I/O Device 011 I/O Device 112 I/O Device 213 I/O Device 3

99 I/O Device 89100

n-1

I/ODev 0

I/ODev 1

I/ODev 2

I/ODev 89

.... . .


CPU Controlled I/O:CPU Controlled I/O:Programmed I/O - InputProgrammed I/O - Input

CPU Controlled I/O:CPU Controlled I/O:Programmed I/O - InputProgrammed I/O - Input

Most elementary I/O

– using B(busy) and D(done) flags[1] If B=1, Repeat [1];[2] B 1;[3] If D=0, Repeat [3];[4] R Input Data Buffer, D 0;[5] If there is more input data goto [3];[6] B 0, end;

Loop1: SBZ X /Skip if B=0JMP Loop1START X /B 1

Loop2: SDO X /Skip if D=1JMP Loop2IN R, X(M R)(n n-1)(if n>0, JMP Loop2)STOP X /B 0

Wasting a lot of cycles here,dependingon the speed of input device

B=0?

D=1?

B 1

End?

R Buf, D 0

B 0

n

n

n

y

y

y


CPU Controlled I/O:CPU Controlled I/O:Programmed I/O - OutputProgrammed I/O - Output

CPU Controlled I/O:CPU Controlled I/O:Programmed I/O - OutputProgrammed I/O - Output

Most elementary I/O

– using B(busy) and D(done) flagsB=0?

D=1?

B 1

End?

Buf R, D 0

B 0

n

n

n

y

y

y

[1] If B=1, Repeat [1];[2] B 1;[3] If D=0, Repeat [3];[4] Output Data Buffer R, D 0;[5] If there is more input data goto [3];[6] B 0, end;

Loop1: SBZ X /Skip if B=0JMP Loop1START X /B 1

Loop2: SDO X /Skip if D=1JMP Loop2OUT R, X(R M)(n n-1)(if n>0, JMP Loop2)STOP X /B 0

Wasting a lot of cycles here,dependingon the speed of input device


• Inefficient because CPU wastes a lot of cycles simply waiting for the slow I/O device to respond

• ExampleSpeed of CPU = 100 MIPS: Assume that identical instruction execution time

Input 1,000 characters from a keyboard, 1 character input time is 1 sec.

How many times SDO instruction in Loop2 will be executed per character input ?

100 MIPS implies that execution time of an instruction is 10-8 sec.

To simplify the problem, neglect the first three instructions and the last instruction since they are executed only once at the beginning and at the very last.

Let X be the number of executions of SDO instruction in Loop2.

Number of instruction executions for one character input becomes;

X + (X-1) + 4

Thus, (2X + 3) x 10-8 sec = 1 sec

Therefore, X = 5 x 107 , i.e., it will be executed 50 million times

CPU Controlled I/O:CPU Controlled I/O:Programmed I/OProgrammed I/O

CPU Controlled I/O:CPU Controlled I/O:Programmed I/OProgrammed I/O


Interrupt processed I/O allows to utilize the slow I/O device’s response time for the productive work, if there is any

CPU Controlled I/O:CPU Controlled I/O:Interrupt Processed I/OInterrupt Processed I/O

CPU Controlled I/O:CPU Controlled I/O:Interrupt Processed I/OInterrupt Processed I/O

Loop1: SBZ XJMP Loop1START X

Loop2: SDO XJMP Loop2IN R, X(M R)(n n-1)(if n>0, JMP Loop2)STOP X

Interrupt from X

Done in the interrupt processing routine

Loop1: SBZ XJMP Loop1START X

Loop3: ION X( Execute other tasks ………….. )

IN R, X(M R)(n n-1)(if n>0, JMP Loop3)STOP X

Waste of CPU cycles in programmed I/O

By allowing Device X to interrupt CPU whendata buffer is ready, this much CPU cycles can be utilized for the productive work.


DMAC Controlled I/ODMAC Controlled I/ODMAC Controlled I/ODMAC Controlled I/O

• CPU must send DMAC with– Direction of data transfer, i.e., Function(R or W)

– Starting address of the block

– Word count

– (Address of DMAC), I/O device address

– (Data block address in I/O device)

• Instruction– Output instruction if programmed I/O system is used

– ST instruction if memory mapped I/O system is used


Channel I/OChannel I/OChannel I/OChannel I/O

• Channel Program stored in memory– Channel program consists of a linked list of Channel Command

Words(CCW)

CC

W0

CC

W1

CC

W2

CC

Wn

CAW . . .

• Instruction– START Cn, Dn

• CAW• CCW

– Information provided to DMAC about data block and direction of transfer


Input Output ProcessorInput Output ProcessorInput Output ProcessorInput Output Processor

Input/Output Processor– Handling of Data to be input/output– Editing, Debugging, Validating, …– 2 kinds of I/O Processors(computers)

» Off-line I/O computers» On-line I/O computers

Off-line

On-line

CPU

Memory

CPU

Memory

Main Computer Dedicated I/O Computer Mag Tape Mag Tape

Disk Disk

Printer

GraphicsDev

Computer


On-line I/O ComputersOn-line I/O ComputersOn-line I/O ComputersOn-line I/O Computers

CPU CPU

Printer

GraphicsDev

ComputerDiskMemory Memory

Main Computer I/O Computer

CPUCPU

Printer

GraphicsDev

Computer

Main Computer I/O Computer

Memory Memory

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CS311-Computer OrganizationInput Output SystemsLecture 11 - 1 Lecture 11 Input Output Systems.

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