Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 1 Copyright Cirrus Logic, Inc. 1997 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CS4952/53 NTSC/PAL Digital Video Encoder Features Simultaneous composite and S-video output Supports RS170A and CCIR601 composite output timing Multi-standard support for NTSC-M, PAL (B, D, G, H, I, M, N, Combination N) Optional progressive scan @ MPEG2 field rates CCIR656 input mode supporting EAV/SAV codes and CCIR601 Master/Slave input modes Stable color subcarrier for MPEG2 systems NTSC closed caption encoder with interrupt Supports Macrovision copy protection in CS4953 version Host interface configurable for parallel or I 2 C compatible operation General purpose input and output pins Individual DAC power-down capability On-chip voltage reference generator On-chip color bar generator +5 volt only, CMOS, low power modes, tri-state DACs Description The CS4952/3 provides full conversion from YCbCr or YUV digital video formats into NTSC & PAL Composite and Y/C (S-video) analog video. Input formats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with sup- port for EAV/SAV codes. Output video can be formatted to be compatible with NTSC-M, or PAL B,D,G,H,I,M,N, and Combination N systems. Also supported is NTSC line 21 and line 284 closed captioning encoding. Four 9-bit DACs provide two channels for an S-Video out- put port and two composite video outputs. 2x oversampling reduces the output filter requirements and guarantees no DAC related modulation components within the spec- ified bandwidth of any of the supported video standards. Parallel or high speed I 2 C compatible control interfaces are provided for flexibility in system design. The parallel interface doubles as a general purpose I/O port when the CS4952/3 is in I 2 C mode to help conserve valuable board area. ORDERING INFORMATION CS4952/3-CL 44 pin PLCC CS4952/3-CQ 44 pin TQFP CLK SCL SDA PDAT[7:0] RD* WR* ADDR XTAL VD[7:0] HSYNC* VSYNC* FIELD INT RESET* C CVBS37 CVBS75 Y VREFIN VREFOUT ISET VAA GND TEST I C Interface 2 Host Parallel Interface Color Sub-carrier Synthesizer Video Formatter Video Timing Generator Control Registers Output Interpolate Chroma Amplifier Chroma Modulate Burst Insert Chroma Interpolate Luma Delay Luma Amplifier Sync Insert 9-Bit DAC Voltage Reference Current Reference 8 8 LPF LPF Output Interpolate LPF 9-Bit DAC 9-Bit DAC 9-Bit DAC Σ U, V Y OCT ‘97 DS223PP2
Transcript
Preliminary Product Information This document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.
1
Copyright Cirrus Logic, Inc. 1997(All Rights Reserved)
NTSC/PAL Digital Video EncoderFeatureslSimultaneous composite and S-video output lSupports RS170A and CCIR601 composite
output timinglMulti-standard support for NTSC-M, PAL (B, D,
G, H, I, M, N, Combination N)lOptional progressive scan @ MPEG2 field rates lCCIR656 input mode supporting EAV/SAV
codes and CCIR601 Master/Slave input modeslStable color subcarrier for MPEG2 systemslNTSC closed caption encoder with interruptlSupports Macrovision copy protection in
CS4953 versionlHost interface configurable for parallel or I2C
compatible operationlGeneral purpose input and output pinsl Individual DAC power-down capabilitylOn-chip voltage reference generatorlOn-chip color bar generatorl+5 volt only, CMOS, low power modes, tri-state
DACs
DescriptionThe CS4952/3 provides full conversion from YCbCr orYUV digital video formats into NTSC & PAL Compositeand Y/C (S-video) analog video. Input formats can be27 MHz 8-bit YUV, 8-bit YCbCr, or CCIR656 with sup-port for EAV/SAV codes. Output video can be formattedto be compatible with NTSC-M, or PAL B,D,G,H,I,M,N,and Combination N systems. Also supported is NTSCline 21 and line 284 closed captioning encoding.
Four 9-bit DACs provide two channels for an S-Video out-put port and two composite video outputs. 2x oversamplingreduces the output filter requirements and guaranteesno DAC related modulation components within the spec-ified bandwidth of any of the supported video standards.
Parallel or high speed I2C compatible control interfacesare provided for flexibility in system design. The parallelinterface doubles as a general purpose I/O port when theCS4952/3 is in I2C mode to help conserve valuableboard area.
PROGRAMMING ..............................................................................................................27Host Control Interface .............................................................................................27
Parameter Symbol Min Typ Max UnitsStatic PerformanceDAC Resolution - - 9 BitsDifferential Non-Linearity DNL -1 ±0.5 +1 LSBIntegral Non-Linearity INL -1 ±0.35 +1 LSBDynamic PerformanceDifferential Gain DB - 2 5 %Differential Phase DP - ±0.5 ±2 °Signal to Noise Ratio SNR -70 - - dB
Hue Accuracy HA - - 2 °
Saturation Accuracy SA - - 2 %
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A.C. CHARACTERISTICS:
Tch TclTisu
Tih
Toa
CLK
V[7:0]
HSYNC*/VSYNC*(Inputs)
HSYNC*/VSYNC*/CB/FIELD/INT
(Outputs)Figure 1. Video Pixel Data and Control Port Timing
Parameter Symbol Min Typ Max UnitsPixel Input and Control Port
Clock Pulse High Time Tch 14.82 18.52 22.58 ns
Clock Pulse Low Time Tcl 14.82 18.52 22.58 ns
Clock to Data Set-up Time Tisu 6 - - ns
Clock to Data Hold Time Tih 0 - - ns
Clock to Data Output Delay Toa - - 17 ns
Parameter Symbol Min Typ Max Units
I2C Host Port Timing
SCL Frequency Fclk 100 1000 KHz
Clock Pulse High Time Tsph 0.1 µs
Clock Pulse Low Time Tspl 0.7 µs
Hold Time (Start Condition) Tsh 100 ns
Setup Time (Start Condition) Tssu 100 ns
Data Setup Time Tsds 50 ns
Rise Time Tsr 1 µs
Fall Time Tsf 0.3 µs
Setup Time (Stop Condition) Tss 100 ns
Bus Free Time Tbuf 100 ns
Data Hold Time Tdh 0 ns
SCL Low to Data Out Valid Tvdo 600 ns
Figure 2. I2C Host Port Timing
SDA
SCL
Tsh
Tsr
Tspl Tsf Tssu
Tsph
Tsds Tsh TssTbuf
Tvdo
Tdh
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A.C. CHARACTERISTICS: (Continued)
ADDR
PDAT[7:0]
TrdhTas
Trpw
Trda
Trah
Trd
RD*
ADDR
PDAT[7:0]
Tas
Twpw
WR*
Twds
Twr
Twdh
Twac
RD*
WR*
TrecTrec
Parameter Symbol Min Typ Max Units8-bit Parallel Host Interface
Read Cycle Time Trd 60 - - ns
Read Pulse Width Trpw 30 - - ns
Address Setup Time Tas 3 - - ns
Read Address Hold Time Trah 10 - - ns
Read Data Access Time Trda - - 40 ns
Read Data Hold Time Trdh 10 - 50 ns
Write Recovery Time Twr 60 - - ns
Write Pulse Width Twpw 40 - - ns
Write Data Setup Time Twds 8 - - ns
Write Data Hold Time Twdh 3 - - ns
Write-Read/Read-Write Recovery Time Trec 50 - - ns
Address from Write Hold Time Twac 0 - - ns
8-bit Parallel Host Port Timing: Read Cycle
8-bit Parallel Host Port Timing: Address Write Cycle
8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle
The CS4952/3 is a complete multi-standard digitalvideo encoder implemented in current 5-volt onlyCMOS technology. CCIR601 or CCIR656 compli-ant digital video input can be converted intoNTSC-M, PAL B, PAL D, PAL G, PAL H, PAL I,PAL M, PAL N, or PAL N Argentina-compatibleanalog video. The CS4952/3 is designed to connectto MPEG1 and MPEG2 digital video decompres-sors without glue logic.
Two 9-bit DAC outputs provide high qualityS-Video analog output while two other 9-bit DACssimultaneously generate composite analog video.The CS4952/3 will accept 8-bit YCbCr or 8-bitYUV input data.
The CS4952/3 is completely configured and con-trolled via an 8-bit host interface port or an I2Ccompatible serial interface. This host port providesaccess and control of all CS4952/3 options and fea-tures like closed caption insertion, interrupts, etc.
In order to lower the end user set-top overall sys-tem costs, the CS4952/3 provides an internal volt-age reference which eliminates the requirement foran external discrete 3-pin voltage reference.
FUNCTIONAL DESCRIPTION
In the following subsections, the functions of theCS4952/3 will be described. The descriptions referto the block diagram on the cover page.
Video Timing Generator
All timing generation is accomplished via a27 MHz input applied to the CLK pin. TheCS4952/3 can also accept an optional color burstcrystal on the ADDR & XTAL pins. See section:Color Subcarrier Synthesizer (page 12), for furtherdetails.
The Video Timing Generator is responsible for or-chestrating most all of the other modules in the de-vice. It works in harmony with external sync inputtiming or by providing external sync timing out-
puts. It automatically disables color burst on appro-priate scan lines and generates serration andequalization pulses on appropriate scan lines.
The CS4952/3 is designed to function as a videotiming master or video timing slave. In both Masterand Slave Modes, all timing is sampled and assert-ed with the rising edge of the CLK pin.
In most cases the CS4952/3 will serve as the videotiming master. The master timing cannot be exter-nally altered other than through the host interfaceby changing the video display modes: PAL orNTSC and Progressive Scan. HSYNC, VSYNCand FIELD are configured as outputs for MasterMode. HSYNC can also be defined as a compositeblanking output signal in Master Mode. Exact hor-izontal and vertical display timing is addressed insection: Operational Description (page 14).
In Slave Mode HSYNC and VSYNC are config-ured as input pins and are used to initialize inde-pendent vertical and horizontal timing generatorsupon their respective falling edges. FIELD remainsan output in Slave Mode.
The CS4952/3 also provides a CCIR-656 SlaveMode where the video input stream contains EAVand SAV codes. In this case, proper HSYNCVSYNC timing is extracted automatically withoutaid from any inputs other than the V [7:0].CCIR-656 input data is sampled with the leadingedge of CLK. Slave Mode vertical and horizontaltiming derived via CCIR-656 or external hardwaremust be equivalent to timing generated by theCS4952/3 in Master Mode.
Video Input Formatter
The video input formatter translates YCbCr inputdata into YUV information, if necessary, and splitsthe luma and chroma information for filtering, scal-ing, and modulation.
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Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequencysynthesizer that produces the correct subcarrier fre-quency for NTSC or PAL. The CS4952/3 generatesthe color burst frequency based on the input CLK(27 MHz). Color burst accuracy and stability arelimited by the accuracy of the 27 MHz input. If thefrequency varies then the color burst frequency willalso vary accordingly.
In order to handle situations in which the CLK var-ies unacceptably, a local crystal frequency refer-ence may be used on the ADDR & XTAL devicepins. In this instance the input CLK is continuouslycompared with the external crystal reference inputand the internal timing of the CS4952/3 is automati-cally adjusted so that the color burst frequency re-mains close to the requirements.
Controls are provided for phase adjustment of theburst to permit color adjustment and phase com-pensation. Chroma hue control is provided by theCS4952/3 via a 10-bit Hue Control Register(HUE_LSB and H_MSB). Burst amplitude controlis also made available to the host via the 8-bit burstamplitude register (SC_AMP).
Chroma Path
The Video Input Formatter at conclusion delivers4:2:2 YUV outputs into separate chroma and lumadata paths. The chroma path will be discussed here.
The chroma output of the Video Input Formatter isdirected to a chroma low pass 19-tap FIR filter. Thefilter bandwidth is selected or the filter may be by-passed via the CONTROL_1 register. The pass-band of the filter is either 650 KHz or 1.3 MHz andthe passband ripple is less than or equal to 0.05 dB.The stopband for the 1.3 MHz selection begins at3 MHz with an attenuation of greater that 35 dB.The stopband for the 650 KHz selection beginsaround 1.1 MHz with an attenuation of greater than20 dB.
The output of the chroma low pass filter is connect-ed to the chroma interpolation filter where upsam-pling from 4:2:2 to 4:4:4 is accomplished. Thechroma digital data is fed to a quadrature modulatorwhere they are combined with the output from thesubcarrier synthesizer to produce the proper modu-lated chrominance signal.
Following chroma modulation the chroma datapasses through a variable gain amplifier where thechroma amplitude may be varied via the C_AMP8-bit host addressable register. The chroma then isinterpolated by a factor of 2 in order to operate theoutput DACs at 2 times the pixel rate. The interpo-lated filters help reduce the sinx/x roll-off for high-er frequencies and reduce the complexity of theexternal analog low pass filters.
Luma Path
Along with the chroma output path, the CS4952/3Video Input Formatter initiates a parallel luma datapath by directing the luma data to a digital delayline. The delay line is built as a digital FIFO wherethe depth of the FIFO replicates the clock perioddelay associated with the more complex chromapath.
Following the luma delay, the data is passedthrough a variable gain amplifier where the lumaDC values are modifiable via the Y_AMP register.
The output of the luma amplifier connects to thesync insertion block. Sync insertion is accom-plished by multiplexing into the luma data path thedifferent sync DC values at the appropriate times.The digital sync generator takes horizontal syncand vertical sync timing signals and generates theappropriate composite sync timing (including ver-tical equalization and serration pulses), blankinginformation, and burst flag. The sync edge ratesconform to RS-170A or CCIR specifications.
The luma only path is concluded via output interpo-lation by a factor of two in order to operate the out-put DACs at two times the pixel rate.
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Digital to Analog Converters
The CS4952/3 provides four complete simulta-neous 27 MHz DACs for analog video output: one9-bit for S-video chrominance, one 9-bit for S-Vid-eo luminance, and two 9-bit composite outputs.Both S-Video DACs are designed for 37.5 Ω over-all loads. The two composite 9-bit DACs are notidentical. One DAC is designed to drive 37.5 Ω de-rived from a double terminated 75 Ω circuit. Thesecond 9-bit DAC is targeted for an on-board localvideo connection where single point 75 Ω termina-tion is sufficient i.e. Ch3/4 RF modulators, videoamps, muxes.
The DACs can be put into tri-state mode via hostaddressable control register bits. Each of the fourDACs has its own separate DAC enable associatedwith it. In the disable mode, the 9-bit DACs sourceor sink zero current.
For lower power standby scenarios the CS4952/3also provides power shut-off control for the DACs.Each DAC has a separate DAC shut-off associatedwith it.
Voltage Reference
The CS4952/3 is equipped with an on-board1.235 V voltage reference generator used by theVideo DACs. For most requirements, the voltagereference output pin can be connected to the volt-age reference input pin along with a decoupling ca-pacitor. Otherwise the voltage reference input maybe connected to an external voltage reference.
Current Reference
The DAC output current per bit is derived in thecurrent reference block. The current step is speci-fied by the size of resistor place between the ISETcurrent reference pin and electrical ground. Thishas been optimized for 10kΩ (see “ISET” onpage 25 for more informmation on selecting theproper ISET value).
Host Interface
The CS4952/3 provides a parallel 8-bit data inter-face for overall configuration and control. The hostinterface uses active low read and write strobesalong with an active low address enable signal toprovide microprocessor compatible read and writecycles. Indirect host addressing to the CS4952/3 in-ternal registers is accomplished via an internal ad-dress register which is uniquely accessible via buswrite cycles with the host address enable signal as-serted.
The CS4952/3 also provides an I2C compatible se-rial interface for device configuration and control.This port can operate in standard or fast (400 KHz)modes. When in I2C mode, the parallel data inter-face PDAT [7:0] pins may be used as a general pur-pose I/O port controlled by the I2C interface.
Closed Caption Services
The CS4952/3 supports the generation of NTSCClosed Caption services. Line 21 and Line 284 cap-tioning can be generated and enabled independent-ly via a set of control registers. When enabled,clock run-in, start bit, and data bytes are automati-cally inserted at the appropriate video lines. A con-venient interrupt interface simplifies the softwareinterface between the host processor and theCS4952/3.
Control Registers
The control and configuration of the CS4952/3 isprimarily accomplished through the control regis-ter block. All of the control registers are uniquelyaddressable via the internal address register. Thecontrol register bits are initialized during a chip re-set.
See the detailed operation section of this data sheetfor all of the individual register bit allocations, bitoperational descriptions and initialization states.
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OPERATIONAL DESCRIPTION
Reset Hierarchy
The CS4952/3 is equipped with an active low asyn-chronous reset input pin RESET. RESET is used toinitialize the internal registers and the internal statemachines for subsequent default operation. See theelectrical and timing specification section of thisdata sheet for specific CS4952/3 chip reset andpower-on signaling timing requirements and re-strictions. All chip outputs are valid after a time pe-riod following RESET pin low.
When the RESET pin is held low, the host interfacein the CS4952/3 is disabled and will not respond tohost initiated bus cycles.
A reset initializes the CS4952/3 internal registers totheir default values as described by Table 5. In thedefault state, the CS4952/53 video DACs are dis-abled and the device is configured to internally pro-vide blue field video data to the DACs (any inputdata present on the V [7:0] pins is ignored). Other-wise the CS4952/53 registers are configured forNTSC-M CCIR601 output operation. At a mini-mum, the DAC register (0x04) must be written (toenable the DACs) and the IN_MODE bit of theCONTROL_0 register (0x01) must be set (to en-able CCIR601 data input on V [7:0]) for theCS4952/53 to become operational after RESET.
Video Timing
Slave Mode Input Interface
In Slave Mode, the CS4952/3 takes VSYNC andHSYNC as inputs. Slave Mode is the default fol-lowing a reset and is changed to Master Mode via acontol register bit (CONTROL_0 [4]). TheCS4952/3 is limited to CCIR601 horizontal andvertical input timing. All clocking in the CS4952/3is generated from the CLK pin. In Slave Mode theSync Generator uses externally provided horizontaland vertical sync signals to synchronize the internaltiming of the CS4952/3.
Video data that is sent to the CS4952/3 must besynchronized to the horizontal and vertical syncsignals. Figure 6 illustrates horizontal timing forCCIR601 input in Slave Mode. Note that theCS4952/3 expects to receive the first active pixeldata on clock cycle 245 (NTSC) when bitSYNC_DLY=0 in the CONTROL_2 Register(Ox02). When SYNC_DLY=1, it expects the firstactive pixel data on clock cycle 246 (NTSC).
Master Mode Input Interface
The CS4952/3 defaults to Slave Mode followingRESET high but may be switched into MasterMode via the MSTR bit in the CONTROL_0 Reg-ister (0x00). In Master Mode, the CS4952/3 usesthe VSYNC, HSYNC and FIELD device pins as
outputs to schedule the proper external delivery ofdigital video into the V [7:0] pins. Figure 7 illus-trates horizontal timing for CCIR601 input in Mas-ter Mode. Note that the CS4952/3 expects toreceive the first active pixel data on clock cycle 245(NTSC) when bit SYNC_DLY=0 in theCONTROL_2 Register (0x02). WhenSYNC_DLY=1, it expects the first active pixel dataon clock cycle 246 (NTSC).
Vertical Timing
The CS4952/3 can be selected through theCONTROL_0 register (0x00) to operate in fourdifferent timing modes: PAL which is 625 verticallines 25 frames per second interlaced, NTSC whichis 525 vertical lines 30 frames per second interlacedand both PAL and NTSC again but in ProgressiveScan where the display is non-interlaced.
The CS4952/3 conforms to standard digital decom-pression dimensions and does not process digitalinput data for the active analog video half lines asthey are typically in the over/underscan region oftelevisions. For NTSC, 240 active lines total perfield are processed and for PAL 288 active lines to-tal per field. Frame vertical dimensions are 480lines for NTSC and 576 lines for PAL. Table 1
specifies active line numbers for both NTSC andPAL. Refer to Figure 8 for HSYNC, VSYNC andFIELD signal timing.
Table 1. Vertical Timing
Horizontal Timing
HSYNC is used to synchronize the horizontal inputto output timing in order to provide proper horizon-tal alignment. HSYNC defaults to an input pin fol-lowing RESET but switches to output in MasterMode (CONTROL_0 [4] = 1). Horizontal timing isreferenced to HSYNC transitioning low. For activevideo lines, digital video input is to be applied tothe V [7:0] inputs 244 (NTSC) or 264 (PAL), CLKperiods following HSYNC going low to determinethe horizontal alignment of the active video.
NTSC Progressive-Scan NA 22-261PAL Progressive-Scan NA 23-310
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NTSC Vertical Timing (odd field)
Line
HSYNC*
VSYNC*
FIELD
3 4 5 6 7 8 9 10
NTSC Vertical Timing (even field)
Line
HSYNC*
VSYNC*
FIELD
PAL Vertical Timing (odd field)
Line
HSYNC*
VSYNC*
FIELD
PAL Vertical Timing (even field)
Line
HSYNC*
VSYNC*
FIELD
264 265 266 267 268 269 270 271
265 1 2 3 4 5 6 7
311 312 313 314 315 316 317 318
Figure 8. Vertical Timing
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NTSC Interlaced
The CS4952/3 supports NTSC-M and PAL-Mmodes where there are 525 total lines per frame andtwo fixed 262.5 line fields per frame and 30 totalframes occuring per second. Please reference Fig-ure 9 for NTSC interlaced vertical timing. Eachfield consists of 1 line for closed caption, 240 ac-tive lines of video plus 21.5 lines of blanking.
VSYNC field one transistions low at the beginningof line 4 and will remain low for 3 lines or (858 x 3)2574 pixel cycles. The CS4952/3 exclusively re-serves line 21 of field one for closed caption inser-tion. Digital video input is expected to be deliveredto the CS4952/3 V [7:0] pins for 240 lines begin-ning on active video lines 22 and continuing
through line 261. VSYNC field two transistionslow in the middle of line 266 and stays low for 3lines times and transitions high in the middle of line269. The CS4952/3 exclusively reserves line 284 offield two for closed caption insertion. Video inputon the V [7:0] pins is expected between lines 285through line 525.
PAL Interlaced
The CS4952/3 supports PAL modes B, D, G, H, I,N, and Combination N where there are 625 totallines per frame and two fixed 312.5 line fields perframe and 25 total frames occuring per second.Please reference Figure 10 for PAL interlaced ver-tical timing. Each field consists of 288 active linesof video plus 24.5 lines of blanking.
Figure 9. NTSC Video Interlaced Timming
523 524 525 1 2 3 4 5 6 7 8 9
VSYNC* Drops
10 22
Analog Field 1
261 262 263
Analog Field 2
285284272271270269268267266265264
523 524 525 1 2 3 4 5 6 7 8 9
VSYNC* Drops
10 22
Analog Field 3
261 262 263
Analog Field 4
285284272271270269268267266265264
Burst begins with positive half-cycle Burst begins with negative half-cycle
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621 622 623
Analog Field 1
Burst Phase = 135 degrees relative to U Burst Phase = 225 degrees relative to U
VSYNC will transition low to begin field one andwill remain low for 2.5 lines or (864 x 2.5) 2160pixel cycles. Digital video input is expected to bedelivered to the CS4952/3 V [7:0] pins for 287lines beginning on active video line 24 and continu-ing through line 310.
Field two begins with VSYNC transitioning lowafter 312.5 lines from the beginning of field one.VSYNC stays low for 2.5 lines times and transi-tions high with the beginning of line 315. Video in-put on the V [7:0] pins is expected between line 336through line 622.
Progressive Scan
The CS4952/3 supports a progessive scan modewhere the video output is non-interlaced. This isaccomplished by displaying only the first videofield for NTSC or PAL. To preserve exact MPEG-2frame rates of 30 and 25 per second, the CS4952/3displays the same first field repetitively but alter-nately varies the field times. Other digital video en-coders commonly support progressive scan byrepetitively displaying a 262 line field (524/525lines for NTSC). In the long run this method isflawed in that over time, the output display rate willoverrun a system clock locked MPEG-2 decom-pressor and display a field twice every 8.75 sec-onds.
PAL Progressive Scan
VSYNC will transistion low to begin field one andwill remain low for for 2.5 lines or (864 x 2.5) 2160pixel times. Please reference Figure 11 for PALnon-interlaced timing. Digital video input is ex-pected to be delivered to the CS4952/3 V [7:0] pinsfor 288 lines beginning on active video line 23 andcontinuing through line 309.
Field two begins with VSYNC transitioning lowafter 312 lines from the beginning of field one.
VSYNC stays low for 2.5 line times and transitionshigh during the middle of line 315. Video input onthe V [7:0] pins is expected between line 335through line 622. Field two is 313 lines long whilefield one is 312.
NTSC Progressive Scan
VSYNC will transition low at line 4 to begin fieldone and will remain low for 3 lines or (858 x 3)2574 pixel times. Please reference Figure 12 forNTSC interlaced timing. Digital video input is ex-pected to be delivered to the CS4952/3 V [7:0] pinsfor 240 lines beginning on active video line 22 andcontinuing through line 261.
Field two begins with VSYNC transitioning low atline 266. VSYNC stays low for 2.5 line times andtransitions high during the middle of line 268. Vid-eo input on the V [7:0] pins is expected betweenline 284 through line 524. Field two is 263 lineslong while field one is 262.
CCIR-656
The CS4952/3 supports an additional Slave Modefeature that is selectable through the CCIR601 bitof the CONTROL_0 register. The CCIR-656 slavefeature is unique because the horizontal and verti-cal timing and digital video are combined into asingle 8-bit 27 MHz input. With CCIR-656 thereare no horizontal and vertical input or outputstrobes, only 8-bit 27 MHz active CbYCrY datawith start and end of video codes being implement-ed with reserved 00 and FF code sequences withinthe video feed. As with all modes, V [7:0] are sam-pled with the rising edge of CLK. The CS4952/3expects the digital CCIR-656 stream to be errorfree. The FIELD output toggles as with nonCCIR-656 input. CCIR-656 input timing is illus-trated in Figure 13.
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309 310 311
Analog Field 1
Burst Phase = 135 degrees relative to U Burst Phase = 225 degrees relative to U
312 313 1 2 3 4 5 6 7 23 24
309
Analog Field 2
308 311 312
VSYNC* Drops
1 2 3 4 5 6 7 23 24310
309 310 311
Analog Field 3
312 313 1 2 3 4 5 6 7 23 24
309
Analog Field 4
308 311 312 1 2 3 4 5 6 7 23 24310
Figure 11. PAL Video Non-Interlaced Progressive Scan Timing
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261 262 1 2 3 4 5 6 7 8 9
Start ofVSYNC
10 22
Field 1
Burst begins with positive half-cycle Burst begins with negative half-cycle
Burst phase = reference phase = 180 relative to B-Y0 Burst phase = reference phase = 180 relative to B-Y0
262 263 1 2 3 4 5 6 7 8 9 10 22
261 262 1 2 3 4 5 6 7 8 9 10 22
262 263 1 2 3 4 5 6 7 8 9 10 22
Field 2
Field 3
Field 4
Start ofVSYNC
Figure 12. NTSC Video Non-Interlaced Progressive Scan Timing
The CS4952/3 provides 2 different digital video in-put modes that are selectable through theIN_MODE bit of the CONTROL_0 register.
In mode 0 and upon RESET, the CS4952/3 defaultsto output a solid color (1 of a possible of 256 col-ors). The background color is selected by writingthe BKG_COLOR register (0x08). The colorspaceof the register is RGB 3:3:2 and is unaffected bygamma correction. The default color following RE-SET is blue.
In mode 1 the CS4952/3 supports a single 8-bit27 MHz CbYCrY source as input on the V [7:0]pins. Input video timing can be CCIR601 master orslave and progressive scan.
Multi-standard Output Format Modes
The CS4952/53 supports a wide range of outputformats compatible with worldwide broadcast stan-dards. These formats include NTSC-M,PAL-B/D/G/H/I, PAL-M, PAL-N and PAL Combi-nation N (PAL-Nc) which is the broadcast standardused in Argentina. After RESET, the CS4952/53 de-faults to NTSC-M operation with CCIR601 analogtiming. NTSC-M can also be supported in the Japa-nese format by turning off the 7.5 IRE pedestalthrough the PED bit in the CONTROL_1 register(0x01).
Output formats are configured by writing controlregisters as shown in Table 2.
Subcarrier Generation
The CS4952/3 automatically synthesizes NTSCand PAL color subcarrier clocks using the CLK fre-quency and four control registers(SC_SYNTH0/1/2/3). The NTSC subcarrier syn-thesizer is reset every four fields and every eightfields for PAL.
The SC_SYNTH0/1/2/3 registers used togetherprovide a 32-bit value which defaults to NTSC val-ues of 43E0F83Eh following reset.
Table 3 indicates the 32-bit value required for thedifferent broadcast formats.
Subcarrier Compensation
Since the subcarrier is synthesized from CLK thesubcarrier frequency error will track the clock fre-quency error. If the input clock has a tolerance of200 ppm then the resulting subcarrier will alsohave a tolerance of 200 ppm. Per the NTSC speci-fication the final subcarrier tolerance is ±10 Hzwhich is more like 3 ppm. Care must be taken in se-lecting a suitable clock source.
In MPEG-2 system environments the clock is actu-ally recovered from the data stream. In these casesthe recovered clock can be 27 MHz ±50 ppm or
±1350 Hz. It varies per television but in many casesgiven an MPEG-2 system clock of 27 MHz±1350 Hz the resultant color subcarrier producedwill be outside of the televisions ability to compen-sate and the chrominance information will not bedisplayed (black and white picture only).
The CS4952/3 is designed to provide automaticcompensation for an excessively inaccurateMPEG-2 system clock. Sub-carrier compensationis enabled through the XTAL bit of theCONTROL_2 register. When enabled theCS4952/3 will utilize a common quartz color burstcrystal (3.579545 MHz ±50 ppm for NTSC) at-tached to the ADDR and XTAL pins to automati-cally compare and compensate the color subcarriersynthesis process. Use of the ADDR and XTALpins requires that the host interface is configuredfor I2C operation.
Closed Caption Insertion
The CS4952/3 is capable of NTSC Closed Captioninsertion on lines 21 and 284 independently.Closed captioning is enabled for either or both lines21 & 284 via the CC_EN [1:0] register bits and datato be inserted is also written into the four ClosedCaption Data registers. The CS4952/3 when en-abled automatically generates the seven cycles ofclock run-in (32 x line rate), start bit insertion(001)and finally insertion of the two data bytes perline. Data low at the video outputs corresponds to 0IRE and data high corresponds to 50 IRE.
There are two independent 8-bit registers per line(CC_21_1 & CC_21_2 for line 21 and CC_284_1
& CC_284_2 for line 284). Interrupts are also pro-vided to simplify the handshake between the driversoftware and the chip. Typically the host wouldwrite all 4 bytes to be inserted into the registers andthen enable closed caption insertion and interrupts.As the closed caption interrupts occur the host soft-ware would respond by writing the next two bytesto be inserted to the correct control registers andthen clear the interrupt and wait for the next field.
Color Bar Generator
The CS4952/3 is equipped with a color bar genera-tor that is enabled through the CBAR bit of theCONTROL_1 register. The color bar generatorworks in Master or Slave Mode and has no effecton the video input/output timing. If the CS4952/3 isconfigured for Slave Mode color bars, proper videotiming must be present on the HSYNC andVSYNC pins for the color bars to be displayed.Given proper Slave Mode input timing or MasterMode, the color bar generator will override the vid-eo input pixel data.
The output of the color bar generator is instantiatedafter the chroma interpolation filter and before theluma delay line. The generated color bar numbersare for 100% amplitude, 100% saturation NTSCEIA color bars or 100% amplitude, 100% satura-tion PAL EBU color bars. For PAL color bars, theCS4952/3 generates NTSC color bar values, whichare very close to standard PAL values. The exactluma and chroma values are listed in Table 4.
System Fsubcarrier Value (dec) Value (hex)NTSC-M 3.5795455 MHz 1138817086 43E0F83EPAL-B, D, G, H, I, N 4.43361875 MHz 1410536854 54131596PAL-N (Argentina) 3.582056 MHz 1139615885 43ED288DPAL-M 3.579611 MHz 1138838095 43CDDFC7
Table 3. Multi-standard Format FSC Register Configurations
CS4952/53
24 DS223PP2
Table 4. Internal Color Bar Values(8-bit values, Cb/Cr are in 2’s complement format)
Interrupts
In order to better support precise video modeswitches and to establish a software/hardwarehandshake with the closed caption insertion blockthe CS4952/3 is equipped with an interrupt pinnamed INT. The INT pin is active high. There arethree interrupt sources: VSYNC, Line 21 and Line284. Each interrupt can be individually disabledwith the INT_EN register. Each interrupt is alsocleared via writing a one to the correspondingINT_CLR register bits. The three individual inter-rupts are ORed together to generate an interruptsignal which is presented on the INT output pin. Ifan interrupt has occurred, it cannot be eliminatedwith a disable, it must be cleared.
General Purpose I/O Port
The CS4952/53 has a GPIO port and register whichis available when the device is configured for I2Chost interface operation. In I2C host interfacemode, the PDAT [7:0] pins are unused by the hostinterface and they may operate independently as in-put or output pins for the GPIO_DATA_REG reg-ister (0x0A). The CS4952/53 also contains theGPIO_CTRL_REG Register (0x09) which is usedto configure the GPIO pins for input or output op-eration.
The GPIO port PDAT [7:0] pins are configured forinput operation when the corresponding
GPIO_CTRL_REG [7:0] bits are cleared. In GPIOinput mode, the CS4952/53 will latch the data onthe PDAT [7:0] pins into the corresponding bit lo-cations of GPIO_DATA_REG when it detects reg-ister address 0x0A through the I2C interface. Adetection of address 0x0A can happen in two ways.The first and most common way this will happen iswhen address 0x0A is written to the CS4952/53 viaits I2C interface. The second method for detectingaddress 0x0A is implemented by accessing registeraddress 0x09 through I2C. In I2C host interface op-eration, the CS4952/53 register address pointer willauto-increment to address 0x0A after an address0x09 access.
The GPIO port PDAT [7:0] pins are configured foroutput operation when the correspondingGPIO_CTRL_REG [7:0] bits are set. In GPIO out-put mode, the CS4952/53 will output the data inGPIO_DATA_REG [7:0] bit locations onto thecorresponding PDAT [7:0] pins when it detects aregister address 0x0A through the I2C interface.
ANALOG
Analog Timing
All CS4952/3 analog timing and sequencing is de-rived from the 27 MHz clock input. The analog out-puts are controlled internally by the video timinggenerator in conjunction with master and slave tim-ing. The video output signals perform accordinglyfor NTSC, PAL specifications and both modes againbut with progressive scan non-interlaced video out-put.
Being that the CS4952/3 is almost entirely a digitalcircuit, great care has been taken to guarantee ana-log timing and slew rate performance as specifiedin the NTSC and PAL analog specifications. Refer-ence the Analog Parameters section of this datasheet for exact performance parameters.
The CS4952/3 can operate with or without the aidof an external voltage reference. The CS4952/3 isdesigned with an internal voltage reference genera-tor that provides a VREFOUT signal. The internalvoltage reference is utilized by electrically con-necting the VREFOUT and VREFIN pins. VRE-FIN can also be connected to an external precision1.235 volt reference. In either case, VREFIN is tobe decoupled to ground with a 0.1 µF capacitor.Decoupling should be applied as close to the devicepin as possible.
ISET
All four of the CS4952/3 digital to analog converterDACs are output current normalized with a com-mon ISET device pin. The DAC output current perbit is determined by the size of the resistor connect-ed between ISET and electrical ground. Typically a10 kΩ±1% metal film resistor should be used. TheISET resistance can be changed by the user to ac-commodate varying video output attenuation viapost filters and also to suit individual preferred per-formance.
In conjunction with the ISET value, the user mayalso independently vary the chroma, luma and col-orburst amplitude levels via host addressable con-trol register bits that are used to control internaldigital amplifiers. The DAC output levels are de-fined by the following operations:
VREFIN/RISET = IREF1.235 V/10 kΩ = 123.5 µA
CVBS37/Y/C Outputs:VOUT (max) = IREF× (8/15)× 511× 37.5Ω =1.262 V
CVBS75 Output:VOUT (max) = IREF× (4/15)× 511× 75Ω =1.262 V
DACs
The CS4952/3 is equipped with 4 independent vid-eo grade current output digital to analog converters.They are 9-bit DACs operating at a 27 MHz twotimes oversampling rate. All four DACs are dis-abled and put in a low power mode upon RESET.All four DACs can be individually powered downand disabled. The output current per bit of all fourDACs is determined by the size of resistor connect-ed between the ISET pin and electrical ground.
Luminance DAC
The Y pin is driven from a 9-bit 27 MHz currentoutput DAC that internally receives the Y or lumi-nance portion of the video signal (black and whiteintensity and syncronization information only). Yis designed to drive proper video levels into a37.5Ω load. Reference the detailed electrical sec-tion of this data sheet for the exact Y digital to an-alog AC and DC performance data. A Y_ENenable control bit in the DAC register (0x08) isprovided to enable or disable the luminance DAC.For a complete disable and lower power operationthe Luminance DAC can be totally shut down viathe Y_PD control bit in the DAC register (0x08). Inthis mode turn-on through the control register willnot be instantaneous.
Chrominance DAC
The C pin is driven from a 9-bit 27 MHz currentoutput DAC that internally receives the C orchrominance portion of the video signal (coloronly). C is designed to drive proper video levelsinto a 37.5Ω load. Reference the detailed electricalsection of this data sheet for the exact C digital toanalog AC and DC performance data. A C_EN en-able control register bit in the DAC register (0x08)is provided to enable or disable the ChrominanceDAC. For a complete disable and lower power op-eration the Chrominance DAC can be totally shutdown via the C_PD control register bit in the DAC
CS4952/53
26 DS223PP2
register (0x08). In this mode turn-on through thecontrol register will not be instantaneous.
CVBS75 DAC
The CVBS75 pin is driven from a 9-bit 27 MHzcurrent output DAC that internally receives a com-bined luma and chroma signal to provide compos-ite video output. CVBS75 is designed to driveproper composite video levels into a 75 Ω load.Reference the detailed electrical section of this datasheet for the exact CVBS75 digital to analog ACand DC performance data. A C_75_EN enable con-trol register bit in the DAC register (0x08) is provid-ed to enable or disable the ouput pin. Whendisabled, no current flows from the output. For acomplete disable and lower power operation theCVBS75 DAC can be totally shut down via theC_75_PD control register bit in the DAC register(0x08). In this mode turn-on through the controlregister will not be instantaneous.
CVBS37 DAC
The CVBS37 pin is driven from a 9-bit 27 MHzcurrent output DAC that internally receives a com-bined luma and chroma signal to provide compos-ite video output. CVBS37 is designed to driveproper composite video levels into a 37.5 Ω load.Reference the detailed electrical section of this datasheet for the exact CVBS37 digital to analog ACand DC performance data. The C_37_EN DAC en-able control register bit is in the DAC register(0x08) provided to enable or disable the ouput pin.When disabled, no current flow from the output.For a complete disable and lower power operationthe CVBS37 DAC can be totally shut down via theC_37_PD control register bit in the DAC register(0x08). In this mode turn-on through the controlregister will not be instantaneous.
CS4952/53
DS223PP2 27
PROGRAMMING
Host Control Interface
The CS4952/3 host control interface can be config-ured for I2C or 8-bit parallel operation. TheCS4952/3 will default to I2C operation when theRD and WR pins are both tied low at power up. TheRD and WR pins are active for 8-bit parallel oper-ation only.
I2C Interface
The CS4952/3 provides an I2C interface for access-ing the internal control and status registers. Externalpins are a bidirectional data pin (SDA) and a serialinput clock (SCL). The protocol follows the I2Cspecifications. A complete data transfer is shown inFigure 14. Note that this I2C interface will work inSlave Mode only - it is not a bus master.
SDA and SCL are connected via an externalpull-up resistor to a positive supply voltage. Whenthe bus is free, both lines are high. The output stag-es of devices connected to the bus must have anopen-drain or open-collector in order to performthe wired-AND function. Data on the I2C bus canbe transferred at a rate of up to 400 kbits/sec in fastmode. The number of interfaces to the bus is solelydependent on the limiting bus capacitance of400 pF. When 8-bit parallel interface operation isbeing used, SDA and SCL can be tied directly toground.
The I2C bus address for the CS4952/3 is program-mable via register I2C_ADR (0x0F).
8-bit Parallel Interface
The CS4952/3 is equipped with a full 8-bit parallelmicroprocessor write and read control port. Alongwith the PDAT [7:0] pins the control port interfaceis comprised of host read RD and host write WRactive low strobes and host address enable ADDRwhich, when low, enables unique address registeraccesses. The control port is used to access internalregisters which configure the CS4952/3 for variousmodes of operation. The internal registers areuniquely addressed via an address register. The ad-dress register is accessed during a host write cyclewith the WR and ADDR pins set low. Host writecycles with ADDR set high will write the 8-bits onthe PDAT [7:0] pins into the register currently se-lected by the address register. Likewise read cyclesoccur with RD set low and ADDR set high will re-turn the register contents selected by the addressregister. Reference the detailed electrical timingparameter section of this data sheet for exact hostparallel interface timing characteristics and specifi-cations. When I2C interface operation is beingused, RD and WR must be tied to ground.PDAT [7:0] are available to be used for GPIO op-eration in I2C host interface mode.
SDA
SCL
I C Protocol2
Start Address R/W ACK Data Stop
A P1-7 8 9
ACK
1-7 8 9
Data ACK
1-7 8 9
Note: I C transfers data always with MSB first, LSB last2
Figure 14. I2C Data Transfer
CS4952/53
28 DS223PP2
Register Description
A set of internal registers are available for control-ling the operation of the CS4952/3. The registersextend from internal address 0x00 through 0x3D.Table 5 shows a complete list of these registers and
their internal addresses. Note that this table and thesubsequent register description section describe thefull register map for CS4952 only. A completeCS4953 register set description is only available toMacrovision ACP-PPV Licensed Buyers.
Address Register Name Type Default Value0x00 CONTROL_0 r/w 01h0x01 CONTROL_1 r/w 04h0x02 CONTROL_2 r/w 00h0x03 RESERVED0x04 DAC r/w F0h
0x05 - 0x06 RESERVED0x07 STATUS read only 00h0x08 BKG_COLOR r/w 03h0x09 GPIO_CTRL_REG r/w0x0A GPIO_DATA_REG r/w 00h
4 MSTR 1: Master Mode, 0: Slave Mode3 CCIR656 video input is in CCIR656 format (0: off, 1: on)2 PROG Progressive scanning enable (enable with 1)1 IN_MODE Input select (0: solid background, 1: use V [7:0] data)0 CBCR_UV enable YCbCr to YUV conversion (1: enable, 0: disable)
Bit Number 7 6 5 4 3 2 1 0Bit Name CBLANK Y_DELAY C_BW C_LPF_EN FLD PED CBAR CBCRSELDefault 0 0 0 0 0 1 0 0
Bit Mnemonic Function7 CBLANK Composite Blank / HSYNC output select (1: CB, 0: HSYNC)6 Y_DELAY luma to chroma delay (0: no delay, 1: luma is delayed by one 13.5 MHz cycle)5 C_BW chroma lpf bandwidth (0: 650 KHz, 1: 1.3 MHz)4 C_LPF_EN chroma lpf on/off (0: off, 1: on)3 FLD Polarity of Field (0: odd field - 0, 1: odd field - 1)2 PED Pedestal offset (0: 0 IRE, 1: 7.5 IRE)1 CBAR internal color bar generator (0: off, 1: on)0 CBCRSEL CbCr select (0: chroma undelayed, 1: chroma delayed by one clock)
CS4952/53
30 DS223PP2
Control Register 2
Address 0x02 CONTROL_2 Read/Write Default Value = 00h
DAC Power Down Register
Address 0x04 DAC Read/Write Default Value = F0h
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED SYNC_DLY XTAL SC_ENDefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:4 - reserved
3 Y_BWSelects between 4.2 Mhz and 6 Mhz on-chip luminance low pass filters; default value is zero which selects the 4.2 Mhz low pass filter option
2 SYNC_DLY
Delays expected timing of first active pixel input data relative to falling edge of HSYNC from 245 27 MHz clock cycles to 246 for NTSC and from 265 to 266 for PAL. Default State is SYNC_DLY=0 for no delay
Bit Number 7 6 5 4 3 2 1 0Bit Name C_75_PD C_37_PD Y_PD C_PD C_75_EN C_37_EN Y_EN C_ENDefault 1 1 1 1 0 0 0 0
Bit Mnemonic Function7 C_75_PD power down composite DAC with 75 Ω load (0: power up, 1: power down)6 C_37_PD power down composite DAC with 37.5 Ω load (0: power up, 1: power down)5 Y_PD power down luma s-video DAC (0: power up, 1: power down)4 C_PD power down chroma s-video DAC (0: power up, 1: power down)3 C_75_EN enable composite video DAC output for 75 Ω (0: tri-state, 1: enable)2 C_37_EN enable composite video DAC output for 37.5 Ω (0: tri-state, 1: enable)1 Y_EN enable s-video DAC for luma output (0: tri-state, 1: enable)0 C_EN enable s-video DAC for chroma output (0: tri-state, 1: enable)
CS4952/53
DS223PP2 31
Status Register
Address 0x07 STATUS Read Only Default Value = 00h
Background Color Register
Address 0x08 BKG_COLOR Read/Write Default Value = 03h
GPIO Control Register
Address 0x09 GPIO_CTRL_REG Read/Write Default Value = 00h
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED CC_INT_21 CC_INT_284 VS_INT FIELDDefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:6 - reserved5 CC_INT_21 Interrupt flag for line 21 (closed caption) complete4 CC_INT_284 Interrupt flag for line 284 (closed caption) complete3 VS_INT Interrupt flag for video field change
2:0 FIELD Field Status bits000: field 8001: field 1010: field 2011: field 3100: field 4101: field 5110: field 6111: field 7
Bit Number 7 6 5 4 3 2 1 0Bit Name BG_COLRDefault 0 0 0 0 0 0 1 1
Bit Mnemonic Function7:0 BG_COLR Background color (7:5 = R, 4:2 = G, 1:0 = B)
Bit Number 7 6 5 4 3 2 1 0Bit Name GPIO_IODefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:0 GPIO_IO input(0)/output(1) control of GPIO registers (bit X: PDAT(X) I/O configuration)
CS4952/53
32 DS223PP2
GPIO Data Register
Address 0x0A GPIO_DATA_REG Read/Write Default Value = 00h
Chroma Filter Register
Address 0x0D C_AMP Read/Write Default Value = 80h
Luma Filter Register
Address 0x0E Y_AMP Read/Write Default Value = 80h
I2C Address Register
Address 0x0F I2C_ADR Read/Write Default Value = N/A
Bit Number 7 6 5 4 3 2 1 0Bit Name GPIO_DATADefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function
7:0 GPIO_DATA GPIO data register; data is output on PDAT [7:0] bus if appropriate bit in GPIO_CTRL_REG (0x09) is set to “1”; data on PDAT [7:0] is latched into
GPIO_DATA_REG [7:0] when register address 0x0A is accessed via I2C.
This register is only accessible in I2C mode.
Bit Number 7 6 5 4 3 2 1 0Bit Name C_COEFDefault 1 0 0 0 0 0 0 0
Bit Mnemonic Function7:0 C_COEF Chroma amplitude coefficient
Bit Number 7 6 5 4 3 2 1 0Bit Name Y_COEFDefault 1 0 0 0 0 0 0 0
Bit Mnemonic Function7:0 Y_COEF Luma amplitude coefficient
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED ADDRDefault - - - - - - - -
Bit Mnemonic Function7 - reserved
6:0 ADDR I2C device address (programmable)
CS4952/53
DS223PP2 33
Subcarrier Amplitude Register
Address 0x10 SC_AMP Read/Write Default Value = 1Ch
Address 0x3B INT_EN Read/Write Default Value = 00h
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED EN_284 EN_21Default 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:2 - reserved1 EN_284 enable closed caption for line 2840 EN_21 enable closed caption for line 21
Register Bit Mnemonic FunctionCC_21_1 7:0 - first closed caption databyte of line 21CC_21_2 7:0 - second closed caption databyte of line 21CC_284_1 7:0 - first closed caption databyte of line 284CC_284_2 7:0 - second closed caption databyte of line 284
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED EN_21 EN_284 VS_ENDefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:3 - reserved2 EN_21 interrupt enable for closed caption line 211 EN_284 interrupt enable for closed caption line 2840 VS_EN interrupt enable for new field
CS4952/53
DS223PP2 35
Interrupt Clear Register
Address 0x3C INT_CLR Read/Write Default Value = 00h
Device ID Register
Address 0x3D ID_REG Read Only Default Value = N/A
Bit Number 7 6 5 4 3 2 1 0Bit Name RESERVED CLR_21 CLR_284 VS_CLRDefault 0 0 0 0 0 0 0 0
Bit Mnemonic Function7:3 - reserved2 CLR_21 clear interrupt for closed caption line 21 (INT_21)1 CLR_284 clear interrupt for closed caption line 284 (INT_284)0 VS_CLR clear interrupt for new video field (INT_V)
Bit Number 7 6 5 4 3 2 1 0Bit Name DEV_ID RESERVEDDefault 0 0 0 0 - - - -
Bit Mnemonic Function7:4 DEV_ID 0000 device ID for CS4952
0001 device ID for CS49533:0 - These bits are reserved and the value they return on a read is not defined
CS4952/53
36 DS223PP2
BOARD DESIGN & LAYOUT CONSIDERATIONS
The printed circuit layout should be optimized forlowest noise on the CS4952/3 power and groundlines. Digital and analog sections should be physi-cally separated and the CS4952/3 placed as close tothe output connectors as possible. All analog sup-ply traces should be as short as possible to mini-mize inductive ringing.
A well designed power distribution network is es-sential in eliminating digital switching noise. Theground planes must provide a low-impedance re-turn path for the digital circuits. A PC board with aminimum of four layers is recommended. Theground layer should be used as a shield to isolatenoise from the analog traces. The top layer (1)should be reserved for analog traces but digitaltraces may share this layer if the digital signalshave low edge rates and switch little current or ifthey are separated from the analog traces by a sig-nificant distance (dependent on their frequencycontent and current). The second layer should thenbe the ground plane followed by the analog powerplane on layer three and the digital signal layer onlayer four
Power and Ground Planes
The power and ground planes need isolation gapsof at 0.05” to minimize digital switching noise ef-fects on the analog signals and components. A splitanalog/digital ground plane should be connected atone point as close as possible to the CS4952/3. Asplit analog/digital power plane should be connect-ed at one point as close as possible to the power en-try point and decoupled properly.
Power Supply Decoupling
Start by reducing power supply ripple and wiringharness inductance by placing a large (33 - 100uF)capacitor as close to the power entry point as pos-sible. Use separate power planes or traces for thedigital and analog sections even if they use the
same supply. If necessary, further isolate the digitaland analog power supplies by using ferrite beads oneach supply branch followed by a low ESR capac-itor.
Place all decoupling caps as close as possible to thedevice as possible. Surface mount capacitors gen-erally have lower inductance than radial lead or ax-ial lead components. Surface mount caps should beplaced on the component side of the PCB to mini-mize inductance caused by board vias. Any vias,especially to ground, should be as large as practicalto reduce their inductive effects.
VREF Decoupling
The VREFOUT pin provides a 1.235 V referencefor the internal DACs. VREFOUT is only intendedto drive VREFIN. Do not connect to an externalload. A small bypass cap, however, may be placedon VREFOUT to reduce noise. Usually a 0.1uFMLC surface mount capacitor is sufficient.
Digital Interconnect
The digital inputs and outputs of the CS4952/3should be isolated from the analog outputs as muchas possible. Use separate signal layers wheneverpossible and do not route digital signals over theanalog power and ground planes.
Noise from the digital section is directly related tothe digital edge rates used. Ringing, overshoot, un-dershoot, and ground bounce are all related to edgerate. Use lower speed logic such as HCMOS for thehost port interface to reduce switching noise. Forthe video input ports, higher speed logic is re-quired, but use the slowest practical edge rate to re-duce noise.
To reduce digital noise, it is important to match thesource impedance, line impedance, and load im-pedance as much as possible. Generally, if the linelength is greater than one fourth the signal edgerate, line termination is necessary. Ringing mayalso be reduced by damping the line with a seriesresistor (22 - 150Ω). Under extreme cases, it may
CS4952/53
DS223PP2 37
be advisable to use microstrip techniques to furtherreduce radiated switching noise if very fast edgerates (<2ns) are used. If microstrip techniques areused, split the analog and digital ground planes anduse proper RF decoupling techniques.
Analog Interconnect
The CS4952/3 should be located as close as possibleto the output connectors to minimize noise pickupand reflections due to impedance mismatch. All un-used analog outputs should be placed in shutdown.This reduces the total power that the CS4952/3 re-quires, and eliminates the impedance mismatch pre-sented by an unused connector. The analog outputsshould not overlay the analog power plane to maxi-mize high frequency power supply rejection.
Analog Output Protection
To minimize the possibility of damage to the ana-log out put sections, make sure that all video con-nectors are well grounded. The connector groundshould have a good DC ground path to the analogand digital power supply grounds. If no DC (andlow frequency) path is present, improperly ground-ed equipment may impose damaging reverse cur-rents on the video out lines. Therefore, it is also agood idea to use output filters that are AC coupledto avoid any problems.
ESD Protection
External DAC Output Filter
If an output filter is required for the compositeand/or S-video outputs of the CS4952/53, the fol-lowing low pass filter in Figure 15 can be used.
2.2µH
330pF 220pF
OUTIN
C1 C2 CCABLE
C2 C1 CCABLEshould be chosen so that = C2 +
Figure 15. Low Pass Filter
CS4952/53
38 DS223PP2
CS4952/3-CL44-pinPLCC
Top View
18 20 22 24 26 28
1246 404244
12
8
10
14
16
7
9
11
13
15
17 29
31
33
35
37
39
34
30
32
36
38
VAA
GND
VAA
CVBS37
CVBS75
TEST
V0
V1
V2
V3
V4
V5
V6
V7
FIELD
HSYNC/CB
VSYNC
XTAL
ADDR
VAA
GND
GND
C
Y
VREFOUT
VREFIN
ISET
VAA
GND
RESET
SCL
SDA
INT
CLKIN
WR
RD
PDAT0
PDAT1
PDAT2
PDAT3
PDAT4
PDAT5
PDAT6
PDAT7
DEVICE PINOUT - 44 PLCC
CS4952/53
DS223PP2 39
PLCC Pin Description
Pin Name Pin Number Type DescriptionV [7:0] 14, 13, 12, 11, 10, 9, 8, 7 IN Digital video data inputsCLK 33 IN 27 MHz input clockADDR 19 IN Address enable line / subcarrier crystal inputXTAL 18 OUT subcarrier crystal outputHSYNC/CB 16 I/O Active low horizontal sync, or composite blank signalVSYNC 17 I/O Active low vertical sync.FIELD 15 OUT Video field ID. Selectable polarityRD 31 IN Host parallel port read strobe, active lowWR 32 IN Host parallel port write strobe, active lowPDAT [7:0] 23,24,25,26,27,28,29,30 I/O Host parallel port/ general purpose I/O
SDA 35 I/O I2C data
SCL 36 IN I2C clock inputCVBS75 5 CURRENT Composite video output for driving 75 Ω loadsCVBS37 4 CURRENT Composite video output for driving 37.5 Ω loadsY 43 CURRENT Luminance analog output for driving 37.5 Ω loadsC 44 CURRENT Chrominance analog output for driving 37.5 Ω loadsVREFOUT 42 OUT Internal voltage reference outputVREFIN 41 IN External voltage reference inputISET 40 OUT DAC current setINT 34 OUT Interrupt output, active highRESET 37 IN Active low master resetTEST 6 IN TEST pin. Ground for normal operationVAA 1, 3, 20, 39 PS +5 V supplyGND 2, 22, 21, 38 PS Ground
Pin Name Pin Number Type DescriptionV [7:0] 8, 7, 6, 5, 4, 3, 2, 1 IN Digital video data inputsCLKIN 27 IN 27 MHz input clockADDR 13 IN Address enable line / subcarrier crystal inputXTAL 12 OUT subcarrier crystal outputHSYNC/CB 10 I/O Active low horizontal sync, or composite blank signalVSYNC 11 I/O Active low vertical sync.FIELD 9 OUT Video field ID. Selectable polarityRD 25 IN Host parallel port read strobe, active lowWR 26 IN Host parallel port write strobe, active lowPDAT [7:0] 17,18,19,20,21,22,23,24 I/O Host parallel port/ general purpose I/O
SDA 29 I/O I2C data
SCL 30 IN I2C clock inputCVBS75 43 CURRENT Composite video output for driving 75 Ω loadsCVBS37 42 CURRENT Composite video output for driving 37.5 Ω loadsY 37 CURRENT Luminance analog output for driving 37.5 Ω loadsC 38 CURRENT Chrominance analog output for driving 37.5 Ω loadsVREFOUT 36 OUT Internal voltage reference outputVREFIN 35 IN External voltage reference inputISET 34 OUT DAC current setINT 28 OUT Interrupt output, active highRESET 31 IN Active low master resetTEST 44 IN TEST pin. Ground for normal operationVAA 14, 33, 39, 41 PS +5 V supplyGND 15, 16, 32, 40 PS Ground
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