VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203
DEPARTMENT OF
ELECTRONICS AND INSTRUMENTATION ENGINEERING
QUESTION BANK
V SEMESTER
CS6303-COMPUTER ARCHITECTURE
Regulation – 2013
Academic Year 2017– 2018
Prepared by
Ms.S.Vanila, Assistant Professor (Sr. G) / EIE
Ms. R. Umamaheswari, Assistant Professor (O. G) /EIE
VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.
DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING
QUESTION BANK SUBJECT : CS6303 COMPUTER ARCHITECTURE
SEM / YEAR : V/ III
UNIT I - OVERVIEW & INSTRUCTIONS
Eight ideas – Components of a computer system – Technology – Performance – Power wall
– Uniprocessors to multiprocessors; Instructions – operations and operands – representing
instructions– Logical operations – control operations – Addressing and addressing modes.
PART – A
S.No Questions BT
Level
Competence
1 List the major components of a computer system. BTL1 Remember
2 What is an instruction register? BTL1 Remember
3 What is meant by stored program concept? BTL1 Remember
4 Define the term computer architecture. BTL1 Remember
5 List the eight great ideas invented by computer architects. BTL1 Remember
6 What is superscalar execution? BTL1 Remember
7 Give the formula for CPU execution time for a program. BTL2 Understand
8 Compare RISC and CISC architecture. BTL2 Understand
9 Classify the methods used to improve system
performance. BTL2 Understand
10 State the need for addressing mode. Give an example. BTL2 Understand
11 Illustrate about the word length for processor. BTL3 Apply
12 Specify the formula for SPEC rating. And what is SPEC? BTL3 Apply
13 Mention the uses of elapsed time and power wall. BTL3 Apply
14 Distinguish between super computer and mainframe
computer. BTL4 Analyze
15 Compare Uniprocessors and Multicore processor. BTL4 Analyze
16 Differentiate clock, clock cycles and processor time. BTL4 Analyze
17 Evaluate the CPU execution time for two input addition
program. BTL5 Evaluate
18 Compare instruction register and program counter in
computer architecture. BTL5 Evaluate
19 Generalize about relative addressing mode with an
example. BTL6 Create
20 Write the merits and demerits of single address
instructions. BTL6 Create
PART B
1 (i) Describe in detail the factors influencing performance.(7)
(ii) What is the need of the addressing mode and explain the
basic addressing modes with an example for each. (6)
BTL 1 Remember
2 (i) Describe the instruction sequencing in detail. (7)
(ii) List the differences between RISC and CISC
architectures. (6)
BTL 1 Remember
3 (i) Examine the important measures of the performance of a
computer. (7)
(ii) Also, Derive basic performance equation of a computer.
(6)
BTL 1 Remember
4 Explain in detail the various components of computer
system with neat diagram. (13) BTL 1 Remember
5 Describe about the eight ideas of computer architecture.
(13) BTL 2 Understand
6 Discuss about the various techniques to represent
instructions in a computer system. (13) BTL 2 Understand
7 (i) Illustrate in detail about Uniprocessors. (6)
(ii)Discuss about the organization of Multiprocessor. (7) BTL 2 Understand
8 Explain classes of computing applications and their
characteristics. (13) BTL 3 Apply
9 Explain the different types of addressing modes with
suitable examples. (13) BTL 3 Apply
10 Explain the following addressing modes with example:
(i) Direct addressing mode (3)
(ii) Immediate addressing mode (3)
(iii) Relative addressing mode (3)
(iv) Indexed addressing modes (4)
BTL 4 Analyze
11 (i) Explain in detail the different Instruction types. (7)
(ii)Compare the merits and demerits of all instruction types.
(6)
BTL 4 Analyze
12 Summarize about the history of development of computers.
(13) BTL 5 Evaluate
13 (i) Outline the various generations of computer system. (7)
(ii)Explain about Power wall in a processor. (6) BTL 6 Create
14 (i) Assume a two address format specified as source,
destination. Examine the following sequence of instructions
and explain the addressing modes used and operation done
in every instruction
Move (R5)+, R0
Add (R5)+,R0
Move R0,(R5)
Move 16(R5),R3
Add #40,R5 (7)
(ii) Consider the computer with three instruction classes
and CPI measurements as given below and Instruction
counts for each instruction class for the same program from
two different compilers are given. Assume that the
computer’s clock rate is 4 GHz. According to the execution
time which code sequence will execute faster?
(6)
Code from CPI for this instruction class
A B C
BTL 6 Create
CPI 1 2 3
Code from Instruction count for each class
Compiler 1
2 1 2
Compiler 2
4 1
1
PART C
1 (i) Develop a program that can evaluate the expression
A * B + C * D
in a single accumulator processor. Assume that the processor
has LOAD, STORE, MULTIPLY and ADD instruction and
that all value fit in the accumulator. (8)
(ii) Describe the different classes of instruction format with
example. (7)
BTL 5
Evaluate
2 Evaluate the value of the effective address of the memory
operand in each of the following instruction. Consider
Registers R1 and R2 of a computer contain the decimal
values 1200 and 4600.
Load 20(R1), R5
Move #3000, R5
Store R5, 30(R1, R2)
Add - (R2), R5
Subtract (R1) +, R5 (15)
BTL 5 Evaluate
3 Our favourite program runs in 10 seconds on computer A,
which has a 2GHz clock. We are trying to help a computer
designer build a computer B, which will run this program in
6 seconds. The designer has determined that a substantial
increase in clock rate is possible, but this increase will affect
the rest of the CPU design, causing computer B to require
1.2 times as many clock cycles as computer A for this
program. What clock rate should we tell the designer to
target? (15)
BTL 6 Create
4 Suppose we have two implementations of the same
instruction set architecture .computer A has a clock cycle
time of 250ps and a CPI of 1.2 for some program, and
computer B has a clock time of 500 ps and a CPI of 1.2 for
the same program. Which computer is faster for this
program and by how much? (15)
BTL 6 Create
UNIT II - ARITHMETIC OPERATIONS
ALU - Addition and subtraction – Multiplication – Division – Floating Point operations –
Subword Parallelism.
PART – A
S.No Questions BT
Level
Competence
1 List the rule for subtraction in floating point operation. BTL 1 Remember
2 Define Von Neumann Rounding. BTL 1 Remember
3 What is arithmetic overflow? BTL 1 Remember
4 What is guard bit and what are the ways to truncate the
guard bits? BTL 1 Remember
5 Define Truncation and chopping. BTL 1 Remember
6 What is ripple carry adder? BTL 1 Remember
7 Define Little Endian arrangement. BTL 2 Understand
8 State the advantages of booth algorithm. BTL 2 Understand
9 Give the rules for multiplication and division of floating
point numbers. BTL 2 Understand
10 Show that why the floating point number is more difficult
to represent and process than integer. BTL 2 Understand
11 Draw the format of floating point number. BTL 3 Apply
12 Mention the rules to perform addition on floating point
numbers. BTL 3 Apply
13 How overflow occur in subtraction? BTL 3 Apply
14 Differentiate overflow and underflow case in single
precision. BTL 4 Analyze
15 When can you say that a floating point number is
normalized? BTL 4 Analyze
16 Analyze about Sub word Parallelism. BTL 4 Analyze
17 Obtain the representation of double precision floating
point number. BTL 5 Evaluate
18 Subtract (11010)2 - (10000)2 using 1's complement and 2's
complement method. BTL 5 Evaluate
19 Formulate the steps involved in restoring division. BTL 6 Create
20 Draw the block diagram for a 64 bit carry look ahead
adder built from 16 bit adder. BTL 6 Create
PART B
1 (i) Describe the operation of carry –look ahead adder in
detail. (7)
(ii) Describe the Booth’s multiplication algorithm with an
example. (6)
BTL 1 Remember
2 Explain Booth's Algorithm for the multiplication of signed
two's complement numbers. (13) BTL 1 Remember
3 (i) List the steps used for integer division methods. (5)
(ii) Illustrate them with dividend (10)10 and divisor (3)10 (8) BTL 1 Remember
4 Describe in detail about division algorithm in detail with
diagram and examples. (13) BTL 1 Remember
5 (i) Design an arithmetic element to perform the basic
floating point operations. (7)
(ii) What is meant by sub-word parallelism? Explain. (6)
BTL 2 Understand
6 (i)Demonstrate multiplication of two binary numbers with
an example. Design an arithmetic element to perform this
multiplication. (7)
(ii) Solve for binary multiplication between two numbers :
(-10)10 and (+5)10 (6)
BTL 2 Understand
7 (i)Explain how floating point operation is carried out in a
computer system. (7)
(ii)Give an example for a binary floating point addition and
explain in brief. (6)
BTL 2 Understand
8 (i) State the restoring division technique. (5)
(ii) Demonstrate the division of 10112 by 1102 using
restoring method. (8)
BTL 3 Apply
9 Draw and explain the block diagram of n-bit two’s
complement adder – subtractor with an example. (13) BTL 3 Apply
10 (i) Evaluate the value of division for (12)10 by (3)10 using
non-restoring division algorithm. (7)
(ii) Explain about the non-restoring division with step by
step intermediate results. (6)
BTL 4 Analyze
11 Explain with a diagram the design of a fast multiplier using
carry save adder circuit. (13) BTL 4 Analyze
12 Draw the block diagram for a floating point adder and
subtractor unit and discuss its operation. (13) BTL 5 Evaluate
13 (i)Multiply (-12)10 and (+15)10 using Booth multiplier
algorithm. (7)
(ii)Show all the intermediate steps involved in Booth
Multiplier algorithm with a flowchart and hardware
architecture. (6)
BTL 6 Create
14 (i)Design a 4 bit adder/subtractor circuit using full adders
and explain its function. (7)
(ii) Design a 4 bit fast adder and explain its function in
detail. (6)
BTL 6 Create
PART C
1 What is the advantage of Ripple carry addition and how it is
overcome in carry look ahead adder and draw the logic
circuit of CLA. (15)
BTL 6 Create
2 (i) Obtain the value for 5-bit, signed, 2's complement, and
binary numbers and add them. Check whether or not
overflow occurs in each case. (8)
(a) 5 and 10
(b) 7 and 13
(c) -14 and 11
(d) -3 and -8
(e) -10 and -13
BTL 5 Evaluate
(ii) Repeat Part (i) for the subtract operation, where the
second number of each pair is to be subtracted from the first
number. Check whether or not overflow occurs in each case.
(7)
3 (i) Design a multiplier for the following pair of signed 2's
Complement numbers using the booth algorithm. Assume
that A is the multiplicand and B is the multiplier.
For A= (01011)2 and B= (110110) 2 (7)
(ii) If the product of two, n-bit, signed numbers in the 2's
Complement representation can be represented in n bits, as
discussed in the manual multiplication algorithm treating
the sign bits the same as the other bits. Formulate the steps
of multiplication on the following pair of 4-bit signed
numbers:
Multiplicand = 11102 and Multiplier = 11012.
Will it work correctly? If yes how? (8)
BTL 6 Create
4 (i)Represent the numbers +1.7,-0.012,+19 and 1/8 in 32 bit
IEEE format. (5)
(ii) What are the largest and smallest numbers
representable in 32 bit IEEE format? (5)
(iii) Perform Addition, Subtraction, Multiplication and
Division operations on the operands.
A= (0 10001 011011)2
B= (1 01111 101010)2 (5)
BTL 5 Evaluate
UNIT III- PROCESSOR AND CONTROL UNIT
Basic MIPS implementation – Building data path – Control Implementation scheme –
Pipelining –Pipelined data path and control – Handling Data hazards & Control hazards –
Exceptions.
PART – A
S.No Questions BT
Level
Competence
1 What is pipelining and what are the advantages of
pipelining? BTL 1 Remember
2 What is the use of exception handling? BTL 1 Remember
3 What is meant by pipeline bubble? BTL 1 Remember
4 Name the control signals required to perform arithmetic
operations BTL 1 Remember
5 What is data path? BTL 1 Remember
6 What do you mean by delayed branching? BTL 1 Remember
7 Differentiate between exception and interrupt. BTL 2 Understand
8 Define hazard. Give an example for data hazard. BTL 2 Understand
9 Give the steps to calculate the processor cycle in
pipelining. BTL 2 Understand
10 Express about branch penalty. BTL 2 Understand
11 Write in detail about the major characteristics of a
pipeline. BTL 3 Apply
12 Mention the causes for side effect in hazards. BTL 3 Apply
13 Classify the types of pipeline hazards BTL 3 Apply
14 How can memory access be made faster in a pipelined
operation? Which hazards can be reduced by faster
memory access?
BTL 4 Analyze
15 Point out the occurrences of structural hazards. BTL 4 Analyze
16 Differentiate between the static and dynamic techniques
in pipelining. BTL 4 Analyze
17 Determine the number of clock cycles that it takes to
process 200 tasks in a 6 segment pipelines. BTL 5 Evaluate
18 Obtain the key aspects in gaining the performance in
pipelined systems BTL 5 Evaluate
19 Identify register delay in pipelining for a simple
instruction execution. BTL 6 Create
20 What would be the effect, if we increase the number of
pipelining stages? BTL 6 Create
PART B
1 (i) Explain the hazards caused by unconditional branching
statements. (7)
(ii) Describe operand forwarding in a pipeline processor
with a diagram. (6)
BTL 1 Remember
2 (i) Describe about control hazard. (6) BTL 1 Remember
(ii) Explain the ways and means of handling control
hazards. (7)
3 (i) Describe about data hazard. (7)
(ii) Explain the ways and means of handling data hazard. (6) BTL 1 Remember
4 Explain how the instruction pipeline works. What are the
various situations where an instruction pipeline can stall?
(13)
BTL 1 Remember
5 Discuss the modified data path to accommodate pipelined
execution with a diagram. (13) BTL 2 Understand
6 (i) Discuss the basic concepts of pipelining. (8)
(ii)Describe the data path and control considerations for
pipelining. (5)
BTL 2 Understand
7 Why is branch prediction algorithm needed? Differentiate
between static and dynamic techniques. (13) BTL 2 Understand
8 (i) Draw and explain the three bus structure in detail. (5)
(ii) Explain 4-stage instruction pipeline. (4)
(iii) Explain the issues affecting pipeline performance. (4)
BTL 3 Apply
9 Illustrate the control signal generation using hardwired and
micro programmed control with necessary block diagrams.
(13)
BTL 3 Apply
10 (i)Explain about the role of cache in pipelining. (7)
(ii)Explain about the pipeline performance characteristics.
(6)
BTL 4 Analyze
11 (i) What are instruction hazards? (5)
(ii) Explain in detail how to handle the instruction hazards
in pipelining with relevant examples. (8)
BTL 4 Analyze
12 (i) Conclude the relationships between pipeline execution
and addressing mode. (8)
(ii) What do you mean by out of order execution? (5)
BTL 5 Evaluate
13 (i) Explain the function of a six segment pipeline showing
the time it takes to process eight tasks. (7)
(ii) Give an account on branch penalty, branch folding,
side effects, speculative execution. (6)
BTL 6 Create
14 Develop a data path diagram of a computer for any two
instructions. (13) BTL 6 Create
PART C
1 Explain about the control steps for the branch –on-negative
instruction for the processor. (15) BTL 5 Evaluate
2 A pipelined processor used delayed branch technique.
Recommend any one of the following possibility for the
design of the processor. In the first possibility, the
processor has a 4-stage pipeline and one delay slot. In the
second possibility, it has a 6-stage pipeline and two delay
slots. Compare the performance of these two alternatives,
taking only the branch penalty into account. Assume that
20% of the instructions are branch instructions and that an
optimizing compiler has an 80% success rate in filing in the
single delay slot. For the second alternative, the complier is
able to find the second slot 25% of the time. (15)
BTL 5 Evaluate
3 Design and explain a parallel priority interrupt hardware for
a system with eight interrupt sources. (15) BTL 6 Create
4 Design a data path for the operational portion of the
memory reference and arithmetic logical instructions that
uses a single register file and a single ALU to handle both
types of instructions adding any necessary MUX. (15)
BTL 6 Create
UNIT-IV Parallelism
Instruction-level-parallelism – Parallel processing challenges – Flynn's classification –
Hardware Multithreading – Multicore processors
PART – A
S.No Questions BT
Level
Competence
1 What is ILP? BTL 1 Remember
2 What is meant by Speculative execution? BTL 1 Remember
3 What is multithreading? BTL 1 Remember
4 Define Register renaming. BTL 1 Remember
5 Define Out of order execution. BTL 1 Remember
6 What is In order commit? BTL 1 Remember
7 Give the Flynn’s classification. BTL 2 Understand
8 Distinguish between Static multiple issue and Dynamic
multiple issue. BTL 2 Understand
9 Compare Superscalar and Dynamic pipeline schedule. BTL 2 Understand
10 Compare and contrast UMA and NUMA multiprocessors. BTL 2 Understand
11 Mention the categories of multiprocessors. BTL 3 Apply
12 Write about the Loop unrolling in Microprocessor systems. BTL 3 Apply
13 Calculate Commit unit for a multiprocessor architecture BTL 3 Apply
14 Point out reorder buffer in parallel architecture BTL 4 Analyze
15 Distinguish between implicit multithreading and explicit
multithreading. BTL 4 Analyze
16 Differentiate between strong scaling and weak scaling BTL 4 Analyze
17 Obtain the taxonomy of Parallel architecture. BTL 5 Evaluate
18 Evaluate Use latency. BTL 5 Evaluate
19 Write short notes on reservation station. BTL 6 Create
20 Prepare the notes about multi-threading. BTL 6 Create
PART B
1 (i)What is Instruction level parallelism? (5)
(ii) Describe about the various dependencies caused in ILP.
(8)
BTL 1 Remember
2 Examine briefly about the four principal approaches to
multithreading with necessary diagrams. (13) BTL 1 Remember
3 Describe about shared memory multiprocessor with a neat
diagram. (13) BTL 1 Remember
4 Explain how to overcome data hazard with dynamic
scheduling. (13) BTL 1 Remember
5 (i) Discuss the challenges in parallel processing with
necessary examples. (7)
(ii) Compare and contrast about SISD, MIMD, SIMD,
SPMD and VECTOR systems. (6)
BTL 2 Understand
6 (i)Discuss about speculative execution. (6)
(ii)Compare and contrast hardware and software speculation
mechanism. (7)
BTL 2 Understand
7 Explain in detail how branch penalties are reduced with
dynamic hardware prediction. (13) BTL 2 Understand
8 Discuss in detail about Flynn’s classification of parallel
hardware. (13) BTL 3 Apply
9 Demonstrate in detail about the motivation of Multi-core
computing. (13) BTL 3 Apply
10 (i)Explain about the symmetric shared memory architecture,
implementation techniques and protocols used. (7)
(ii)Analyze in detail about the performance issues in
symmetric shared memory architecture. (6)
BTL 4 Analyze
11 (i)Explain about the distributed shared memory architecture,
implentation techniques. (7)
(ii)Analyze in detail about the performance issues in
distributed shared memory architecture. (6)
BTL 4 Analyze
12 Explain the terms
(i) Multicore Processor. (8)
(ii) Hardware Multithreading. (5)
BTL 5 Evaluate
13 Design MIPS architecture with necessary exceptions handler.
(13) BTL 6 Create
14 Develop a basic MIPS architecture with necessary
multiplexers and control lines. (13) BTL 6 Create
PART C
1 (i)Explain about the challenges in instruction level
parallelism. (8)
(ii)State the limitations of parallel processing. (7)
BTL 5 Evaluate
2 (i) Design the hardware based speculation for a MIPS
processor. (7)
(ii) Explain how multiple issues is handled with speculation.
(8)
BTL 5 Evaluate
3 (i) Explain how thread level parallelism within a processor
can be exploited. (7)
(ii) With suitable diagrams, explain simultaneous
multithreading, its design challenges and potential
performance enhancements. (8)
BTL 6 Create
4 With suitable illustrative examples, sketch the procedure for
how compiler techniques can be exploited for achieving
ILP. (15) BTL 6 Create
UNIT-V Memory and I/O Systems
Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache
performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and
interrupts, I/O processors.
PART – A
S.No Questions BT
Level
Competence
1 What is meant by address mapping? BTL 1 Remember
2 What is cache memory? BTL 1 Remember
3 Define memory interfacing. BTL 1 Remember
4 List the components of an I/O interface. BTL 1 Remember
5 What is meant by bus arbitration? BTL 1 Remember
6 Name and give the purpose of widely used bus standard in
microprocessor system. BTL 1 Remember
7 Give the units of an interface. BTL 2 Understand
8 Summarize the sequence of events involved in handling an
interrupt request from a single device. BTL 2 Understand
9 Give the purpose of dirty/modified bit in cache memory. BTL 2 Understand
10 Differentiate between memory mapped input/output and I/O
mapped input / output. BTL 2 Understand
11 Mention about iso-synchronous data stream. BTL 3 Apply
12 Specify the different I/O transfer mechanism available. BTL 3 Apply
13 Distinguish between cache and virtual memory. BTL 3 Apply
14 Differentiate serial and parallel port. BTL 4 Analyze
15 Point out the uses of DMA. BTL 4 Analyze
16 Differentiate memory types based on size, speed and cost. BTL 4 Analyze
17 Compare Hit and Miss in cache memory. BTL 5 Evaluate
18 Assess how DMA can improve I/O speed. BTL 5 Evaluate
19 Write notes on the importance of interleaved memory. BTL 6 Create
20 Write about the devices which can be connected to the
computer using PCI bus. BTL 6 Create
PART B
1 Describe about the following DRAM technology with
diagram:
(i) Synchronous DRAM (7)
(ii) Asynchronous DRAM (6)
BTL 1 Remember
2 (i)What is an interrupt? (5)
(ii) Describe about the different types of interrupts and the
different ways of handling the interrupts. (8)
BTL 1 Remember
3 (i) Describe the features and operations of SCSI (7)
(ii) Describe the Interrupt Service Routines used in Operating
System. (6)
BTL 1 Remember
4 (i) Write short notes on I/O Processor. (6)
(ii) What is the need for an I/O Interface? (7) BTL 1 Remember
5 Discuss the steps involved in the address translation of virtual
memory with necessary block diagram. (13) BTL 2 Understand
6 Illustrate in detail about the various memory technologies
and its relevance. (13) BTL2 Understand
7 (i)Discuss the features and operations of PCI (7)
(ii) Discuss the features of USB in detail. (6) BTL2 Understand
8 How do you handle multiple and simultaneous interrupts?
(13) BTL 3 Apply
9 Illustrate in detail about the various mechanisms needed for
choosing I/O devices for any application. (13) BTL 3 Apply
10 Explain the different mapping functions that can be applied
on cache memories in detail. (13) BTL 4 Analyze
11 (i) Explain virtual memory address translation in detail with
necessary diagrams. (7)
(ii) What is meant by Direct Memory Access? Explain the
use of DMA controllers in a computer system. (6)
BTL 4 Analyze
12 Summarize the needs and the importance of Peripheral
Component Interface Bus. (13) BTL 5 Evaluate
13 Summarize the need for Memory Management Technique
with a four level memory. (13) BTL 6 Create
14 (i) Analyze how data transfer done with DMA technique. (7)
(ii) Discuss about the two modes of operation. (6) BTL 6 Create
PART C
1 (i) Explain mapping functions in cache memory to determine
how memory blocks are placed in cache. (8)
(ii) Explain in detail about bus arbitration techniques in
DMA. (7)
BTL 5 Evaluate
2 (i) A block-set-associative cache consists of a total of 64
blocks divided into 4 –block sets. The main memory contains
4096 blocks, each consisting of 128 words.
(a) Evaluate how many bits are there in main memory
address. (4)
(b) Evaluate how many bits are there in each of the TAG,
SET and WORD fields. (5)
(ii) Criticize the following statement: “Using a faster
processor chip results in a corresponding increase in
performance of a computer even if the main memory speed
remains the same”. (6)
BTL 5 Evaluate
3 Design an appropriate interface for connecting a seven
segment display as an output device on a synchronous bus.
(15)
BTL 6 Create
4 A 1024X1024 array of 32 bit numbers is to be normalized as
follows. For each column, the largest element is found and
all elements of the column are divided by this maximum
value. Assume that each page in the virtual memory consists
of 4K bytes, and that 1M bytes of the main memory are
allocated for storing data during this computation. Suppose
that it takes 40ms to load a page from the disk into the main
memory, when a page fault occurs?
(a) How many page faults would occur if the elements of
the array are stored in column order in the virtual
memory? (5)
BTL 6 Create
(b) How many page faults would occur if the elements
are stored in row order? (5)
(c) Estimate the total time needed to perform this
normalization for both the arrangements of (a) and (b).
(5)
