CSC 252: Computer Organization
 Spring 2019: Lecture 12


Instructor: Yuhao Zhu

Department of Computer Science

University of Rochester

Action Items: • Assignment 3 is due March 1, midnight

Carnegie Mellon

Announcement• Programming Assignment 3 is due on March 1, midnight

• Mid-term exam: March 7; in class

• Past exam & Problem set: http://www.cs.rochester.edu/courses/

252/spring2019/handouts.html

2

A3 due

Midterm

Lecture Lecture

Lecture

http://www.cs.rochester.edu/courses/252/spring2019/handouts.html

Carnegie Mellon

3

The Need for Storing Bits• Assembly programs set architecture (processor) states.

• Register File • Status Flags • Memory • Program Counter

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3

The Need for Storing Bits• Assembly programs set architecture (processor) states.

• Register File • Status Flags • Memory • Program Counter

• Every state is essentially some bits that are stored/loaded.

Carnegie Mellon

3

The Need for Storing Bits• Assembly programs set architecture (processor) states.

• Register File • Status Flags • Memory • Program Counter

• Every state is essentially some bits that are stored/loaded.• Think of the program execution as an FSM.

Carnegie Mellon

3

The Need for Storing Bits• Assembly programs set architecture (processor) states.

• Register File • Status Flags • Memory • Program Counter

• Every state is essentially some bits that are stored/loaded.• Think of the program execution as an FSM.• The hardware must provide mechanisms to load and store bits.

Carnegie Mellon

3

The Need for Storing Bits• Assembly programs set architecture (processor) states.

• Register File • Status Flags • Memory • Program Counter

• Every state is essentially some bits that are stored/loaded.• Think of the program execution as an FSM.• The hardware must provide mechanisms to load and store bits.• There are many different ways to store bits. They have trade-offs.

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Build a 1-Bit Storage

4

Q

D

C

Some Logic

•What I would like:

• D is the data I want to store (0 or 1) • C is the control signal

• When C is 1, Q becomes D (i.e., storing the data) • When C is 0, Q doesn’t change with D (data stored)

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Building Block: RS Latch

5

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

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Building Block: RS Latch

5

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

Q+

Q–

R

S

OR

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Building Block: RS Latch

5

0

1

0 1

1 0

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

Q+

Q–

R

S

OR

Carnegie Mellon

Building Block: RS Latch

5

1

0

1 0

0 1

0

1

0 1

1 0

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

Q+

Q–

R

S

OR

Carnegie Mellon

Building Block: RS Latch

5

1

0

1 0

0 1

0

1

0 1

1 0

0

0

!q q

q !q

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

Q+

Q–

R

S

OR

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Building Block: RS Latch

5

R-S Latch

1

0

1 0

0 1

0

1

0 1

1 0

0

0

!q q

q !q

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

Q+

Q–

R

S

OR

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A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

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A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

Stable State(i.e., 1 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

When C is 1, D is 1, Q+ will eventually become 1.

Stable State(i.e., 1 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

When C is 1, D is 1, Q+ will eventually become 1.

Storing 0

1

0 1 1 1 0

0 0 1

Stable State(i.e., 1 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

When C is 1, D is 1, Q+ will eventually become 1.

Storing 0

1

0 1 1 1 0

0 0 1

Stable State(i.e., 1 stored)

Stable State(i.e., 0 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

When C is 1, D is 1, Q+ will eventually become 1.

Storing 0

1

0 1 1 1 0

0 0 1

When C is 1, D is 0, Q+ will eventually become 0.

Stable State(i.e., 1 stored)

Stable State(i.e., 0 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

6

D Latch

Q+

Q–

R

S

D

C

Data

Control

Storing 1

1

1 0 0 0 1

1 1 0

When C is 1, D is 1, Q+ will eventually become 1.

Storing 0

1

0 1 1 1 0

0 0 1

When C is 1, D is 0, Q+ will eventually become 0.

Stable State(i.e., 1 stored)

Stable State(i.e., 0 stored)

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

7

D Latch

Q+

Q–

R

S

D

C

Data

Control

Holding Data

0

d !d q

!q

!q

q0

0

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

7

D Latch

Q+

Q–

R

S

D

C

Data

Control

Holding Data

0

d !d q

!q

!q

q0

0

If C == 0, Q+ doesn’t change with d

Carnegie Mellon

A Simple Way of Storing/Accessing 1 Bit

7

D Latch

Q+

Q–

R

S

D

C

Data

Control

Holding Data

0

d !d q

!q

!q

q0

0

If C == 0, Q+ doesn’t change with d

Stable State(i.e., q held)

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

• When you want to store d, you have to first set C to 1, and then set d

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

• When you want to store d, you have to first set C to 1, and then set d• There is a propagation delay of the combinational circuit from D to Q+

and Q–. So hold C for a while until the signal is fully propagated

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

Carnegie Mellon

D-Latch is “Transparent”

• When you want to store d, you have to first set C to 1, and then set d• There is a propagation delay of the combinational circuit from D to Q+

and Q–. So hold C for a while until the signal is fully propagated• Then set C to 0. Value latched depends on value of D as C goes to 0

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

Carnegie Mellon

D-Latch is “Transparent”

• When you want to store d, you have to first set C to 1, and then set d• There is a propagation delay of the combinational circuit from D to Q+

and Q–. So hold C for a while until the signal is fully propagated• Then set C to 0. Value latched depends on value of D as C goes to 0• D-latch is transparent when C is 1

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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D-Latch is “Transparent”

• When you want to store d, you have to first set C to 1, and then set d• There is a propagation delay of the combinational circuit from D to Q+

and Q–. So hold C for a while until the signal is fully propagated• Then set C to 0. Value latched depends on value of D as C goes to 0• D-latch is transparent when C is 1• D-latch is “level-triggered” b/c Q changes as the voltage level of C rises.

8

C

D

Q+

Time

Changing DLatching

1

d !d !d !d d

d d !d

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

D

C

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control 0

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control 0

1

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control 0

10

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

10

1

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

10

1

->1

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

10

1

->0->1

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control

10

1

->0->1->0

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Edge-Triggered Latch (Flip-Flop)

9

Q+

Q–

R

S

D

C

Data

Control TTrigger

C

D

Q+

Time

T

10

1

->0->1->0

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Edge-Triggered Latch (Flip-Flop)

• Flip-flop: Only latches data for a brief period

9

Q+

Q–

R

S

D

C

Data

Control TTrigger

C

D

Q+

Time

T

10

1

->0->1->0

Carnegie Mellon

Edge-Triggered Latch (Flip-Flop)

• Flip-flop: Only latches data for a brief period

• Value latched depends on data as C rises (i.e., 0–>1); usually called at the rising edge of C

9

Q+

Q–

R

S

D

C

Data

Control TTrigger

C

D

Q+

Time

T

10

1

->0->1->0

Carnegie Mellon

Edge-Triggered Latch (Flip-Flop)

• Flip-flop: Only latches data for a brief period

• Value latched depends on data as C rises (i.e., 0–>1); usually called at the rising edge of C

•Output remains stable at all other times

9

Q+

Q–

R

S

D

C

Data

Control TTrigger

C

D

Q+

Time

T

10

1

->0->1->0

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Registers

• Stores several bits of data

• Collection of edge-triggered latches (D Flip-flops)

• Loads input on rising edge of the C signal

10

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

i7i6i5i4i3i2i1i0

o7o6o5o4o3o2o1o0

C

Structure

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Registers

• Stores several bits of data

• Collection of edge-triggered latches (D Flip-flops)

• Loads input on rising edge of the C signal

10

I O

C

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

DC Q+

i7i6i5i4i3i2i1i0

o7o6o5o4o3o2o1o0

C

Structure

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Register Operation

11

State = x

Output = xInput = yx

C

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Register Operation

11

State = x

Output = xInput = yx

C Rises

C

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Register Operation

11

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

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Register Operation

• Stores data bits

• For most of time acts as barrier between input and output

• As C rises, loads input

• So you’d better compute the input before the C signal rises if you want

to store the input data to the register

11

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

Carnegie Mellon

Register Operation

• Stores data bits

• For most of time acts as barrier between input and output

• As C rises, loads input

• So you’d better compute the input before the C signal rises if you want

to store the input data to the register

11

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C Output continuously produces y after the rising edge unless you cut off power.

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Clock Signal

• A special C: periodically oscillating between 0 and 1

• That’s called the clock signal. Generated by a crystal oscillator

inside your computer

12

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

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Clock Signal

• A special C: periodically oscillating between 0 and 1

• That’s called the clock signal. Generated by a crystal oscillator

inside your computer

12

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

Clock

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Clock Signal

• A special C: periodically oscillating between 0 and 1

• That’s called the clock signal. Generated by a crystal oscillator

inside your computer

12

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

Clock

x0 x1 x2 x3 x4 x5In

Carnegie Mellon

Clock Signal

• A special C: periodically oscillating between 0 and 1

• That’s called the clock signal. Generated by a crystal oscillator

inside your computer

12

State = x

Output = xInput = yx

C RisesState = y

Output = yy

C

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Carnegie Mellon

Clock Signal

• Cycle time of a clock signal: the time duration between two rising edges.

13

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Carnegie Mellon

Clock Signal

• Cycle time of a clock signal: the time duration between two rising edges.

13

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Cycle time

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Clock Signal

• Cycle time of a clock signal: the time duration between two rising edges.• Frequency of a clock signal: how many rising (falling) edges in 1 second.

13

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Cycle time

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Clock Signal

• Cycle time of a clock signal: the time duration between two rising edges.• Frequency of a clock signal: how many rising (falling) edges in 1 second.• 1 GHz CPU means the clock frequency is 1 GHz

13

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Cycle time

Carnegie Mellon

Clock Signal

• Cycle time of a clock signal: the time duration between two rising edges.• Frequency of a clock signal: how many rising (falling) edges in 1 second.• 1 GHz CPU means the clock frequency is 1 GHz

• The cycle time is 1/10^9 = 1 ns

13

Clock

x0 x1 x2 x3 x4 x5In

x0 x1 x2 x3 x4 x5Out

Cycle time

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Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

2 x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out

2 x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out

ReadsrcA

valA 2 x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out

ReadsrcA

valA 22

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out

ReadsrcA

valA 2x2

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value

ReadsrcA

valA 2x2

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value

Read WritesrcA

valA

dstW

valW2x2

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value

Read WritesrcA

valA

dstW

valW2x2

y2

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value

Read WritesrcA

valA

dstW

valW2x2

Risingedge

y2

x

Register File

1 z

w3

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value

Read WritesrcA

valA

dstW

valW2x2

Risingedge

y2

x

Register File

1 z

w3

y

Clock

Carnegie Mellon

Register File

14

• A register file consists of a set of registers that you can individual read from and write to.

• To read: give a register file ID, and read the stored value out• To write: give a register file ID, a new value, overwrite the old value• How do we build a register file out of individual registers??

Read WritesrcA

valA

dstW

valW2x2

Risingedge

y2

x

Register File

1 z

w3

y

Clock

Carnegie Mellon

Register File Read

15

Register 0

Register 1

Register 2

Register 3

D

C

D

C

D

C

D

C

• Continuously read a register independent of the clock signal

Carnegie Mellon

Register File Read

15

Register 0

Register 1

Register 2

Register 3

D

C

D

C

D

C

D

C

4:1 MUX

Read Reg ID

Out

• Continuously read a register independent of the clock signal

Carnegie Mellon

Register File Write

16

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

4:1 MUX

Read Reg ID

Out

Carnegie Mellon

Register File Write

16

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

4:1 MUX

Read Reg ID

Out

Carnegie Mellon

Register File Write

16

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

4:1 MUX

Read Reg ID

Out

Clock

Carnegie Mellon

Register File Write

16

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

4:1 MUX

Read Reg ID

Out

Clock

• Only write the a specific register when the clock rises. How??

Writ

e R

eg ID

W1

W0

Carnegie Mellon

Register File Write

16

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

4:1 MUX

Read Reg ID

Out

Clock

• Only write the a specific register when the clock rises. How??

W1 W0 C3 C2 C1 C00 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0

Writ

e R

eg ID

W1

W0

Carnegie Mellon

Decoder

17

W1 W0 C3 C2 C1 C0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

W1W0 C0

C1

C2

C3

Carnegie Mellon

Decoder

17

C0 = !W1 & !W0

C1= !W1 & W0

C2 = W1 & !W0

C3 = W1 & W0

W1 W0 C3 C2 C1 C0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

W1W0 C0

C1

C2

C3

Carnegie Mellon

Decoder

17

C0 = !W1 & !W0

C1= !W1 & W0

C2 = W1 & !W0

C3 = W1 & W0

W1 W0 C3 C2 C1 C0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

W1W0 C0

C1

C2

C3

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

0

1

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

0

1

0

0

0

1

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

0

1

0

0

0

1

Carnegie Mellon

Register File Write

18

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out

0

1

0

0

0

1

• This implementation can read 1 register and write 1 register at the same time: 1 read port and 1 write port

Carnegie Mellon

Multi-Port Register File

19

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out1

0

1

0

0

0

1

•What if we want to read multiple registers at the same time?

Carnegie Mellon

Multi-Port Register File

19

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out1

0

1

0

0

0

1

•What if we want to read multiple registers at the same time?

4:1 MUX

Out2

Read Reg ID 2

Carnegie Mellon

Multi-Port Register File

19

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out1

0

1

0

0

0

1

•What if we want to read multiple registers at the same time?

4:1 MUX

Out2

Read Reg ID 2

• This register file has 2 read ports and 1 write port. How many ports do we actually need?

Carnegie Mellon

Multi-Port Register File

20

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out1

0

1

0

0

0

1

• Is this correct? What if we don’t want to write anything?

4:1 MUX

Out2

Read Reg ID 2

Carnegie Mellon

Multi-Port Register File

20

Register 0

Register 1

Register 2

Register 3

D

C0

D

C1

D

C2

D

C3

Data

Clock

2:4Decoder

Writ

e R

eg ID

4:1 MUX

Read Reg ID

Out1

0

1

0

0

0

1

• Is this correct? What if we don’t want to write anything?

4:1 MUX

Out2

Read Reg ID 2

Enable

Carnegie Mellon

Executing an ADD instruction

21

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Clock

Register File

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Clock

Register File

Read Reg. ID 1

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Clock

Register File

Read Reg. ID 1

Read Reg. ID 2

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Clock

Register File

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Clock

Register File

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

What Logic?

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

22

• How does the processor execute addq %rax,%rsi • The binary encoding is 60 06

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

AddInstruction Code Function Code

newData

Memory(Later…)

PC

Enable

What Logic?

6006…

s0s1s2s3

Clock

FlagsZ S O

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

6006…

s0s1s2s3

FlagsZ S O

Clock

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

FlagsZ S O

Clock

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

FlagsZ S O

Clock

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

FlagsZ S O

Clock

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

nPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

nPCoPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

nPCoPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;• Logic 3: if (s0 == 6) nPC = oPC + 2;

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

nPCoPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;• Logic 3: if (s0 == 6) nPC = oPC + 2;• How about Logic 4?

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Clock

nPCoPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;• Logic 3: if (s0 == 6) nPC = oPC + 2;• How about Logic 4?

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Logic 4

Clock

nPCoPC

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;• Logic 3: if (s0 == 6) nPC = oPC + 2;• How about Logic 4?

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

FlagsZ S O

Logic 4

Clock

nPCoPC

How do these logics get implemented?

Carnegie Mellon

Executing an ADD instruction

23

• Logic 1: if (s0 == 6) select = s1;• Logic 2: if (s0 == 6) Enable = 1; else Enable = 0;• Logic 3: if (s0 == 6) nPC = oPC + 2;• How about Logic 4?

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

PC

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Logic 3

Risingedge

FlagsZ S O

Logic 4

Clock

nPCoPC

How do these logics get implemented?

Carnegie Mellon

Executing an ADD instruction

24

• When the rising edge of the clock arrives, the RF/PC/Flags will be written.

• So the following has to be ready: newData, nPC, which means Logic1, Logic2,

Logic3, and Logic4 has to finish.

ALU

Select

Clock

Register File

Write Reg. ID

Read Reg. ID 1

Read Reg. ID 2

Reg 1 Data

Reg 2 Data

addq rA, rB 6 0 rA rB

newData

Memory(Later…)

Enable

Logic 1

Logic 2

6006…

s0s1s2s3

Risingedge

FlagsZ S O

PC

Logic 3

Clock

nPCoPC

Logic 4