Ahmed Mumtaz Mustehsan, CIIT, Islamabad

CSC 322 Operating Systems Concepts

Lecture - 23:by

Ahmed Mumtaz Mustehsan

Special Thanks To:Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. (Chapter-5) Silberschatz, Galvin and Gagne 2002, Operating System Concepts,

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Chapter 5Input/ Output

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• OS controls I/O devices => • Issue commands, • handles interrupts, • handles errors

• Provide easy to use interface to devices• Hopefully device independent

• First look at hardware, then software• Emphasize software• Software structured in layers• Look at disks

Overview

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• Some typical device network, and bus data rates.

I/O Devices

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• Two types of I/O devices- block, character• Block

Can read blocks independently of one another• Hard disks, CD-ROMs, USB sticks• 512 to 32,768 bytes

• CharacterAccepts stream of characters without block structure• Printers, mice, network interfaces

• Not everything fits, e.g. clocks don’t fit• Division allows for OS to deal with devices in device

independent manner• File system deals with blocks

Overview

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• A is track, B is sector, C is geometrical sector, D is cluster

Disk geometry

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• I/O unit has 2 components-mechanical, electronic (controller)

• Controller is a chip with a connector which plugs into cables to device sometimes more than one of identical devices like SCSI controllers can handle 8 drives including (CD drive)

• Disk• Disk might have 10,000 sectors of 512 bytes per

track or different spec.• Serial bit stream comes off drive• Has preamble 4096 bits/sector, error correcting

code• Preamble has sector number, cylinder number,

sector size….

Device Controllers

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• Controller assembles block from bit stream, does error correction, puts into buffer in controller

• Blocks are what are sent from a disk

Device Controllers

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• Controller has registers which OS can write and read

• Write- means OS gives command to device• Read- means OS learns device status……• Devices have data buffer which OS can

read/write (e.g. video RAM, used to display pixels on a screen)

• How does CPU communicate with registers and buffers?

Memory Mapped I/O

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(a) Separate I/O ports and memory space. (e.g. IBM-360)(b) Memory-mapped I/O. (e.g. PDP-11)(c) Memory mapped data buffers and separate ports

hybrid approach (e.g. Pentium, 0 to 64K I/O ports and 64K to1MB device data buffer)

Memory-Mapped I/O

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• First scheme (Separate memory and I/O space) • When CPU wants to read from memory or I/O

port, it : • Puts read on control line• Puts address on address line• Puts I/O space or memory space on separate 2nd

signal line to differentiate Read from memory space or I/O space

• It requires special I/O instructions (IN/OUT assembly language) to read and write device registers

• Memory mapped approach• Put address on address line and let memory

and I/O devices compare address with the ranges they serve and respond accordingly.

How CPU addresses registers and buffers

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• Don’t need special instructions to read/write control registers=> can write a device driver in C

• Don’t need special protection to keep users from doing I/O directly.

• Put each device drivers on different address space, on different pages, avoid conflict.

• Allocate driver pages to user address space, hene:• Reduce kernel size• Avoid device drivers interfering with others.• Avoid crash of OS due to buggy driver.

Memory mapped advantages

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• Every instruction that can reference memory can reference control registers as well.

Example:LOOP TEST PORT_4 //check if port 4 is zero BEQ READY //it is zero, go to ready BRACCH LOOP //otherwise, continue testingREADY:

• If no memory map I/O instruction just references registers, the registers are to be loaded in CPU, then tested, need more instructions to do the test-read

• Slowing down the response of detecting idle devices.

Memory mapped advantages contd…

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Caching a device control Register:• caching device status memory words, which means

that old memory value (e.g. for port 4) could remain in cache , no status update, loop forever.Solution: Hardware should be able to disable caching when it is worthwhile

I/O devices and memory have to respond to memory references:• Works with single bus because both memory and

I/O look at address on bus and decide which one to respond?

• Harder with multiple buses because I/O devices can’t see their addresses referred to the buses not connected with.

Memory mapped disadvantage

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• (a) A single-bus architecture. (b) A dual-bus memory architecture.

Memory-Mapped I/O

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Solution-1: Try I/O devices if memory bus not respond• CPU to try memory first. If it does not get a response

then it tries I/O devices.Solution-2: Put Snooping device.• The snoopy device pass all addresses of potent5ial

interest of I/o devices.• I/O devices may not be able to match the speed of

memory bus.Solution-3: Filter addresses (Pentium approach)• Filter addresses e.g. 640K to 1MB could be marked as

non memory range forwarded to PCI bus instead of memory.

• Main point-have to complicate hardware to make this work

Memory-Mapped I/O

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• CPU COULD request data one byte at a time from I/O controller.

• Big waste of CPU time, use DMA• DMA controller on mother-board; normally one

controller for multiple devices• CPU reads/writes to registers in DMA controller:

• Memory address register• Byte count register• Control registers

I/O port, direction of transfer, transfer units (byte/word), transfer mode, number of bytes to transfer in a burst

DMA

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• Controller reads a block into its memory buffer• Computes checksum (e.g. ECC )• Interrupts OS• Now OS reads byte at a time or word at a time

from controllers buffers and stores it in to the main memory

When DMA is not used

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• Operation of a DMA transfer.

How does DMA work?

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Step-1:CPU programs the DMA controller registers what and where to transfer. It also instructs DC to read the data from disk into its buffer and perform checksum.Step-2: DMA controller issues a read request over a bus to disk controller. The DC reads the memory address to write,Step-3: Write to memory is another bus cycle.Step-4: After memory write, DC send ack. to DMA over the bus.• DMA increment memory address and decrement

word count , if count > 0 repeat step-1 to step-4.• Otherwise, If byte count is zero, DMA interrupt CPU

that memory transfer is complete.

How does DMA work?

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• Cycle stealing mode-transfer goes on word at a time, competing with CPU for bus cycles. Idea is that CPU loses the occasional cycle to the DMA controller called cycle stealing.

• Burst mode-DMA controller grabs bus and sends a block

• Fly by mode-DMA controller tells device controller to send word to it instead of memory. Can be used to transfer data between devices. (e.g. memory to memory)

DMA controller modes

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• Why buffer data in controllers? • Can do check-sum• Bus may be busy-need to store data

someplace• Is DMA really worth it?

Not if :• don’t have too much data to transfer. • CPU is much faster than DMA controller and

can do the job faster. • Embedded system CPU is free; can be used for

data transfer

Quiz

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• The connections between the devices and the interrupt controller use interrupt lines on the bus rather than dedicated wires. (sets interrupt bit)

PC interrupt structure

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• Each devise asserts a signal on a bus assigned until attended by Interrupt controller.

• Controller detects and distinguish the interrupt signal by the device.

• If no other interrupt pending it immediately process the interrupt. Otherwise process high priority interrupt, and ignores the interrupt.

• Controller puts number on address line telling CPU which device wants attention

• Table (interrupt vector) points to interrupt service routine

• Number on address line acts as index into interrupt vector

• Interrupt vector contains PC which points to start of service routine

Interrupt processing

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• Interrupt service routine acks interrupt• Saves information about interrupted program• Where to save information

• User process stack, kernel stack are both possibilities

• Both have problems• User process, stack pointer might me illegal

may cause fatal error or stack pointer at the end of page may cause page fault, interrupt causing interrupt, difficult to handle that where to save state?

• Save to kernel stack, legal stack pointer, but trap to kernel space, change MMU, will invalidate TLB and cache, reloading all these is time consuming

Interrupt processing

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• Sure, if we don’t use pipelined or superscalar CPU’s. But we do use them.

• Can’t assume that all instructions up to and including given instruction have been executed

• Pipeline-bunch of instructions are partially completed

• Superscalarinstructions are decomposed and can execute out of order

Can we save the PC and PSW?

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