CSC N901 specificationeshine-ic.com/Upfiles/down/20185482459.pdf · With 16KB I-Cache and 8KB...

WUHAN ESHINE TECHNOLOGY CO., LTD

www.eshine-ic.com - 1 - 2014/01/05 V1.3

CJC3912 Andes N9-based 32-BIT MCU

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CJC3912

Features 32-bit microprocessor

AndesCore N9 @ 122MHz With 16KB I-Cache and 8KB D-Cache Boot from SPI Flash Integrate JTAG port to support real time,

non-stop ICE function for system development and debugging 72KB internal SRAM

Embedded 72KB high-speed SRAM for code + data Internal ROM

256*32bit Internal ROM to keep product ID

SPI_Boot High Speed SPI Interface Support XIP(execute in place) from SPI flash Speed up to 30MHz

Audio Process Unit Stereo 24-bit Sigma-Delta ADC and DAC 2-ch Audio LINEIN and Stereo Headphone

output 1-ch Stereo MIC input, built in low-noise

microphone bias

www.eshine-ic.com - 2 - 2014/01/05 V1.3 Copyright © 2014, WUHAN ESHINE TECHNOLOGY CO., LTD

Bi-directional serial programmable audio interface supporting PCM/I2S formats ADC

2-ch 10-bit SAR ADC Maximum coversion rate: 400K samples per

second Analog input voltage range: 0.8-2.5V @

3.3V Power TouchKey

Up to 13 Touch Key pin Programmable Sensitivity and Stability

USB2.0 Controller Compliant with USB specification revision

2.0 Dual role USB that can function as host or

slave Supprt High-Speed,Full-Speed, Low-Speed

Mode Compatible with EHCI 1.0 Built in DMA for real time data transfer Support USB Hub function

DMA Controller provides up to 8 configurable channels

INTC(Interrupt controller) Support 32 interrupt inputs

Provide both edge and level triggered interrupt source with positive and negative directions I2C

Compatible with Philips I2C standard SPI

Programmable Master/Slave mode Speed up to 30MHz

UART *2 Three UART ports with flow control(TX, RX,

CTS, RTS) Baud rate up to 921.6Kbps

SD Controller SD/SDHC/SDIO/MMC Support SD2.0 with capacity up to 32GB

PWM * 3 Auto reload mode or one-shot pulse mode

Capture and compare function

Three programmable 32-bit Timers One 32-bit Watch Dog Timer 32.768KHz RTC function support Three groups GPIO and total of 36 GPIO ports

GPIOA, GPIOB, GPIOC all have alternate functions Power Control

The clock and power of All Peripheral module can be individually turned off

Internal LDO generate 1.8V @ 250mA power supply

Support four power mode: Idle, Standby, Sleep and Normal mode

GPIOx[7:0] can wakeup CJC391x from Sleep mode

100mA @ Normal Mode, 1mA @ Sleep Mode Package: LQFP80

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CJC3912


Contents 1. Description.............................................................................................................................................5

1.1. Device Overview.......................................................................................................................6 1.2. System Diagram .......................................................................................................................7 1.3. System Clock Diagram ............................................................................................................8

2. Overview ................................................................................................................................................9

2.1. Andes N9@ 32bits RISC Code ..............................................................................................9 2.2. Embedded SRAM.....................................................................................................................9 2.3. Embedded ROM.......................................................................................................................9 2.4. PLL .............................................................................................................................................9 2.5. RTC ..........................................................................................................................................10 2.6. DMA controller ........................................................................................................................10 2.7. Interrupt controller ..................................................................................................................10 2.8. USB2.0 controller ...................................................................................................................10 2.9. SD/SDHC/SDIO/MMC controller..........................................................................................11 2.10. Audio process unit..............................................................................................................11 2.11. SARADC..............................................................................................................................11 2.12. LDO ......................................................................................................................................12 2.13. LVR .......................................................................................................................................12 2.14. IIC .........................................................................................................................................12 2.15. SPI ........................................................................................................................................12 2.16. UART....................................................................................................................................12 2.17. PWM.....................................................................................................................................13 2.18. Timer ....................................................................................................................................13 2.19. Watchdog.............................................................................................................................13 2.20. GPIO ....................................................................................................................................13 2.21. Touchkey controller ............................................................................................................14 2.22. Embedded Debug ..............................................................................................................14 2.23. Boot Mode ...........................................................................................................................14

3. Pinouts and Pin Descriptions ............................................................................................................15

3.1. LQFP-80 Package..................................................................................................................15 3.2. Pin Description........................................................................................................................16

4. Memory Mapping ................................................................................................................................18

5. Electrical Characteristics ...................................................................................................................20

5.1. Absolute Maximum Ratings ..................................................................................................20 5.2. Recommended Operating Conditions .................................................................................20 5.3. Current Characteristics..........................................................................................................21

5.3.1. Normal mode supply current Characteristics .........................................................21 5.3.2. Sleep mode supply current Characteristics............................................................22

5.4. GPIO Characteristics .............................................................................................................23

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5.5. Audio Characteristics.............................................................................................................24 5.5.1. Line Input to ADC Characteristics ............................................................................24 5.5.2. Microphone Input to ADC Characteristics...............................................................24 5.5.3. DAC to LINEOUT Characteristics ............................................................................25 5.5.4. DAC to HeadPhoneOut(No Capacitor) Characteristics ........................................26 5.5.5. DAC to HeadPhoneOut(Couple Capacitor) Characteristics ................................26 5.5.6. LINEIN to HEADPHONE OUT Characteristics ......................................................27

5.6. SARADC characteristics .......................................................................................................27 5.7. PLL characteristics .................................................................................................................28

5.7.1. System PLL .................................................................................................................28 5.7.2. USB PLL ......................................................................................................................28

5.8. Touch Key Controller Characteristics ..................................................................................28

6. Typical Application Instruction ..........................................................................................................29

6.1. Specified application scenario description..........................................................................29

7. Application Circuit ...............................................................................................................................32

8. Package (LQFP80).............................................................................................................................33

9. Part Numbering ...................................................................................................................................34

10. Revision History..............................................................................................................................35

11. NOTICES.........................................................................................................................................35

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CJC3912


1. Description

The CJC391x family is a high-performance and low-cost MCU targets for various applications, like MP3, Bluetooth Communication, Toys, Storage Control, and so on. The CJC391x family embeds a high-performance and low-power AndesCore N9 microprocessor which is 32-bit RISC process with 5-stage pipeline to provide high DMIPS per watt. It is also a versatile SoC with highly integrated peripherals that includes internal 72KB high-speed SRAM, high-performance audio process unit, and many on chip controllers such as USB2.0 Host/Slave, UART, SPI, I2C, SDIO, I2S/PCM, PWM, TIMER, TouchKey, GPIO and etc. The CJC391x family support XIP( execute in place ) and boots from SPI Flash directly. It can also run at internal SRAM after boot up. In order to improve the system security, on-chip ROM store the device ID as application indentification mark. The Andes-N9 runs up to 122MHz on the high-speed SRAM to offer enough horsepower for many MIPS-hungry tasks, while the remaining MIPS is still able to serve the need of application program. The CJC391x family is designed with special care to minimize the power consumption while allowing for the flexibility to reach for high performance. It includes the clock gating for individual IP, and The CJC391x family can be further operated under different power-saving modes: Normal, Idle, Standby, Sleep, different mode have different clock and power strategy. CJC391x Application domains as following: Car audio equipment Music center equipment Iphone/ipad soundbox Boombox Wireless headphone Handfree car kits Internet radio Toys Edutainment robots Home application On-click reader Bluetooth sport equipment

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CJC3912


1.1. Device Overview

Table 1. The CJC391x Family features and hardware function

Peripherals CJC3914A CJC3914B CJC3912 CJC3911 SRAM (KB) 72 Timer 3 Watch dog 1 10Bits SARADC 2 2 2 4 I2C 1 24bit Audio DAC 1 24bit Audio ADC 1 PWM -- -- 3 4 UART 2 2 2 3 SPI 1 1 2 2 SD/SDIOMMC 1 1 1 2 I2S(PCM) -- -- 1 1 Touch Key 12 12 13 24 Audio line Out / HP_OUT 1 Audio line In 2 MIC IN 1 USB 1 -- 1 1 JTAG -- -- -- 1 GPIOA mux_ctl_gpioxx[]=2'b01 12 12 12 21 GPIOB mux_ctl_gpioxx[]=2'b10 4 4 11 21 GPIOC mux_ctl_gpioxx[]=2'b11 12 12 13 24 GPIOD -- -- -- 10 CPU frequency 98.3MHz (Default) Operating voltage 3.3V Operating temperatures -20 to 70 Package QFN64 QFN64 LQFP80 LQFP128 1. CJC391x is only boot from the external serial flash, you can connect them with SPIB interface.

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CJC3912

1.2. System Diagram


Andes N9 CPU

Fmax:122MHz

16KB I-Cache8KB D-Cache

SRAM 72KB

DMA Core

USB2.0 OTG Controller

APU Audio Codec

SPI Boot From SPI FLASH

(Max 64MBit)

SPIMaster/Slave

AH

B：

Fm

ax:6

1MH

z

TouchKey

UART1

UART2

I2C

32-Bit Timer1

32-Bit Timer2

32-Bit Timer3

10Bit SAR ADC

SD1

GPIO Port A

GPIO Port C

GPIO Port B

WDT

INT Controller

PCU

RTC

SYS_PLL

LVR

JTAG 3.3V Power

APB

： F

max

:30M

Hz

APB

： F

max

:30M

Hz

AUD_LLIN1AUD_RLIN1AUD_LLIN2AUD_RLIN2AUD_LMICINAUD_RMICINAUD_LHPOUT

AUD_RHPOUTHP_VMID

APB

I2S_BCLK/PCM_BCLKI2S_LRC/PCM_SYNCI2S_DIN/PCM_DINI2S_DOUT/PCM_DOUT

SPIB_CSn

SPIB_SCKSPIB_SISPIB_SO

UART1_RTS

UART1_TXDUART1_RXDUART1_CTS

GPIOA11

GPIOA8GPIOA9GPIOA10

UART2_TXDUART2_RXD

GPIOA12GPIOA13

I2C_SCLI2C_SDA

GPIOA6GPIOA7

AIN0AIN1

USB_VBUS_VALIDUSB_DRV_VBUS

USB_RESUSB_DMUSB_DP

GPIOA4GPIOA5

X32KO

TPX2TPX3TPX4

TPX9TPX10TPX11TPX12TPX13

TPX6TPX7TPX8

SD1_CDSD1_CLKSD1_CMDSD1_DAT0

GPIOB14GPIOB15GPIOB16GPIOB17

GPIOA[1:0]

GPIOC13GPIOC12

GPIOC14

GPIOC19GPIOC20GPIOC21GPIOC22GPIOC23

GPIOC16GPIOC17GPIOC18

XTAL OSC 26MHz

X26MI

X26MO

USB_PLL12MHz

Core_CLKAHB_CLKAPB_CLKAPU_CLK

TouchKey_CLK

X32KI

X32KO

XTAL 32KHz

1.8V LDO

3.3V AVDD3.3V DVDD

1.8V@250mA, DVDD181.8V Digital Core

1.8V USB Core

POR

AVDD18_USB

GPIOA0GPIOA1

CJC3912 RESETn

TPX_ROUTTPX_COUT

TouchKey Sensitivity Adjust

SPIMS_CSn

SPIMS_SCKSPIMS_SISPIMS_SO

GPIOB7

GPIOB4GPIOB5GPIOB6

GPIOA[13:4]

GPIOB[7:4]GPIOB[17:14]

GPIOC[14:12]GPIOC[23:16]

PWMPWM0PWM1PWM2

GPIOB0GPIOB1GPIOB2

TPX14TPX15

GPIOC0GPIOC1

GPIOC[1:0]

USB_DRV_VBUSX32KO GPIOA4

1. GPIOA, GPIOB, GPIOC can’t be used together, once only using one group of them. 2. DVDD18 can output 1.8V/250mA power supply. 3. AVDD18_USB most be connect with DVDD18 in the PCB, otherwise USB can’t be used. 4. X32KO can output 32.768KHz clock.

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CJC3912

1.3. System Clock Diagram


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CJC3912


2. Overview

2.1. Andes N9@ 32bits RISC Code

Andes N9 core is a 32-bit CPU with 5-stage pipeline, it support 16/32bit mixed instruction format, support multiply-accumulate and multiply-subtract instruction and support static branch prediction. It has 16/32 generation 32bit registers. The processor support vector interrupts for interrupt and external interrupt controller, it support 2/3 HW-level nested interruption. It supports AHB, APB, AHB Lite and AMI interface in synchronous and asynchronous mode with low latency.

2.2. Embedded SRAM

The embedded high-speed SRAM is designed for both program code and scratchpad data RAM. The CJC391x family include several part SRAM, the processor have a 72KB SRAM act as the system memory, 2*8KB SRAM act as the data cache and instruction cache, another the DMA module have SRAM to act as data transfer FIFO, APU module have SRAM to store the middle-step calculation result. The 72KB SRAM is an AHB device, it provide data to N9 processor, processor decode the data and configure the system, update data cache and instruction, execute the instruction. The CJC391x family, 72KB SRAM act as system memory, when system boot up, the high-speed direct SPI interface read the system configuration, OS and application program to the SRAM. After system is boot, the 72KB SRAM will be mapped to system memory space in a continuous address space which from 0x8000,0000,this will be decrypted in following memory mapping part.

2.3. Embedded ROM

The CJC391x family integrate a 256*32bit ROM on chip, it used to store chip ID. ROM module is separated and not on AHB or APB bus.

2.4. PLL

PLL system and block level clock from an external 26MHZ crystal. The CJC391x family have two external crystals, one is 26MHZ active crystal for internal PLL usage, the other is 32.768KHZ for on-chip RTC. The CJC391x family have two PLL, one is system PLL and another is USB_PLL, system PLL receive the 26MHZ crystal and generate system clock according to the APU sampling

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CJC3912


rate. The PLL output is send to digital divide circuit and generates the division clock for each block according to the CLK-DIV configuration register. USB_PLL receive 26MHz input and generate constant 12MHZ PLL output for USB module usage, the clock jitter is about 200ppm.

2.5. RTC

The CJC391x family chip integrate on-chip RTC, this module is on APB bus as a slave device. It will work continuously whether system is active or not, it provides year, month, date, hour, minute, second information for the system and software can configure and modify the year, month, date, hour, minute, second data. The CJC391x family RTC module has an independent crystal 32.768KHZ, this crystal is divided to 1HZ and send to the RTC counter module. The CJC391x family RTC provides a programmable auto-alarm function. When thesecond-auto-alarm function is turned on, the RTC will auto-trigger an interrupt each second. The automatic minute and hour alarm can be turned on as well. This function is useful for implementing a clock.

2.6. DMA controller

The CJC391x family DMA controller is an AHB slave device and Compliant with AMBA v2.0, it is designed to enhance the system performance and reduce the processor-interrupt generation. The System efficiency is improved by employing the high-speed data transfers between the system and the device. Can be used with the main peripherals: SPI, USB, UART, SD, SRAM, APU, general-purpose.

2.7. Interrupt controller

The CJC391x family interrupt controller module is an APB device, it has IVIC (internal vector interrupt controller) mode and EVIC (external vector interrupt controller) mode to communicate with CJC391x CPU. It support 32 IVIC HW0 (FIQ) priority level interrupt inputs, support 32 IVIC HW1 (IRQ) priority level interrupt inputs, share the 32 HW0 (FIQ) and 32 HW1 (IRQ) interrupt inputs as 32 EVIC interrupt inputs, provide 0(min.)~7(max.) configurable priority levels for each EVIC interrupt input. The output signals to the microprocessor can be configured as either active high or active low.

2.8. USB2.0 controller

The CJC391x family USB controller is an AHB device, the main function is to implement the data transfer between CJC391x system and external USB master device or USB slave device. Other functions and features as following:

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USB PHY compliance with UTMI+ specification version 1.0 USB controller compliance with UTMI+ level 2 Support high speed, full speed, low speed but no preamble packet Built in DMA for real time data transfer Exclusive support USB host and USB device in one specified application SYNC field and EOP detection on receive packet and transmit packet Support USB hub function Only support USB read function Not support system boot from USB

2.9. SD/SDHC/SDIO/MMC controller

The CJC391x family chip integrate SD card controller module, the module is an APB bus interface, it implement the data transfer from external SD card and CJC391x system, and not support write to SD card. It can transfer large data by DMA. CJC391x Secure Digital (SD) host controller functions as the master in an SD memory card interface. It controls the communication between the AHB/APB bus and the SD card. The core supports the SD bus protocol of the SD cards and MMC bus of MMC operation as well.

2.10. Audio process unit

The CJC391x family APU module is an AHB device, it is mixed by a 16-bit analog module and a 16-bit digital module, it receive the analog signal and transfer to digital data signal and exchange and transmit to CJC391x other module controlled by CJC391x processor, it also exchange and receive from CJC391x other module, transfer them to analog signal and exchange with external circuit which is controlled by CJC391x processor. APU module includes two analog modules, one is 16-bit sigma-delta ADC, the other is 16-bit sigma-delta DAC, and they are co-work with digital filter to implement high-performance analog-to-digital and digital-to-analog transfer.

2.11. SARADC

10-bit SARADC module is an APB bus device, the main function of this module is sample the external sensor, voltage signal, transfer them to digital data by SARADC block, update the status register and interrupt signal, exchange data with CJC391x processor. The maximum sampling rate is 400KHZ. After finishing one round, interrupt signal will generate, processor will respond this interrupt and enter into ISR.

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2.12. LDO

The CJC391x family LDO implement the power transfer from 3.3V to 1.8V, this LDO is a high driven capability which output drive the whole chip digital logic.

2.13. LVR

The CJC391x family LVR module is a low voltage reset generation module, it is an APB device. The main circuit in this module is comparator, it comparator the supply voltage with the configured threshold, if the supply is lower than the threshold, reset will be generated and send to all others module, then CJC391x will enter into reset state. The threshold for reset is programmable.

2.14. IIC

The CJC391x family IIC bus interface controller is an APB device, it allows the host processor to serve as a master or slave in the IIC bus. Data are transmitted to and received from the IIC bus via a buffered interface. It is Compliant with AMBA 2.0 APB, Supports the stand and fast modes by programming the clock division register, support the 7-bit, 10-bit, and general-call addressing modes. It has glitch suppression capability through the debounce circuit. The salve address is Programmable, it supports the master-transmit, master-receive, slave-transmit, and slave-receive modes, and supports the multi-master mode also.

2.15. SPI

The CJC391x family, there are two SPI modules, one is dedicated for system boot, and another is a normal APB device SPI. The dedicated boot SPI is an AHB device and also an APB device, when system boot, this SPI act as a AHB device and support high-speed data transfer (up to 30MHz), when CJC391x system write back to external FLASH, this dedicated SPI act as an APB device and write back in normal speed. The dedicated SPI transfer data between external FLASH with on-chip using hardware handshake mode, not need system assign a DMA channel. The SPI of APB device is a normal SPI module, it is a synchronous serial port interface that allows the host processor to serve as a master or a slave. It can connect to various devices by using serial protocol.

2.16. UART

The CJC391x family chip have two UART interface, there are all APB devices. Each UART have a programmable interrupt to the system.

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CJC3912


The CJC391x family UART support two work mode: UART mode, SIR mode. It also supports IRDA1.3 SIR Protocol which is used in household electrical device IR transmitter and receiver (38KHZ).

2.17. PWM

The CJC391x family have four 16-bit PWM timers. The duty control of PWM output waveform is programmable. It’s selected between Auto reload mode and one-shot pulse mode. They have capture and compare functions.

2.18. Timer

The CJC391x family timer module is an APB device, it provides three independent sets of 32-bit sub-timers, and the first one is the default sub-timer. Each sub-timer can use either internal system clock (PCLK) or external clock (EXTCLK) to increase or decrease the counting. Two match registers are provided for each sub-timer. Whenever the value of the match registers equals to any one of the sub-timers, the timer interrupt is triggered immediately. The issuance of the timer interrupt can be decided by the register setting when an overflow occurs. CJC391x System assigns 3 interrupt for timer.

2.19. Watchdog

The CJC391x family watchdog module is an APB bus device. It’s used to prevent the system from the infinite loop if the software gets trapped in the deadlock. In the normal operation, the user restarts the WDT at the regular intervals before the counter (a 32-bit down counter) counts down to 0. If the counter does reach 0, the WDT generates one or a combination of the signals, system reset, system interrupt, or external interrupt to reset the system, interrupt the system, or interrupt an external device correspondingly.

2.20. GPIO

The CJC391x family GPIO controller module is a user-programmable general-purpose input/output controller. It is used to input/output data from the system and device. Each GPIO can be programmed as an input or output. GPIOx can also be an interrupt input, and it supports at the rising edge, falling edge, both edge, and the high/low level interrupt sense types. Only GPIOx[7:0] can wakeup CJC391x from Sleep mode

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2.21. Touchkey controller

The CJC391x family module integrate touchkey controller module, it is an APB bus device. It sample the external touchkey action and transfer to internal trigger signal, processor get this trigger signal and respond to the external touch action. Touchkey controller module support up to 11 touchkey input, when detect the touch action, the controller module generates the interrupt signal to processor, interrupt signal is high level active and clear by the ISR. It can support glass, ceramics and plastic medium surface, support multi-key mode or single-key mode, it have programmable sensitivity and stability, programmable touch maximum open-time and programmable Re-Calibration Time.

2.22. Embedded Debug

The CJC391x family processor provides an embedded debug module to allow programmers perform debugging activities through a standard JTAG interface.

2.23. Boot Mode

The system has two SPI, one is high-speed SPI which is on both AHB bus and APB bus, the other is an APB device SPI which can be configured as master or slave. System boot use the high-speed SPI, read is as AHB bus device and write back is as APB bus device. When power on, the boot loader will be executed by copy data from external flash to internal SRAM, the system is configured and memory space is re-mapped from 0x0000-0000.

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3. Pinouts and Pin Descriptions

3.1. LQFP-80 Package


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3.2. Pin Description

Pin Number Pin Name Type

(NOTE 1)Alternate function

Description

1 TPX9 AB GPIOC19 TouchKey9 or GPIOC19 2 TPX10 AB GPIOC20 TouchKey10 or GPIOC20

3 TPX11 AB GPIOC21 TouchKey11 or GPIOC21 4 TPX12 AB GPIOC22 TouchKey12 or GPIOC22 5 TPX13 AB GPIOC23 TouchKey13 or GPIOC23

6 USB_DRV_VBUS B GPIOA4/X32KO USB_DRV_VBUS: USB Master/Slave mode Power Control. X32KO: Output 32.768KHz clock.

7 USB_VBUS_VALID B GPIOA5 USB_VBUS_VALID: USB Valid status detect.

8 USB_RES A Connect 12.1Kohm resistor to GND

9 AVDD33_USB POWER 3.3V power for USB 10 USB_DP A USB differential D plus connection11 USB_DM A USB differential D minus

connection

12 AVSS33_USB GND USB ground 13 AVDD18_USB (NOTE 2) POWER 1.8V power for USB 14 VDD33_RTC POWER 3.3V power for RTC

15 X32KI I 32.768KHz OSC IN 16 X32KO O 32.768KHz OSC OUT 17 VSS33_RTC GND RTC ground

18 TEST_MODE I Float or connect ground 19 AUD_LLIN1 A Audio Left Linein 1 20 AUD_RLIN1 A Audio Right Linein 1

21 AUD_LLIN2 A Audio Left Linein 2 22 AUD_RLIN2 A Audio Right Linein 2 23 AUD_LMICIN A Audio Left MIC IN, Internal max

Boost 40dB.

24 AUD_RMICIN A Audio Right MIC IN, Internal max Boost 40dB.

25 AVDD33_2 POWER 3.3V power for Analog. 26 AUD_LHPOUT A Left Headphone output

27 HP_VMID A Headphone VMID 28 AUD_RHPOUT A Right Headphone output

29 AVSS33_2 GND Analog ground

30 TPX_ROUT A Touchekey Sensitivity adjust

resistor

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31 TPX_COUT A Touchkey Sensitivity adjust

capacity

32 AIN0 AB GPIOA0 SAR ADC input 0 33 AIN1 AB GPIOA1 SAR ADC input 1 34 SPIMS_SCK B GPIOB4 SPI Master/Slave Serial clock.

35 SPIMS_SI B GPIOB5 SPI Master/Slave Serial data input.

36 SPIMS_SO B GPIOB6 SPI Master/Slave Serial data

output.

37 SPIMS_CSn B GPIOB7 SPI Master/Slave chip select, low

valid.

38 VSS33_IO2 GND I/O ground. 39 X26MI I 26MHz OSC Input. 40 X26MO O 26MHz OSC Output.

41 VDD33_IO2 POWER 3.3V power for I/O.

42 TPX2 AB SD_CMD /

GPIOC12 Touchkey2 or SD_CMD or GPIOC12.

43 TPX3 AB SD_CD /

GPIOC13 Touchkey3 or SD_CD or GPIO13.

44 TPX4 AB GPIOC14 Touchkey4 or GPIOC14. 45 I2S_BCLK/PCM_BCLK B I2S/PCM interface bit clock. 46 I2S_LRC/PCM_SYNC B I2S/PCM Sampling Clock.

47 I2S_DIN/PCM_DIN I I2S/PCM data input. 48 I2S_DOUT/PCM_DOUT O I2S/PCM data output. 49 SD_DAT0 B GPIOB17 SD_DAT0: SD Card data0.

50 SD_CLK B GPIOB15 SD_CLK: SD Card clock. 51 SD_CMD B GPIOB16 SD_CMD: SD Card command. 52 SD_CD B GPIOB14 SD_CD: SD Card detect.

53 I2C_SCL B GPIOA6 I2C Bus serial clock.

54 I2C_SDA B GPIOA7 I2C Bus serial data.

55 VDD33_IO3 POWER 3.3V power for I/O.

56 VSS33_IO3 GND I/O ground.

57 SPIB_SCK B SPI Boot Serial clock. 58 SPIB_SI B SPI Boot Serial data input. 59 SPIB_SO B SPI Boot Serial data out.

60 SPIB_CSn B SPI Boot chip select, low valid. 61 RESETn I System reset pin, low valid. 62 PWM0 B GPIOB0 PWM output for timer0.

63 PWM1 B GPIOB1 PWM output for timer1. 64 PWM2 B GPIOB2 PWM output for timer2.

65 UART1_TXD B GPIOA8 Data transmitter output for

UART1.

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66 UART1_RXD B GPIOA9 Data receiver input for UART1.

67 UART1_CTS B GPIOA10 Clear to send input for UART1. 68 UART1_RTS B GPIOA11 Requset to send output UART1.

69 UART2_TXD B GPIOA12 Data transmitter output for

UART2.

70 UART2_RXD B GPIOA13 Data receiver input for UART2. 71 VSS33_IO1 GND I/O ground. 72 VDD33_IO1 POWER 3.3V power for I/O.

73 DVSS18 GND Digital ground. 74 DVDD18 POWER Output 1.8V @ 250mA power. 75 AVDD33_1 POWER 3.3V power for analog.

76 TPX14 AB GPIOC0 TouchKey14 or GPIOC0 77 TPX15 AB GPIOC1 TouchKey15 or GPIOC1 78 TPX6 AB GPIOC16 TouchKey6 or GPIOC16

79 TPX7 AB GPIOC17 TouchKey7 or GPIOC17 80 TPX8 AB GPIOC18 TouchKey8 or GPIOC18

Note：

1. A = Analog B = bidirectional I = input O = output P = power G = GND.

2. AVDD18_USB is the power for USB PHY ,must be connected to DVDD18.

4. Memory Mapping

The CJC391x family always boot from external flash through high speed SPI, which move the code from external flash to internal high-speed 72KB SRAM. Thereafter, the CJC391x will re-boot from address 0x0000-0000 of the re-mapped memory space.

From To Size CJC391x

0x00000000 0x03FFFFFF 64M SPI_Boot ROM 0x04000000 0x07FFFFFF 64M Internal ROM 0x08000000 0x0BFFFFFF 64M reserved 0x0C000000 0x0FFFFFFF 64M reserved 0x10000000 0x7FFFFFFF 1792M reserved 0x80000000 0x8FFFFFFF 256M SRAM (mem) 0x90000000 0x900FFFFF 1M reserved 0x90100000 0x901FFFFF 1M reserved 0x90200000 0x902FFFFF 1M reserved 0x90300000 0x903FFFFF 1M reserved 0x90400000 0x904FFFFF 1M reserved 0x90500000 0x905FFFFF 1M reserved 0x90600000 0x906FFFFF 1M DMAC 0x90700000 0x907FFFFF 1M APU 0x90800000 0x908FFFFF 1M USB OTG

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0x90900000 0x909FFFFF 1M reserved 0x90A00000 0x90AFFFFF 1M reserved 0x90B00000 0x90BFFFFF 1M reserved 0x90C00000 0x90CFFFFF 1M AHBC 0x90D00000 0x90DFFFFF 1M AHB2APB (reg) 0x90E00000 0x90EFFFFF 1M reserved 0x90F00000 0x90FFFFFF 1M reserved 0x91000000 0x910FFFFF 1M reserved 0x91100000 0x929FFFFF 25M reserved 0x92A00000 0x92AFFFFF 1M reserved 0x92B00000 0x93FFFFFF 21M reserved

0x94000000 0x940FFFFF 1M APB SPI 0x94100000 0x941FFFFF 1M reserved 0x94200000 0x942FFFFF 1M APB UART1 0x94300000 0x943FFFFF 1M reserved 0x94400000 0x944FFFFF 1M APB SDC 0x94500000 0x945FFFFF 1M reserved 0x94600000 0x946FFFFF 1M APB UART2 0x94700000 0x947FFFFF 1M APB UART3 0x94800000 0x948FFFFF 1M APB PCU 0x94900000 0x949FFFFF 1M APB TIMER 0x94A00000 0x94AFFFFF 1M APB WDT 0x94B00000 0x94BFFFFF 1M APB RTC 0x94C00000 0x94CFFFFF 1M APB GPIO 0x94D00000 0x94DFFFFF 1M TouchKey 0x94E00000 0x94EFFFFF 1M APB I2C 0x94F00000 0x94FFFFFF 1M APB PWM 0x95000000 0x950FFFFF 1M APB INTC 0x95100000 0x951FFFFF 1M ADC 0x95200000 0x952FFFFF 1M SPI_Boot (reg) 0x95300000 0x95FFFFFF 13M reserved 0x96000000 0x9FFFFFFF 160M reserved

0xA0000000 0xAFFFFFFF 256M reserved 0xB0000000 0xB3FFFFFF 64M reserved 0xB4000000 0xB7FFFFFF 64M reserved 0xB8000000 0xBBFFFFFF 64M reserved 0xBC000000 0xBFFFFFFF 64M reserved 0xC0000000 0xFFFFFFFF 1G reserved

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5. Electrical Characteristics

5.1. Absolute Maximum Ratings

AVDD33_1 to AVSS33_2 -0.5V to 4.5V AVDD33_2 to AVSS33_2 -0.5V to 4.5V VDD33_RTC to AVSS33_2 -0.5V to 4.5V AVDD33_USB to AVSS33_USB -0.5V to 4.5V AVDD18_USB to AVSS33_USB -0.5V to 2.3V VDD33_IO1 to VSS33_IO1 -0.5V to 4.5V VDD33_IO2 to VSS33_IO2 -0.5V to 4.5V

Supply voltage range

VDD33_IO3 to VSS33_IO3 -0.5V to 4.5V I/O Input Voltage VIN -0.5V to 5.0V Operating temperature, TA -20 to 70 Storage temperature, Tstg -65 to 150

5.2. Recommended Operating Conditions

Symbol Parameter Conditions Min Typ. Max Unit

Main Crystal System crystal 26 MHz

RTC Crystal RTC crystal 32.768 KHz

Fcore Core frequency Default 67.7 98.3 122.8 MHz

Fhclk AHB frequency Default 33.86 49.512 61.4 MHz

Fpclk APB frequency Default 16.9 24.576 30.7 MHz

Fapu APU frequency Default 11.2896 12.288

/ 12

MHz

AVDD33_1 Power for Analog 3.00 3.30 3.60 V

AVDD33_2 Power for Analog 3.00 3.30 3.60 V

AVDD33_USB Power for USB OTG

PHY

3.00 3.30 3.60 V

VDD33_RTC Power for RTC 3.00 3.30 3.60 V

AVDD18_USB USB PHY VDD External support

1.8V power

1.62 1.80 1.98 V

DVDD18 Internal 1.8V LDO

output

Analog Power >=

3.0V

1.70 1.80 1.90

VDD33_IO1/2/3 IO VDD supply 3.00 3.30 3.60 V

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5.3. Current Characteristics

5.3.1. Normal mode supply current Characteristics

AVDD33_1 = 3.3V, AVDD33_2 = 3.3V, AVDD33_USB = 3.3V, AVDD33_RTC = 3.3V, AVDD18_USB

connect with DVDD18, VDD33_IO1 = 3.3V, VDD33_IO2 = 3.3V, VDD33_IO3 = 3.3V, Core Frequency

= 98.3MHz, AHB Clock = 49.15MHz, APB Clock = 24.576MHz, APU Clock = 12.288MHz, All module is

power on, TA = 25(unless otherwise noted).

Symbol Parameter Test Conditions

Min Typ. Max Unit

IAVDD33_1 Current of AVDD33_1 84.6 mA


IAVDD33_RTC Current of

AVDD33_RTC

0.3 mA

IAVDD33_USB Current of

AVDD33_USB

USB in Full 3.02 mA


AVDD18_USB

Speed mode. 3.25 mA

IVDD33_IO1/2/3 Current of

VDD33_IO1/2/3

GPIOA/B/C

can not connect

anything

1.97 mA

ITC Total Current 108.77 mA

PD Power dissipation 359 mW

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5.3.2. Sleep mode supply current Characteristics


connect with DVDD18, VDD33_IO1 = 3.3V, VDD33_IO2 = 3.3V, VDD33_IO3 = 3.3V, All module is

power down except RTC module, TA = 25(unless otherwise noted).


Min Typ. Max Unit

IAVDD33_1 Current of AVDD33_1 0 mA


IAVDD33_RTC Current of

AVDD33_RTC

0.3 mA


AVDD33_USB

0 mA


AVDD18_USB

USB in Full

Speed mode.

0 mA

IVDD33_IO1/2/3 Current of

VDD33_IO1/2/3

GPIOA/B/C

can not connect

anything

0.1 mA

ITC Total Current 0.98 mA

PD Power dissipation 3.23 mW

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5.4. GPIO Characteristics


connect with DVDD18, VDD33_IO1 = 3.3V, VDD33_IO2 = 3.3V, VDD33_IO3 = 3.3V, Core Frequency =

98.3MHz, AHB Clock = 49.15MHz, APB Clock = 24.576MHz, APU Clock = 12.288MHz, All module is

power on, TA = 25(unless otherwise noted).


Min Typ. Max Unit

VIL Input Low Voltage 0.3*VDD33_IO V

VIH Input High Voltage 0.7*VDD33_IO 5 (Note1) V

IOL = 4 mA 0 0.2 V VOL Output Low Voltage

IOL = 12 mA 0 0.2 V

IOL = 4 mA VDD33_IO-0.2 VDD33_IO VDD33_IO+0.2 V VOH Output High Voltage

IOL = 12 mA VDD33_IO-0.2 VDD33_IO VDD33_IO+0.2 V

IOL

Low-Level Sink Current,

GPIOA/B/C

4 mA

IOH

High-Level Output Current,

GPIOA/B/C

4 mA

Note1: if the GPIO input voltage is greater than 4V, please connect a 100ohm resistor or more than.

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5.5. Audio Characteristics

5.5.1. Line Input to ADC Characteristics




power on, TA = 25. ADC Slave Mode, 24bit I2S format, fs = 48kHz, XTI/MCLK = 256fs, unless

otherwise stated(unless otherwise noted).

PARAMETER SYMBOL TEST CONDITIONS

MIN TYP MAX UNIT

Line Input to ADC Input Signal Level (0dB) VINLINE 0.9AVDD VPP

A-weighted, 0dB gain

@ fs = 48kHz

98 Signal to Noise Ratio

SNR

A-weighted, 0dB gain

@ fs = 96kHz

98

dB

Dynamic Range DR A-weighted, -60dB full

scale input

98 dB

Total Harmonic Distortion THD+N -1dB input, 0dB gain -83 dB Power Supply Rejection Ratio

PSRR 1kHz, 3dBV -50 dB

Interchannel isolation Crosstalk 1KHz -103 dB 0dB gain 20k 30k Input Resistance RINLINE

12dB gain 10k 15k Ω

Input Capacitance CINLINE 10 pF

5.5.2. Microphone Input to ADC Characteristics




power on, TA = 25. ADC Slave Mode, 24bit I2S format, fs = 48kHz, XTI/MCLK = 256fs, MICIN

couple 1uF capacity, unless otherwise stated(unless otherwise noted).

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT

Microphone Input to ADC

Microphone Boost VBB 20 40 dB

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Input Signal Level (0dB) VINLINE 0.9AVDD VPP

Microphone to Headphone AOUT MICIN=0dBV, VB=40dB, In sidetone mode

B -6.98 dBV

Signal to Noise Ratio

SNR A-weighted, 0dB gain @ fs = 48kHz

99 dB

Dynamic Range DR A-weighted, -60dB full scale input

91 dB

Total Harmonic Distortion THD+N 0dB input, 0dB gain -83 dB Input Resistance RINLINE 10k Ω Input Capacitance CINLINE 10 pF

5.5.3. DAC to LINEOUT Characteristics




power on, TA = 25 . ADC Slave Mode, 24bit I2S format, fs = 48kHz, APU_CLK = 256fs,

HeadPhoneOut couple 220uF capacity, HPVMID connect 1uF to ground, RLoad = 10K, unless otherwise

stated(unless otherwise noted).


MIN TYP MAX UNIT

LINEOUT From DAC Playback Only (Load = 10kΩ. 50pF) A-weighted, @ fs = 48kHz

102 Signal to Noise Ratio

SNR

A-weighted @ fs = 96kHz

102

dB


102 dB

1kHz, 0dBfs -81 Total Harmonic Distortion THD+N 1kHz, -3dBfs -84

dB

Interchannel isolation Crosstalk 1KHz, 0dBfs -110 dB

Power Supply Rejection Ratio PSRR 1kHz, 3dBV 43 dB

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5.5.4. DAC to HeadPhoneOut(No Capacitor) Characteristics




power on, TA = 25. Slave Mode, fs = 48kHz, APU_CLK = 256fs, HeadPhoneOut no couple capacitor,

HPVMID connnect to ground, RLoad = 16Ohm, unless otherwise stated(unless otherwise noted).


MIN TYP MAX UNIT

Stereo Headphone Output From DAC (Load = 16Ohm, no capacitor) Signal to Noise Ratio

SNR A-weighted, @ fs = 48kHz

98.5 dB


98.5 dB

Total Harmonic Distortion THD+N 1kHz, -3dBfs -83 dB Interchannel isolation Crosstalk 1KHz, 0dBfs -99 dB

Power Supply Rejection Ratio PSRR 1kHz 43 dB

5.5.5. DAC to HeadPhoneOut(Couple Capacitor) Characteristics




power on, TA = 25. Slave Mode, fs = 48kHz, APU_CLK = 256fs, HeadPhoneOut couple 220uF

capacitor, HPVMID connnect 1uF to ground, RLoad = 16Ohm, unless otherwise stated(unless otherwise

noted).


MIN TYP MAX UNIT

Stereo Headphone Output From DAC (Load = 16Ohm, Couple 220uF capacitor) Signal to Noise Ratio


96 dB


96 dB

Total Harmonic Distortion THD+N 1kHz, -3dBfs -85 dB

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Interchannel isolation Crosstalk 1KHz, 0dBfs -99 dB

Power Supply Rejection Ratio PSRR 1kHz 43 dB

5.5.6. LINEIN to HEADPHONE OUT Characteristics




power on, TA = 25. Slave Mode, fs = 48kHz, APU_CLK = 256fs, HeadPhoneOut couple 220uF capacity,

HPVMID connnect 1uF to ground, RLoad = 16Ohm, unless otherwise stated(unless otherwise noted).


MIN TYP MAX UNIT

LINEIN to ADC and HEADPHONEOUT From DAC Signal to Noise Ratio


96 dB


96 dB

Total Harmonic Distortion THD+N 1kHz, -3dBfs -84 dB

5.6. SARADC characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITOperation voltage AVDD33_2 3.0 3.3 3.6 V Operation Current IDD 2.38 mA Reference voltage VREF AVDD33_2 V Resolution Res 8 9 10 bit Conversion time TC 1 2.5 us Sampling rate SR 400 KHz Integral Non-Linearity Error INL ±2 LSB differential Non-Linearity Error DNL ±1 LSB

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5.7. PLL characteristics

5.7.1. System PLL

SYS_PLL (MHz)

CPU CORE(MHz)

HCLK_DIV AHB (MHz)

PCLK_DIV APB (MHz)

APU Codec (MHz)

Description

147.456 73.728 2 36.864 2 18.432 12.288 fs=48KHz

172.032 86.016 2 43.008 2 21.504 12.288 fs=48KHz

196.608 98.304 2 49.152 2 24.576 12.288 Default,

fs=48KHz

221.184 110.592 2 55.296 2 27.648 12.288 fs=48KHz

245.76 122.88 2 61.44 2 30.72 12.288 fs=48KHz

135.4752 67.7376 2 33.8688 2 16.9344 11.2896 fs=44.1KHz

146.7648 73.3824 2 36.6912 2 18.3456 11.2896 fs=44.1KHz

169.344 84.672 2 42.336 2 21.168 11.2896 fs=44.1KHz

203.2128 101.6064 2 50.8032 2 25.4016 11.2896 fs=44.1KHz

225.792 112.896 2 56.448 2 28.224 11.2896 fs=44.1KHz

5.7.2. USB PLL

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

fUSB_PLL USB PLL Clock 191.99900191.99925192.00015 MHzfUSB_PHY USB PHY Clock fUSB_PLL /16 11.99993 11.99995 12.00001 MHz

Clock jitter 4 ppmIUSB_PLL USB PLL Current AVDD33_2 =

3.3V 7.27 mA

5.8. Touch Key Controller Characteristics

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITOperation voltage AVDD33_2 3.0 3.3 3.6 V Operation Current IDD 60 uA Resolution RESO 7 9 14 bit Channels 0 23 Reference voltage VTH 1/3AVDD 5/6AVDD Sampling rate FCTS 1/8 APB 1/3 APB APB Hz Extern charging capacitance

Cmod 4.7

nF

Extern discharge resister

Rb 2.2

kΩ

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6. Typical Application Instruction

6.1. Specified application scenario description

Mp3/Bluetooth A2DP decoding => internal audio DAC => DAC out In this scenario, CJC391x act as bluetooth data decoder(if data come from bluetooth), MP3 decoder and audio processor. if the mp3 source is come from Bluetooth, processor will decode bluetooth channel protocol and mp3 data format. the decoder result, mp3 data, will transfer to audio DAC, then outputs analog audio signal. If in USB/SD card mode, data is input to system through USB interface or SD card interface, the decoded mp3 data is processed as the same as Bluetooth mode.


N9 Core

mp3/Bluetooth A2DP AO_OUT_L

I2S/PCM

DAC

ADC

UART

PCM

UART

BlueCore AO_OUT_R

MICP

MICN

Figure 1. CJC391x 1st application scenario data path diagram

Bluetooth IC <===> internal audio DAC/ADC In this scenario, CJC391x is work with mobile phone as a speaker and microphone. The data path in this scenario is bi-direction through PCM interface which is combined with IIS module. The received voice is send to CJC391x by bluecore chip through PCM interface and DAC out to listener, the speaker voice is send to CJC391x through microphone port, and on-chip APU transfers it to digital signal and transmit through PCM interface and bluecore chip to mobile phone.

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N9 Core

AO_OUT_L

I2S/PCM

DAC

ADC

UART

PCM

UART

BlueCoreAO_OUT_R

MICP

MICN

Figure 2. CJC391x 2nd application scenario data path diagram

External voice source => internal switch => audio analog out In this scenario, N9 core acts as a internal switch, it receive the voice from microphone input , transfer voice signal to digital and do some audio enhancement on the signal and playback the voice through internal DAC.

N9 Core

AO_OUT_L

I2S/PCM

DAC

ADC

UART

PCM

UART

BlueCoreAO_OUT_R

MICP

MICN

Figure 3. CJC391x 3rd application scenario data path diagram

External voice source => internal DAC (IIS) In this scenario, CJC391x acts as a DAC chip to playback the external digital voice source. It get external voice source through IIS interface.

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N9 Core

AO_OUT_L

I2S/PCM

DAC

ADC

UART AO_OUT_R

MICP

MICN I2S Master

Figure 4. CJC391x 4th application scenario data path diagram

Mp3/Bluetooth A2DP decoding => external audio DAC (IIS) In this scenario, CJC391x acts as a Bluetooth signal switch, it receive the bluecore chip signal through UART interface, transfer the data format to IIS interface and send to external DAC. In this scenario, N9 core implement the data format transfer function, it transfer voice signal from UART format to PCM/IIS format.

N9 Core

mp3/Bluetooth A2DP

AO_OUT_L

I2S/PCM

DAC

ADC

UART

PCM

UART

BlueCore AO_OUT_R

MICP

MICN I2S DAC

Figure 5. CJC391x 5th application scenario data path diagram

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7. Application Circuit

R910K

C210.1uFS1

GND

3.3V_IN

GND

Out 1.8V@250mA Power

1.8V_OUT 3.3V_IN

C1 1uFC2 1uFC3 1uFC4 1uFC5 0.1uFC7 0.1uF

3.3V_IN

LLIN1

LLIN2RLIN1

RLIN2

C9 0R/4.7uF

C8 /220uF0RC10 R/220uF0

++

Note1HPGND

R3 12.1KGND

R4 2.2K C64.7nF

GND

R1 4.7K

R2 4.7K3.3V_IN

Note2

RES

ETn

C13100pF

MIC1

R5100R

C1110uF

C120.1uF

GND

R6

LMICIN

LMICINRMICIN

Note4

Not

e5

+

3.3V_INC230.1uFR

18

0R

SPIB_CSNSPIB_SI

SPIB_SOSPIB_SCK

GND

GND

3.3V_IN

R22

NCN

ote3

CS1

SO2

WP3

GND4 SI 5SCK 6HOLD 7VCC 8U2

SPI_FLASH

Note616/32OhmHEADPHONE

SPIB

_CSN

SPIB

_SO

SPIB

_SI

SPIB

_SC

K

3.3V_IN

C16100pF

MIC2

R7100R

C1410uF

C150.1uF

GND

R8

RMICINNot

e5

+

3.3V_IN

C2422uF

C270.1uF

C2522uF

C280.1uF

C290.1uF

C300.1uF

C310.1uF

C320.1uF

C330.1uF

C340.1uF

GND

1.8V_OUT

C2622uF

C350.1uF

GND

C360.1uF

Note7

X26

MI

39

X26

MO

40

USB_DRV_VBUS/X32KO/GPIOA46

USB_VBUS_VALID/GPIOA57

USB_RES8

USB_DP10

USB_DM11

X32

KI

15

X32

KO

16

AV

DD

33_U

SB9

AV

DD

18_U

SB13

VD

D33

_RTC

14A

VD

D33

_225

VD

D33

_IO

241

VD

D33

_IO

355

VD

D33

_IO

172

DV

DD

1874

AV

DD

33_1

75

AV

SS33

_USB

12

VSS

33_R

TC17

AV

SS33

_229

VSS

33_I

O2

38

VSS

33_I

O3

56

VSS

33_I

O1

71

DV

SS18

73

TEST

_MO

DE

18

PWM

0/G

PIO

B0

62PW

M1/

GPI

OB

163

PWM

2/G

PIO

B2

64

RES

ETn

61

AUD_LLIN119

AUD_RLIN120

AUD_LLIN221

AUD_RLIN222

AUD_LMICIN23

AUD_RMICIN24

AUD_LHPOUT26

HP_VMID27 AUD_RHPOUT28

I2S_BCLK/PCM_BCLK45

I2S_LRC/PCM_SYNC46

I2S_DIN/PCM_DIN47

I2S_DOUT/PCM_DOUT48

TPX_ROUT 30

TPX_COUT 31

TPX2/GPIOC12 42

TPX3/GPIOC13 43

TPX4/GPIOC14 44

TPX6/GPIOC16 78

TPX7/GPIOC17 79

TPX8/GPIOC18 80

TPX9/GPIOC19 1

TPX10/GPIOC20 2

TPX11/GPIOC21 3

TPX12/GPIOC22 4

TPX13/GPIOC23 5

SD1_DAT0/GPIOB17 49

SD1_CLK/GPIOB15 50

SD1_CMD/GPIOB16 51

SD1_CD/GPIOB14 52

I2C_SDA/GPIOA754 I2C_SCL/GPIOA653

SPIB

_SC

K57

SPIB

_SI

58

SPIB

_SO

59

SPIB

_CSN

60UART1_TXD/GPIOA865

UART1_RXD/GPIOA966

UART1_CTS/GPIOA1067

UART1_RTS/GPIOA1168

UART2_TXD/GPIOA1269

UART2_RXD/GPIOA1370

SPIMS_SCK/GPIOB4 34SPIMS_SI/GPIOB5 35SPMS_SO/GPIOB6 36SPIMS_CSN/GPIOB7 37

AIN0/GPIOA032 AIN1/GPIOA133

CJC3912

TPX14/GPIOC0 76

TPX15/GPIOC1 77

U1CJC3912

Y2

32.768KHzY1

26MR10 10M

C1915pF

C2015pF

GND

C1815pF

C1715pF

GND

R23 10MNote8

Note1: if C8, C9, C10 is 0R, then HPGND must be float; else if C8 = 220uF, C10 = 220uF, C9 = 4.7uF, then HPGND must be connect to the system ground. Note2: if I2C_SCL/GPIOA6 and I2C_SDA/GPIOA7 select as I2C bus, then must be pull-up a resistor. Note3: WP = 1, SPI Flash can be writed; WP = 0, SPI Flash write protected. Note4: AVDD18_USB must connect with DVDD18 when use the USB, and DVDD18 can output 1.8V@250mA power supply designed for external using. Note5: The R6 and R8 Value according to the MIC model to adjust, make the positive electrode of MIC DC voltage is 2V. Note6: R4 and C6 is used for adjust touchkey sensitivity, default value R4=2.2K, C6=4.7nF. Note7: In the vicinity of each power supply pins placed at least a 0.1uF capacitance, in order to better

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CJC3912 performance, can be put a few 22uF big capacitance. Note8: 32.768KHz Crystal both ends must be connect 10M resistor

8. Package (LQFP80)


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9. Part Numbering


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10. Revision History Edition Author Date Description

V1.0 YT 2012.11.16 first draft of CJC391x Datasheet v1.0

V1.0.1 YT 2012.11.19 Update RTC function description

Update the GPIOS in the chapter of Device Overview

V1.0.2 YT 2013.08.20 Update the chapter of Pinouts and Pin Descriptions

Update the chapter of Package Chracteristics

V1.1 PIPI 2013.10.08 Update File Frame, and add some system diagram and

application circuit.

V1.2 PIPI 2013.12.16 Update File Format

V1.3 PIPI 2014.01.05 Change application circuit and note.

11. NOTICES

The information contained herein could be changed without notice owing to product and /or technical

improvements. Please make sure before using the product that the information you are referring to is

up-to-date.

No responsibility is assumed by us for any consequence resulting from any wrong orimproper operation,

etc.of the product.

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