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CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

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CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng
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Page 1: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

CSE 242A Integrated Circuit Layout

Automation

Lecture 5: Placement

Winter 2009

Chung-Kuan Cheng

Page 2: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Placement Formulation

ij

Obj: min (| | | |)

min clock cycle

min routing congestion

Multipin net model on wire length

ij i j i jC x x y y

½ perimeter of min bounding box

Single trunk (v or h)

Spanning tree

Steiner tree

Page 3: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Layout Area

Rectilinear Area

Block Shapes

Single row height: width=1~2 or even hunderds

Multiple rows

Donuts

Page 4: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Formulation: Constraints

Groups: A set of cells to be placed within X & Y distance

Regions: If a cell is attached to a region, it needs to be placed within the specified area.

Sites: Each slot has a type. Each cell is specified by types on its area. The types have to be matched for a correct placement.

Page 5: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

IO Placement

Page 6: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Placement Formulation

Quadratic Assignment (NP Complete)

i j

Cij

i

j

Comps

Slots

Cij

Linear Assignment

Page 7: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Placement Methods

Analytical Method Constructive Method Iterative Method

Page 8: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Analytical Method: QPlace (RAMP)

Resistive Analog Module Placement

i

ij

ij

x

f

c

a b

c

d

a b

c

d

1/

i

ij

ij ij

v

i

v r

Page 9: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Analytical Method (Obj)2 2

1 1

1

ij

11 12

21 22

Obj: min ( )

, 0

... fixed IOs or comps

...

B=[b ] , , , ,

[ ]

Tij ij ij i j

ij ij

T

ij ij ii ijj

c x c x x X BX

X b I X

where

x

X

b c i j b c i j

B B

B B

Page 10: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Analytical Method: Obj

11 12 11 2

21 22 2

1 11 1 1 12 2 2 22 2

21 1 22 2

( ) [ ]

2

( ) 2 2

T T

T T T

B B Xf x X BX X X

B B X

X B X X B X X B X

f x B X B X

Page 11: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Analytical Method

Constraints Sum xi = c1

Sum xi2= c2

Sum xi3= c3

Sum xin= cn

Page 12: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Repulsive Force

i

j

If i & j are not connected

2| |ij

ijij

rf

r

By density

Page 13: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Constructive Method

Input: Seeds X,

Unplaced set V-X

Pick a cell in in V-X with strongest connection to X

Place i at a location so that partial cost is minimized

{ }

Iterate until V=X

X X i

Adv: Fast, Simple, Flexible

Dis: Quality of the Results

Page 14: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Iterative Improvement

Given an initial placement A. Find the best pair to swap B. Find the best sequence to swap

A

D

BC

A

B

C

D

Page 15: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

iComponent i has a set of nets N

Each net has two extreme points

Length of | | | | | |i

e e

i e i e e ee N

a b

i x a x b b a

Iterative Method

Target zone of each component i:Count from left. Each ae or be is counted once,Target zone = Region between |N| and |N|+1.

Page 16: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Simulated Annealing0

0

T

T

( )

, initialT()

I=1

while (I Imax)

I+=1, N=0, j=0

whindow size(I)

while (N Nmax)

j+=1, N+=1

if(j==update_limit)

j=0

if( < )

raiseT(T)else if( )

lowerT(T)

Y=perturb(X)

C=C(Y)-C(X)

if accept( C,T)

X=Y

SA x

x x T

Page 17: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

SA Cost Function0

0

R 0

0max

max

max

(

| ( ) ( ) |

| ( ) ( ) |

(i) choice of S.T.

0.25L 1.4

1( ) (1.4 1.15 )

1

(ii) Choice of S.T.

0.03

1( ) (5 4 )

1

(iii) #bins/#cell

R

ij ij ijij

cb

R dr

R

TR

d

d

TR R

C W P P

W C x y

P W b W b

P L r L r

P L

IP I L

I

L L

L

IP I L

I

s=1.5

allowing 33% probability of generating a single cell move

Page 18: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Window Size, Temperature, & acceptance ratio

I

III III

4/3

max

4/3max

500 #moves=4000N

N 500 #moves=4000N( )

500160

Nmax{25 ,25 ( ) }

500

(1 ) (K=40)T

N

I

N N N

T TK

Page 19: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Local Placement

a b c d

Choose k cells

Find the opt sequence of the k cells

Find a larger set of cellsDerive the opt matching (Ignore the relation between the k cells)

Page 20: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Performance Driven Placement

Replication

a

x b

a

x

x

bGate Sizing, Buffer Insertion

Page 21: CSE 242A Integrated Circuit Layout Automation Lecture 5: Placement Winter 2009 Chung-Kuan Cheng.

Pin Swapping

a

b

c

a c b


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