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MEMORYMEMORY
DATAPATHDATAPATH
CONTROLCONTROL
INPU
T -
OU
TPU
TIN
PU
T -
OU
TPU
T
RAM, ROM, Registers, …RAM, ROM, Registers, …
Finite state machine: Finite state machine: PLA, Counters, Flip-PLA, Counters, Flip-flops, Latches, …flops, Latches, …
Interconnect:Interconnect:Switches, Arbiters, Switches, Arbiters, Bus, …Bus, … Arithmetic Unit:Arithmetic Unit:
Adder, Multiplier, Shifter, Adder, Multiplier, Shifter, Comparator, …Comparator, …
Bu
ild
ing
Blo
cks f
or
Dig
ital A
rch
itectu
res
Bu
ild
ing
Blo
cks f
or
Dig
ital A
rch
itectu
res
CPU
A Generic Digital Processor
Bit-Sliced Design
Bit 3Bit 3
Bit 2Bit 2
Bit 1Bit 1
Bit 0Bit 0
ControlControl
Tile identical processing elementsTile identical processing elements
Regis
ter
Regis
ter
Adder
Adder
Shifte
rShifte
r
Mult
iple
xer
Mult
iple
xer
DA
TA
-IN
DA
TA
-IN
DA
TA
-OU
TD
ATA
-OU
T
Comparators
Compares Two binary words and indicate if they Compares Two binary words and indicate if they are equalare equal
AA ComparatorComparator A=BA=B
BB A>B A>B A<B A<B
AA
BB FF
Advanced Comparators:Advanced Comparators:
1-bit Comparator: XOR gate, the Output is 1 if A 1-bit Comparator: XOR gate, the Output is 1 if A B B
AA
ComparatorComparator BB
A=BA=B
Iterative ComparatorEQI X Y EQO
0 X X 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
XX YY
EQIEQI
EQOEQO
1 bit comparator:1 bit comparator:
Multibit Iterative Comparator
EQ0 =1EQ0 =1
X0X0 Y0Y0 X1X1 Y1Y1 X(N-1)X(N-1) Y(N-1)Y(N-1)
EQNEQN XX YY
EQIEQI EQOEQO EQ1EQ1
XX YY
EQIEQI EQOEQO EQ1EQ1
XX YY
EQIEQI EQOEQO
EQ1(N-1)EQ1(N-1)
Iterative Comparator: cascaded 1 bit Iterative Comparator: cascaded 1 bit comparatorscomparators
MSI Comparator: 74x85
B0B0
A1A1
B1B1
A2A2
B2B2
A3A3
A0A0
B3B3
74x8574x85
A<BINA<BIN
A=BINA=BIN
A>BINA>BIN
A<BOUTA<BOUT
A=B OUTA=B OUT
A>BOUTA>BOUT
4 bit comparator4 bit comparator
(A<B)+(A=B).(A<B IN)(A<B)+(A=B).(A<B IN)
(A>B)+(A=B).(A>B IN)(A>B)+(A=B).(A>B IN)(A=B).(A=B IN)(A=B).(A=B IN)
3 Cascading inputs3 Cascading inputs
Cascading Cascading inputs initial inputs initial values:values:
(A=B IN) = 1(A=B IN) = 1
(A>B IN) = 0(A>B IN) = 0
(A<B IN) = 0(A<B IN) = 0
8 bit Comparator
B0B0
A1A1
B1B1
A2A2
B2B2
A3A3
A0A0
B3B3
74x8574x85
A<BINA<BIN
A=BINA=BIN
A>BINA>BIN
A<BOUTA<BOUT
A=B OUTA=B OUT
A>BOUTA>BOUT
B0B0
A1A1
B1B1
A2A2
B2B2
A3A3
A0A0
B3B3
74x8574x85
A<BINA<BIN
A=BINA=BIN
A>BINA>BIN
A<BOUTA<BOUT
A=B OUTA=B OUT
A>BOUTA>BOUT
B0B0
A1A1
B1B1
A2A2
B2B2
A3A3
A0A0
B3B3
B4B4
A5A5
B5B5
A6A6
B6B6
A7A7
A4A4
B7B7
+5V+5V
A<BA<B
A=B A=B
A>BA>B
Most Significant bitsMost Significant bitsLeast Significant bitsLeast Significant bits
Half AdderX Y SUM COUT
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
SUM = X SUM = X Y Y
CCOUTOUT = = X.YX.Y
YY
XXSS
CCOUTOUT
Full Adder1-bit-wide adder, produces sum and carry 1-bit-wide adder, produces sum and carry outputsoutputs
X Y Cin S Cout
0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1
S = S = X’Y’CX’Y’CININ+X’YC+X’YCININ’+XY’C’+XY’CININ’+XYC’+XYCIN IN
S = X S = X Y Y C CININ
CCOUTOUT = XY + XC = XY + XCIN IN + YC+ YCININ
Ripple Adder
Speed limited by carry chain: Speed limited by carry chain: ttadderadder (n-1)t (n-1)tcarry carry + t+ tsumsum
Goal:Goal: Make the fastest possible carry path circuit Make the fastest possible carry path circuit
Faster adders eliminate or limit carry chainFaster adders eliminate or limit carry chain2-level AND-OR logic 2-level AND-OR logic 2 2nn product terms product terms3 or 4 levels of logic, 3 or 4 levels of logic, carry lookaheadcarry lookahead
Cascade n Full Adders to get n-bit binary AdderCascade n Full Adders to get n-bit binary Adder
Subtraction is the same as addition of the two’s complement.Subtraction is the same as addition of the two’s complement.
The two’s complement is the bit-by-bit complement plus 1.The two’s complement is the bit-by-bit complement plus 1.
X – Y = X + Y’ + 1X – Y = X + Y’ + 1
Complement Complement YY inputs to adder, set inputs to adder, set CCinin to to 11..
For a borrow, set For a borrow, set CCinin to to 00.. XX Y’Y’
11
Subtraction
M = 0: Ripple AdderM = 0: Ripple Adder
M = 1: Ripple M = 1: Ripple SubtractorSubtractor
X0X0 Y0Y0
X1X1 Y1Y1
X(n-X(n-1)1)
Y(n-1)Y(n-1)
COUT/COUT/BOUTBOUT
S0/D0S0/D0 S(n-1) / D(n-S(n-1) / D(n-1)1)
S1/D1S1/D1
XX YY
COUTCOUT
CINCIN SS
XX YY
COUTCOUT
CINCIN SS
XX YY
COUTCOUT
CINCIN SS
MM
Adder/Subtractor CircuitAdder/Subtractor Circuit
CLL: Carry Lookahead CLL: Carry Lookahead
LogicLogic
XX YY CLLCLL
SS CLLCLL
XX YY
SS
S0S0 S1S1S(n-1)S(n-1)
X0X0 Y0Y0 X1X1 Y1Y1 X(n-X(n-1)1)
Y(n-1)Y(n-1) I(n-1)I(n-1) I1I1 I0I0
Carry Lookahead Adder Carry Lookahead Adder UnitsUnits
CLLCLL
XX YY
SS
COUTCOUT
Carry Lookahead AdderCarry Lookahead Adder
SS YiYi
XiXi
CiCi
SS
Ci+1Ci+1
YiYi
XiXi
Xi-1Xi-1
X0X0Yi-1Yi-1
Y0Y0C0C0
CiCiCarryCarryLookaheadLookaheadLogicLogic
hsihsi
AdderAdder
Full Adder vs. Carry Lookahead Adder
We need to provide an expression for the We need to provide an expression for the ccii in the CLL Unit in the CLL Unit
When does the Full adder produce carry?When does the Full adder produce carry?Answer:Answer:
If both XIf both Xii andand Y Yii equal 1 (carry is equal 1 (carry is generatedgenerated) )
OR..OR..
If If CCii=1=1 and either X and either Xii oror Y Yii equal 1 (carry is equal 1 (carry is propagatedpropagated))
CCi+1i+1= (X= (Xii.Y.Yii) + (X) + (Xii+Y+Yii).C).Cii {Compare to: C {Compare to: COUTOUT=XY + XC=XY + XCIN IN + + YCYCININ}}
CCi+1 i+1 = = ggi i + + ppii..CCiiLet Let ggii = X = Xii.Y.Yii
ppii = X= Xii + Y + Yii
GenerateGenerate
PropagatePropagate
Carry Lookahead Logic
CC1 1 = g= g0 0 + p+ p00.C.C00
CC2 2 =g=g1 1 + p+ p11.C.C11 = g = g1 1 + p+ p11gg0 0 + p+ p11.p.p00.C.C00
CC33 = g = g2 2 + p+ p22.C.C22 = g = g2 2 + p+ p22.g.g1 1 + p+ p22.p.p11.g.g0 0 + p+ p22.p.p11.p.p00.C.C00
CC44 = g = g3 3 + p+ p33.C.C33 = g = g3 3 + p+ p33.g.g2 2 + p+ p33.p.p22.g.g1 1 + p+ p33.p.p22.p.p11.g.g0 0 + p+ p22.p.p11.p.p00.C.C00
CC55 = = …………………………………………………………………………………………………………………………………………………………………………………………
CCi+1 i+1 = g= gi i + p+ pii.C.Cii ggi i = X= Xi i . Y. Yii ppi i = X= Xi i + Y+ Yii
XX 00,Y,Y 00 XX 11,Y,Y 11 XXN-1N-1,Y,Y N-1N-1......
CC i,0i,0 PP 00 CCi,1i,1 PP 11 CC i,N-1i,N-1 PPN-1N-1
......
Alm
ost
Alm
ost
th
e s
am
e a
mou
nt
of
dela
y t
he s
am
e a
mou
nt
of
dela
yCarry Lookahead LogicCarry Lookahead Logic
AA00BB00AA11
S1S1S2S2
BB11AA22BB22
CC0 0 S0S0
AA33
74x28374x283
S3S3
CC44
BB33
Uses Carry Lookahead Uses Carry Lookahead internallyinternally
74x283 4-bit Adder74x283 4-bit Adder
ALUALU performs performs ArithmeticArithmetic and and LogicalLogical Functions Functions A, B: 4 bit inputsA, B: 4 bit inputsS3, S2, S1, S0: Function selectS3, S2, S1, S0: Function selectM = 0: Arithmetic operations: + = Plus, – = MinusM = 0: Arithmetic operations: + = Plus, – = MinusM = 1: Logical operations: + = OR, . = ANDM = 1: Logical operations: + = OR, . = AND
S1S1
S2S2
S3S3
F1F1
F2F2
MM
CINCIN
A0A0
S0 S0
F0F0
B0B0
74x18174x181
F3F3
COUTCOUT
A1A1
B1B1
A2A2
B2B2
A3A3
B3B3
A=BA=B
PP
GG
Inputs Functions
S3 S2 S1 S0 M=0 (arithmetic)
M=1 (logic)
0 0 0 0 A – 1 + CIN A’
0 1 1 0 A – B – 1 + CIN A XOR B’
1 0 0 1 A + B + CIN A XOR B
1 0 1 1 (A OR B) + CIN A + B
1 1 0 0 A + A + CIN 0000
1 1 1 1 A + CIN A
MSI Arithmetic Logic Units (ALU )