CSE140: Design of Sequential Logic · 2017-08-29 · Sources: TSR, Katz, Boriello & Vahid...

Sources: TSR, Katz, Boriello & Vahid

CSE140: Design of Sequential Logic

Instructor: Mohsen Imani

1


Flip Flops

2


Counter

3


Up counter

4


Up counter

5


FSM with JK-Flip Flop

6


State Table

7


State Table

8


Circuit Minimization

9


Circuit

10


Timing Constraints in Sequential Designs

11


• Our seemingly logically correct design can go wrong –signals don’t travel in zero time

• We next look at timing constraints for combinational andsequential logic.

Combinational

CLK

Timing Constraints in Sequential Circuit Designs


Combinational Logic Timing

13

I. Min delay of a gate, also called contamination delay: tcd

Minimum time from when an input changes until the output starts to change

II. Max delay of a gate, also called propagation delay: tpd

Maximum time from when an input changes until the output is guaranteed to reachits final value (i.e., stop changing)


Combinational Logic: Output Timing Constraints

14

A

B

C

D

Y

Which path in the above circuit determines the contaminationdelay of the circuit (assuming the delay of all the gates is thesame)?

A. Blue path

B. Red path

C. Both

D. Neither


Combinational Logic: Output Timing Constraints

15

A

B

C

D

Y

Which path in the above circuit determines the propagationdelay of the circuit (assuming the delay of all the gates is thesame)?

A. Blue path

B. Red path

C. Both

D. Neither


D-FF Input Constraints: Setup and Hold Times

16

CLK

tsetup

D

thold

ta

I. Setup time: tsetup

Time before the clock edge that data must be stable (i.e. not change)

II. Hold time: thold

Time after the clock edge that data must be stable

Aperture time: ta

Time around clock edge that data must be stable (ta = tsetup + thold)

DQ

Q’

R

SD

C

D latch

Q

R

SD

C

D latch

Q


Output Timing Constraints

I. Min delay of FF, also called contamination delay or min CLK to Q delay: tccq

Time after clock edge that Q might be unstable (i.e., starts changing)

II. Max delay of FF, also called propagation delay or maximum CLK to Q delay: tpcq

Time after clock edge that the output Q is guaranteed to be stable (i.e. stopschanging)

CLK

tccqtpcq

Q

17

DQ

Q’


The timing of which of the following signals can cause asetup-time violation ?

18

A. The input signal D(t)B. The output signal Q(t)C. Both of the aboveD. None of the above

DQ

Q’

D(t)

CLK

Q(t)

CombLogic


Causes of Timing Issues in Sequential Circuits

• Input to a FF comes from the output of another FF througha combinational circuit

• The FF and combinational circuit have a min & max delay

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

Which of the followingviolations occurs if max delayof R1 is zero & max delay ofthe combinational circuit isequal to the clock period?

A. Hold time violation for R2B. Setup violation for R2C. Hold time violation for R1D. Setup violation for R1E. None of the above


Setup Time Constraint



CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

Setup time constraint:

Tc ≥ tsetup+ max delay(FF) +

max delay(combinational)

Tc ≥ tpcq + tpd + tsetup


Causes of Timing Issues in Sequential Circuits



CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

Which of the violations wouldoccur if the min delay of R1was zero and the combinationalcircuit was just a wire?

A. Hold time violation for R2B. Setup violation for R2C. Hold time violation for R1D. Setup violation for R1E. None of the above


Hold Time Constraint



CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

Hold time constraint:thold < min delay(FF) +

min delay(combinational)

thold < tccq + tcd


FF Timing Parameters

23

R1 Combinational

CLK

R2

CLK

D1 Q1 D2

Once a flip flop has been built, its timing characteristicsstay fixed: tsetup , thold, tccq, tpcq

What about the clock? Does the clock edge arrive at thesame time to all the D-FFs on the chip?


• The clock doesn’t arrive at all registers at the same time• Skew: difference between the two clock edges• Perform the worst case analysis

t skew

C LK1

C LK2

CL

C LK2C LK1

R 1 R 2

Q 1 D 2

C LKdelay

C LK

Clock Skew


• In the worst case, CLK2 is earlier than CLK1• tpcq is max delay through FF, tpd is max delay through logic

CLK1

Q1

D2

Tc

tpcq tpd tsetuptskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

Setup Time Constraint with Skew


• In the worst case, CLK2 is later than CLK1• tccq is min delay through FF, tcd is min delay through logic

tccq tcd

thold

Q1

D2

tskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

CLK1tccq + tcd > thold + tskew

tcd > thold + tskew – tccq

Hold Time Constraint with Skew


Summary on timing constraints

R1 Combinational R2

Combinational:- Maximum delay = Propagation delay- Minimum delay = Contamination delay

Flip Flops:- Input:

- Setup time- Hold time

- Output:- Propagation clock-to-Q time- Contamination clock-to-Q time

Once the logic/FFsare built, thesetimingcharacteristics arefixed properties


Summary on timing constraints

R1 Combinational R2

Constraint inequalities:- Without clock skew: ≥ + +< +- With clock skew: ≥ + + ++ < +

Setup timeconstraint

Hold timeconstraint


CLK CLKA

B

C

D

X'

Y'

X

Y

per g

ate

Timing Characteristicstccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 25 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 25) ps > 70 ps ? No!

Timing Analysis Example


Timing Characteristicstccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 pstpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps


Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHzHold time constraint:

tccq + tcd > thold ?

(30 + 50) ps > 70 ps ? Yes!

Timing Analysis Example

CLK CLKA

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

per g

ate

Does it satisfy hold time constraint?A. YesB. No


Example: timing constraints

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

AND 20ns 10ns

NOT 10ns 10ns

XOR 110ns 50ns

FF

20ns

30ns

10ns

70ns

A

B

C

D

E

What’s the maximum frequency?A. 1 / 110nsB. 1 / 220nsC. 1 / 200nsD. 1 / 180nsE. None of the above



D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

≥ + + = 20 + 70 + (110 + 20)1) Assume = 0, find the maximum frequency

= 1 = 1220 10 ≅ 4.5MHz

A

B

C

D

E



D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

< +2) Does the circuit have a hold violation?A. YesB. NoC. I don’t know

30 < 10 Hold time violation !

A

B

C

D

E

AND 20ns 10nsNOT 10ns 10nsXOR 110ns 50ns

FF20ns30ns10ns70ns



D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

3) Where to place a buffer with = = 25 to solve this hold time violation?A. After A B. After B C. After C D. Before D E. Before E

< + 30 < 10 + 10 + 25 Hold time violationsolved!

A

B

C

D

E



D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

≥ + + + = 20 + 70 + 110 + 20 + 204) Assume = 20 , find the maximum frequency

= 1 = 1240 10 ≅ 4.16MHz

A

B

C

D

E



D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

D-FFD Q

5) Assume = 20 and the additional buffer, do we have a holdtime violation?+ < +30 + 20 < 10 + 10 + 25 Hold time violation !

A

B

C

D

E


Sequential Circuit Design Summary• SR Latch, D Latch, D-FF• Design procedure for FSMs

1. Capture FSM2. Create state table3. Assign the states4. Excitation table5. Implement the combinational logic

• Mealy vs. Moore FSM• Non-ideal properties of FFs

– Setup/hold time constraints– Maximum operating frequency– Clock skew 37


MORE FSM EXAMPLES TO DO ATHOME

38


15 cents for candy! Watch out – no change!

• Moore machine– outputs associated with

state

39

0¢[0]

10¢[0]

5¢[0]

15¢[1]

N’ D’ + Reset

D

D

N

N+D

N

N’ D’

Reset’

N’ D’

N’ D’

Reset

0¢

10¢

5¢

15¢

(N’ D’ + Reset)/0

D/0

D/1

N/0

N+D/1

N/0

N’ D’/0

Reset’/1

N’ D’/0

N’ D’/0

Reset/0

• Mealy machine– outputs associated with transitions


Example: Moore implementation• Encode states and map to logic

40

0 0 1 10 1 1 1X X 1 X1 1 1 1

Q1D1

Q0

ND

0 1 1 01 0 1 1X X 1 X0 1 1 1

Q1D0

Q0

ND

0 0 1 00 0 1 0X X 1 X0 0 1 0

Q1Open

Q0

ND

present state inputs next state outputQ1 Q0 D N D1 D0 open0 0 0 0 0 0 0

0 1 0 1 01 0 1 0 01 1 – – –

0 1 0 0 0 1 00 1 1 0 01 0 1 1 01 1 – – –

1 0 0 0 1 0 00 1 1 1 01 0 1 1 01 1 – – –

1 1 – – 1 1 1


Example: Mealy implementation

41

0¢

10¢

5¢

15¢

Reset/0

D/0

D/1

N/0

N+D/1

N/0

N’ D’/0

Reset’/1

N’ D’/0

N’ D’/0

Reset/0present state inputs next state output

Q1 Q0 D N D1 D0 open0 0 0 0 0 0 0

0 1 0 1 01 0 1 0 01 1 – – –

0 1 0 0 0 1 00 1 1 0 01 0 1 1 11 1 – – –

1 0 0 0 1 0 00 1 1 1 11 0 1 1 11 1 – – –

1 1 – – 1 1 1

0 0 1 00 0 1 1X X 1 X0 1 1 1

Q1Open

Q0

ND


FSM design: Multiple input counter

• Given FSM of a multiple input counter, design the circuitimplementing its functionality

00State01 11 10

Inputs00

01

11

10

00State

01 11 10

Input00 00 00 01 01

01 01 11 00 11

11 11 11 11 00

10 10 01 00 1042

present next state outputstate 00 01 10 11

S0 S0 S1 S2 S3 1S1 S0 S3 S1 S3 0S3 S1 S0 S0 S3 0S2 S1 S3 S2 S0 1

S0 S1

S2 S3

00

00

01

10 11

10

01,10

10

11

01

0011

00


Multiple input counter: Logic for D-FF

• Derive logic equations for inputs ofD-FF 00

State01 11 10

Input00 00 00 01 01

01 01 11 00 11

11 11 11 11 00

10 10 01 00 10

D1 00 01 11 10

I1I000

01

11

10

43

D0 00 01 11 10

I1I000

01

11

10


CSE140: Components and Design Techniquesfor Digital Systems

Register Transfer Level (RTL) Design

Slides from Tajana Simunic Rosing


High-Level State Machine• Some behaviors may be

too complex to describe byusing classical FSMs

• Soda dispenser– c: bit input, 1 when coin

deposited– a: 8-bit input: value of the

deposited coin– s: 8-bit input: cost of a soda– d: bit output, processor sets it

to 1 when total value ofdeposited coins equals orexceeds cost of a soda

as

cd

Sodadispenserprocessor

25

1 025

1

1

500

0

0

0

tot:25tot:50


46

Challenges in High-Level State Machines

as

cd


5.2

Which of the following makes theFSM design of this problemdifficult?

A. 8-bit input/outputB. Tracking the current totalC. Multibit comparisonD. All of the aboveE. None of the above

as

cd


25

1 025

1

1

500

0

0

0

tot:25tot:50


47

Benefits of HLSMs

• High-level state machine(HLSM) extends FSM with:– Multi-bit input/output– Local storage– Arithmetic operations

8 8as

cd


• Conventions– Numbers:

• Single-bit: '0' (single quotes)• Integer: 0 (no quotes)• Multi-bit: “0000” (double quotes)

– == for comparison equal– Multi-bit outputs must be

registered via local storage– // precedes a comment

Inputs: c (bit), a (8 bits), s (8 bits)Outputs: d (bit) // '1' dispenses sodaLocal storage: tot (8 bits)

Wait

Disp

Init

d:='0'tot:=0

c'∗(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Add


48

Benefits of HLSMs

• High-level state machine(HLSM) extends FSM with:– Multi-bit input/output– Local storage– Arithmetic operations

8 8as

cd


• Conventions– Each transition is implicitly ANDed

with a rising edge of the clock– Any bit output not explicitly

assigned a value in a state isimplicitly assigned to 0. Thisconvention does not apply formultibit outputs

– Every HLSM multibit output isregistered


Wait

Disp

Init

d:='0'tot:=0

c'∗(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Add


49

FSMs vs. HLSMs

How does the HLSM differ fromthe FSM for this problem?A. The HLSM stores multibit

data, but the FSM doesn’tB. The FSM stores the state but

the HLSM doesn’tC. Implementing HLSM and FSM

requires multibit data registersD.All of the aboveE. None of the above

8 8as

cd


a


Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'∗(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Add


50

Similarities between FSMs & HLSMs

Which of the following arecommon between HLSMs andFSMs?A. Transitions happen at the

edge of a clockB. They both have external

complex dataC. All of the aboveD. None of the above

8 8as

cd



Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'∗(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Add


51

RTL Design ProcessStep 1: Capture a high-level state machine- Describe the system’s desired behavior as a high-level state machine. The

state machine consists of states and transitions. The state machine is highlevel because the transition conditions and the state actions are more thanjust Boolean operations on single-bit input and outputs

Recommendations:- Always list all inputs, outputs and local registers on top of your HLSM

diagram- Clearly specify the size in bits of each of them- On states: update the value of registers, update of outputs- On transitions: express conditions in terms of the HLSM inputs or state of

the internal values and arithmetic operations between them.


52

RTL Design ProcessStep 2: Convert it to a circuit- 2.a: Create a datapath

- Create a datapath to carry out the data operations of the high levelstate machine

- Elements of your datapaths can be registers, adders, comparators,multipliers, dividers, etc.

External dataoutputs

Datapath...

DPcontrolinputs

...

...

External datainputs


RTL Design Process

A B

Saddreg

Q

Ildclr A B

ltcmpeq gt

mux2x1Q

I1

s0

I0

S = A+B (unsigned)A<B: lt=1A=B: eq=1A>B: gt=1

s0=0: Q=I0s0=1: Q=I1

clk^ and clr=1: Q=0clk^ and ld=1: Q=Ielse Q stays same

shift<L/R>I

Q

shiftL1: <<1shiftL2: <<2shiftR1: >>1...

A B

Ssub

S = A-B(signed)

upcntQ

incclr

clk^ and clr=1: Q=0clk^ and inc=1: Q=Q+1else Q stays same

A B

Pmul

P = A*B(unsigned)

RF

R_d

W_eW_a

W_d

R_eR_a

clk^ and W_e=1: RF[W_a]= W_dR_e=1: R_d = RF[R_a]

A

Qabs

Q = |A|(unsigned)

(signed)

Datapath components:


54

RTL Design ProcessStep 2: Convert it to a circuit- 2.b: Connect the datapath to a controller

- Connect the datapath to a controller block. Connect the external controlinputs and outputs to the controller block.

- Clearly label all control signals that are exchanged between thedatapath and the controller


Externalcontrolinputs

Controller...

Externalcontrol

outputs

...Datapath

...

DPcontrolinputs

DPcontroloutputs

...

...

...

External datainputs


55

RTL Design ProcessStep 2: Convert it to a circuit- 2.c: derive the controller’s FSM

- Convert the high-level state machine to a finite state machine (FSM) forthe controller, by replacing data operations with setting and reading ofcontrol signals to and from the datapath



Controller...

Externalcontrol

outputs

...Datapath

...

DPcontrolinputs

DPcontroloutputs

...

...

...

External datainputs The controller FSM

should have:- Inputs:

- Ext control inputs- DP control

outputs- Outputs:

- Ext. controloutputs

- DP control inputs


RTL Design Process: summary• Capture the behavior with

HLSM• Convert it to a circuit

– High-level architecture(datapath and control path)

– Datapath capable ofHLSM's data operations

– Design controller to controlthe datapath



Controller...

Externalcontrol

outputs

...Datapath

...

DPcontrolinputs

DPcontroloutputs

...

...

...

External datainputs


Step 2.a: Create Datapath for Soda Dispenser

• Need tot register to keep track ofthe money deposited so far

• Need 8-bit comparator to compares (current sum) and a (target cost)

• Need 8-bit adder to update:tot = tot + a

• Connect everything• Create control IO

ldclr

tot

8-bit<

8-bitadder

8

8

88

s a

Datapath

tot_ldtot_clr

tot_lt_s

Inputs: c (bit), a(8 bits), s (8 bits)Outputs : d (bit)Local registers: tot (8 bits)

WaitAdd

Disp

Init

d=0tot=0

c‘ (tot<s)‘c‘ ∗(tot<s)

d=1

c

tot= tot+a


Signals in Soda Dispenser

8

8

8

s

8

a

Datapath

tot_ldtot_clr

tot_lt_s

ldclr tot

8-bit<

8-bitadder

a

a


Wait

Disp

Init

d:='0'tot:=0 c’*(tot<s)’

c'∗(tot<s)

d:='1'

c

tot:=tot+a

SodaDispenser

Add

According to the current design, under which of the following conditions doesthe register output ‘tot’ change at the rising clock edge?A.Whenever the value of the coin inserted (‘a’) changesB.Whenever the cost of the soda (‘s’) changesC.When the signal tot_ld becomes highD.When the signal tot_clr becomes highE.Both C. & D.


Step 2.b: Connect Datapath to a Controller

• Controller’s inputs– External input c

(coin detected)– Input from datapath

comparator’soutput, which wenamed tot_lt_s

• Controller’s outputs– External output d

(dispense soda)– Outputs to datapath

to load and clearthe tot register

tot_lt_s

tot_clr

tot_ld

Controller Datapath

s

c

d

a8 8

ldclr

tot

8-bit<

8-bitadder

8

8

88

s a

Datapath

tot_ldtot_clr

tot_lt_s


Step 2.c – Derive the Controller’s FSM

• FSM has the same statesand arcs as HLSM

• Replace all references tothe data elements in theHLSM with appropriatecontrol signals & values tot_lt_s

tot_clr

tot_ld

Con

trolle

r

Dat

apat

h

s

c

d

a8 8

ldclr tpt

8-bit<

8-bitadder

8

8

88

s a

Datapath

tot_ldtot_clr

tot_lt_s

Inputs::c,tot_lt_s(bit)Outputs:d,tot_ld,tot_clr(bit)

Wait

Disp

Init

d=0tot_clr=1

c’*tot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add


Final Step: Implement the controller FSM

Implement the FSM as astate register and logic

d000000000

1

000000001

0

111100000

0

n0111111001

0

n1000010110

0

010101010

0

c001100110

0

s1000000001

1

s0000011110

1

tot_lt_s

tot_ld

tot_clr

Init

Wait

Add

Disp

I n p u t s : : c, tot_lt_s (bit)Outputs: d, tot_ld , tot_clr (bit)

Wait

Disp

Init

d=0tot_clr=1

c’*tot_lt_s

d=1

c

tot_ld=1

c

d

tot_ld

tot_clr

tot_lt_s

Controller

Add


Another RTL Design:Laser-Based Distance Measurer

• Laser-based distance measurement – pulse laser,measure time T to sense reflection– Laser light travels at speed of light, 3*108 m/sec– Distance is thus D = T sec * 3*108 m/sec / 2

Object ofinterest

D

2D = T sec * 3*108 m/secsensor

laser

T (in seconds)


63

Laser-Based Distance Measurer IO

• Inputs/outputs– B: bit input, from button, to begin measurement– L: bit output, activates laser– S: bit input, senses laser reflection– D: 16-bit output, to display computed distance

sensor

laser

T (in seconds)

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor


64

Laser-Based Distance Measurer: HLSM

• Declare inputs, outputs, and local storage– Dreg required for multi-bit output

• Create initial state, name it S0– Initialize laser to off (L:='0')– Initialize displayed distance to 0 (Dreg:=0)

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

a

Inputs: B (bit), S (bit)Outputs: L (bit), D (16 bits)Local storage: Dreg(16)

S0 ?

L := '0' // laser offDreg := 0 // distance is 0

DistanceMeasurer

(first state usuallyinitializes the system)

Recall: '0' means single bit,0 means integer


65


• Add another state, S1, that waits for a button press– B' – stay in S1, keep waiting– B – go to a new state S2

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

S0

L := '0'Dreg := 0

S1 ?

B' // button not pressed

B// buttonpressed

S0

DistanceMeasurer...


66


• Add a state S2 that turns on the laser (L:='1')• Then turn off laser (L:='0') in a state S3

Laser-based

distancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

DistanceMeasurer...

S0 S1

L := '0'Dreg := 0

S2

L := '1'// laser on

S3

L := '0'// laser off

B'

B


67


• Stay in S3 until sense reflection (S)• To measure time, count cycles while in S3

– To count, declare local storage Dctr– Initialize Dctr to 0 in S1. In S2 would have been O.K. too.

• Don't forget to initialize local storage—common mistake– Increment Dctr each cycle in S3

Laser-baseddistancemeasurer16

from button

to displayS

L

D

Bto laser

from sensor

a

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr + 1// count cycles

Dctr := 0// reset cycle

count

B' S' // no reflection

B

S // reflection?

Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)Local storage: Dreg, Dctr (16 bits)

DistanceMeasurer


68


• Once reflection detected (S), go to new state S4– Calculate distance– Assuming clock frequency is 3x108, Dctr holds number of meters, so

Dreg:=Dctr/2• After S4, go back to S1 to wait for button again

a

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr+1

Dreg := Dctr/2// calculate D

Dctr := 0

B' S'

B SS4

Inputs: B (bit), S (bit) Outputs: L (bit), D (16 bits)DistanceMeasurerLocal storage: Dreg, Dctr (16 bits)

Laser-based

distancemeasurer

16

from button

to displayS

L

D

Bto laser

from sensor


69

Laser-Based Distance Measurer: Create a Datapath

• HLSM data I/O DP I/O• HLSM local storage reg• HLSM state action and

transition condition datacomputation Datapathcomponents and connections

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr+1


Dctr := 0

B' S'

B SS4


Datapath

Dreg_clrDreg_ld

Dctr_clrDctr_ld

clrld

Q

IDreg: reg(16)

A B

SAdd1: add(16)

clrld

Q

Dctr: reg(16)I

1 16

16Shr1: shiftR1(16)

I

Q

16

16

16D


70

Laser-Based Distance Measure:Connecting the Datapath to a Controller

D

B L

S

16to display

from buttonController

to laser

from sensorDreg_clr

Dreg_ld

Dctr_clr

Dctr_ld

Datapath

300 MHz Clock


71

Laser-Based Distance Measurer:Derive the Controller FSM

• FSM has samestates,transitions, andcontrol I/O

• Achieve eachHLSM dataoperation usingdatapath controlsignals in FSM

S0 S1 S2 S3

L := '0'Dreg := 0

L := '1' L := '0'Dctr := Dctr+1


Dctr := 0

B' S'

B SS4


Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld

S0 S1 S2 S3

L = 0 L = 1 L = 0L = 0

B S

B SS4

Dreg_clr = 1Dreg_ld = 0Dctr_clr = 0Dctr_ld = 0(laser off)(clear Dreg)

Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_ld = 1(laser off)(count up)

Dreg_clr = 0Dreg_ld = 0Dctr_clr = 1Dctr_ld = 0(clear count)

L = 0Dreg_clr = 0Dreg_ld = 1Dctr_clr = 0Dctr_ld = 0(load Dreg with Dctr/2)(stop counting)

Dreg_clr = 0Dreg_ld = 0Dctr_clr = 0Dctr_ld = 0(laser on)

Controller

clrld

clrld

Q Q

IDctr: reg(16) Dreg: reg(16)

16

16

D

Datapath

Dreg_clr

Dctr_clrDctr_ld

Dreg_ld

Shr1: shiftR1(16)

A B

SAdd1: add(16)

I

1

16

16

16

I

Q

HLSM


72

Laser-Based Distance Measurer:Simplify the Controller FSM

• Same FSM, usingconvention ofunassignedoutputs implicitlyassigned 0

Inputs: B, S Outputs: L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_ld

S0 S1 S2 S3

L = 0 L = 1 L = 0

B′ S′

B S

Dreg_clr = 1(laser off)(clear Dreg)

Dctr_ld = 1(laser off)(count up)

Dctr_clr = 1(clear count)

Dreg_ld = 1Dctr_ld = 0(load Dreg with Dctr/2)(stop counting)

(laser on)

S4

Controller

Some assignments to 0 still shown, due totheir importance in understandingdesired controller behavior

Date post:	15-Aug-2020
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CSE140: Design of Sequential Logic · 2017-08-29 · Sources: TSR, Katz, Boriello & Vahid...

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