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CSE260-1-1
Review for Exam 1
Chapters 1 through 3
CSE260-1-2
Chapter 1 Overview
Information Representation Number Systems [binary, octal and
hexadecimal] Base Conversion Decimal Codes [BCD (binary coded
decimal)] Alphanumeric Codes Parity Bit Gray Codes
CSE260-1-3
1-2 Number Systems
Positive radix, positional number systems Examples:
• Decimal (radix r =10)
• Binary (radix r =2)
• Octal (radix r = )• Hexadecimal (r = )
Ex: 1101.01 = ( . )10
Ex: 24.3 = 2x101 + 4x100+3x10-1
Digits (0-9)
Bits (0-1)
Digits: 1,2,…9, A, B, C, D, E, F
CSE260-1-4
Range of numbers
Binary number: ex. a 3-bit number: n=3• 000, 001 … ,111 or in decimal system: 0, 1 … 7
Total of 8 numbers (=23) Range: from 0 to 7 (0 to 23-1)
• In general a n-bit number represents: 2n different numbers Min: 0
Max number: 2n-1
For fractions: m bits after the radix point:• Min: 0• Max number: (2m -1)/2m
CSE260-1-5
Use of HEX system
Short hand notation of large binary numbers:• Each HEX digits can be represented by exactly 4 bits
(16=24)
• Thus (10011110.0101)2
Conversion from binary to HEX and HEX to binary is very easy:
(10011101)2 = ( )16
(1010110110.11)2 = ( )16
B39.716 = ( )2
9 E . 5
CSE260-1-6
Octal system
Radix r = 8 8 digits:
• 0, 1, 2,…7
Ex: 2758 = 2x82 + 7x8 + 5x1 = 128 + 56 + 5
= 18910
Each octal digit can be represented by 3 bits
CSE260-1-7
1-3 Conversion Between Bases
To convert from one base to another:
1) Convert the Integer Part
2) Convert the Fraction Part
3) Join the two results with a radix point
CSE260-1-8
Example: convert (325.65)10 to hex
Integer part: 32510 = ( . )16
Fractional part: .65
325/16 = 20 and rem = 520/16 = 1 and rem = 4 1/16 = 0 and rem = 1 Most significant
Least significant digit
Thus 32510 = 14516
0.65x16 = 10.4 thus int = 10= A0.4x16 = 6.4 thus int = 60.4x16 = 6.4 thus int = 6Etc.
Most significant
Least significant
Thus .6510 = A6616325.6510 = 145.A6616
CSE260-1-9
Conversion - Summary
Binary
DecimalHexadecimal
Octal
Divisions (or x) by 16
Ai.16i
Ai.8i
Divisons by 8
Divisons by 2SAi.2i
Group in bits of 3
Group in bits of 4
Octal Hex: through the binary representation
CSE260-1-10
1-4 Binary Codes
A n-bit binary code is a n-bit word which can represent up to 2n different elements.
Example: 3-bit code can represent up to 8 different elements”
CSE260-1-11
Binary Coded Decimal (BCD)
The BCD code is the 8,4,2,1 code. This code only encodes the first ten
values from 0 to 9. Each decimal digit is coded
separately by 4 bits Example:
• (325)10 = (0011 0010 0101)BCD
Exercise: (856)10 = ( )BCD
523
12
Overview Chapter 2
• Binary Logic and Gates• Boolean Algebra• Standard Forms• Two-Level Optimization• Map Manipulation• Other Gate Types• Exclusive-OR Operator and Gates• High-Impedance Outputs
13
Operator Definitions and Truth Tables
Truth table - a tabular listing of the values of a function for all possible combinations of values on its arguments
Example: Truth tables for the basic logic operations:
111
001
010
000
Z = X·YYX
AND ORX Y Z = X+Y0 0 00 1 11 0 11 1 1
01
10
X
NOT
XZ =
14
3.
9.
4.2. X . 1 X=
X . 0 0=
2-2 Boolean Algebra Boolean algebra deals with binary variables and
a set of three basic logic operations: AND (.), OR (+) and NOT ( ) that satisfy basic identities
1. X + 0 X=
+X 1 1=
7. 8. 0=X . X1=X + X
X = X
Existence 0 and 1 or operations with 0 and 1
Idempotence
Involution
5. 6. X . X X=X + X X=Existence complements
Basic identities
DualReplace “+” by “.”, “.” by +,“0” by “1” and “1’’ by”0”
15
Commutative
Associative
Distributive
DeMorgan’s
Boolean Algebra
10. X + Y Y + X=
12. (X + Y) Z+ X + (Y Z)+=
16. X + Y X . Y=
11. XY YX=13. (XY)Z X(YZ )=
15. X+ YZ (X + Y)(X + Z)=
17. X . Y X + Y=
Dual
Boolean Theorems of multiple variables
14. X (Y+ Z) XY XZ+=
16
Other useful Theorems
Minimization
Absorption
Simplification
Consensus
XY + XY = Y (X + Y)(X + Y) = Y
X + XY = X X(X + Y) = X
X + XY = X + Y X(X + Y) = XY
XY + XZ + YZ = XY + XZ
(X + Y)( X + Z)(Y + Z) = (X + Y)( X + Z)
Dual
17
2-3 Standard (Canonical) Forms
It is useful to specify Boolean functions in a form that:• Allows comparison for equality.• Has a correspondence to the truth
tables Canonical Forms in common usage:
• Sum of Products (SOP), also called Sum or Minterms (SOM)
• Product of Sum (POS), also called Product of Maxterms (POM)
18
Examples: Two variable minterms and maxterms.
The index above is important for describing which variables in the terms are true and which are complemented.
Maxterms and Minterms
Index Minterm Maxterm
0 (00) x y x + y
1 (01) x y x + y
2 (10) x y x + y
3 (11) x y x + y
19
Index Examples – Four Variables
Index Binary Minterm Maxterm i Pattern mi Mi
0 0000 1 0001 3 0011 5 0101 7 0111 10 1010 13 1101 15 1111
dcba ?
? dcba +++dcba
dcba dcba +++dcba +++
dcba dcba +++?
dbadcba dcba +++
?c
i mM = i ii Mm =
Notice: the variables
are in alphabetical order in a standard formdcba
Relationship between min and MAX term?
20
Minterm Function Example
F(A, B, C, D, E) = m2 + m9 + m17 + m23
F(A, B, C, D, E) write in standard form:
Sum of Product (SOP) expression: • F = Σm(2, 9, 17, 23)
A’B’C’DE’ + A’BC’D’E + AB’C’D’E + AB’CDE
m2 m9 m17 m23
21
Expressing a function with Maxterms
Start with the SOP: F1(x,y,z) =m1 + m4 + m7 Thus its complement F1can be written as
• F1 = m0 +m2 +m3 + m5 + m6 (missing term of F1)
Apply deMorgan’s theorem on F1:• (F1 = (m0 +m2 +m3 + m5 + m6)
= m0.m2.m3.m5.m6
= M0.M2.M3.M5.M6
= ΠM(0,2,3,5,6)
Thus the Product of Sum terms (POS):
)z y z)·(x y ·(x z) y (x F1 ++++++=
z) y x)·(z y x·( ++++
also called, Big M notation
22
2-4 Circuit Optimization
Goal: To obtain the simplest implementation for a given function
Optimization requires a cost criterion to measure the simplicity of a circuit
Distinct cost criteria we will use:• Literal cost (L)• Gate input cost (G)• Gate input cost with NOTs (GN)
23
Literal – a variable or its complement Literal cost – the number of literal
appearances in a Boolean expression corresponding to the logic circuit diagram
Examples (all the same function):• F = BD + AB’C + AC’D’ L = 8• F = BD + AB’C + AB’D’ + ABC’ L = • F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D) L =• Which solution is best?
Literal Cost
24
Karnaugh Maps (K-map)
A K-map is a collection of squares• Each square represents a minterm• The collection of squares is a graphical representation
of a Boolean function• Adjacent squares differ in the value of one variable• Alternative algebraic expressions for the same function
are derived by recognizing patterns of squares The K-map can be viewed as
• A reorganized version of the truth table• A topologically-warped Venn diagram as used to
visualize sets in algebra of sets
25
2-5 Map Manipulation: Systematic Simplification
A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle with the number of squares a power of 2.
A prime implicant is called an Essential Prime Implicant if it is the only prime implicant that covers (includes) one or more minterms.
Prime Implicants and Essential Prime Implicants can be determined by inspection of a K-Map.
26
Sometimes a function table or map contains entries for which it is known:• the input values for the minterm will never occur, or• The output value for the minterm is not used
In these cases, the output value need not be defined Instead, the output value is defined as a “don't care” By placing “don't cares” ( an “x” entry) in the function
table or map, the cost of the logic circuit may be lowered.
Example 1: A logic function having the binary codes for the BCD digits as its inputs. Only the codes for 0 through 9 are used. The six codes, 1010 through 1111 never occur, so the output values for these codes are “x” to represent “don’t cares.”
Don't Cares in K-Maps
27
Other Gate Types: overview
A B BUF NAND NOR XOR XNOR
0 0 0 1 1 0 1
0 1 0 1 0 1 0 1 0 1 1 0 1 0
1 1 1 0 0 0 1
A AB
AB
AB
AB
28
The Tri-State Buffer
For the symbol and truth table, IN is the data input, and EN, the control input.
For EN = 0, regardless of the value on IN (denoted by X), the output value is Hi-Z.
For EN = 1, the output value follows the input value.
Variations: • Data input, IN, can be inverted • Control input, EN, can be
invertedby addition of “bubbles” to signals.
IN
EN
OUT
EN IN OUT
0 X Hi-Z
1 0 0
1 1 1
Symbol
Truth Table
OUT= IN.EN
Charles Kime & Thomas Kaminski
© 2008 Pearson Education, Inc.(Hyperlinks are active in View Show mode)
Chapter 3 – Combinational Logic Design
Logic and Computer Design Fundamentals
NAND Mapping Algorithm
1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
....
.
.
....
.
.
....
NOR Mapping Algorithm
1. Replace ANDs and ORs:
2. Repeat the following pair of actions until there is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.
.
.
....
.
.
.
.
.
....
.
.
.
Enabling Function
Enabling permits an input signal to pass through to an output
Disabling blocks an input signal from passing through to an output, replacing it with a fixed value
The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1
When disabled, 0 output When disabled, 1 output See Enabling App in text
XF
EN
(a)
ENX
F
(b)
3-7 Decoding A n-bit binary code can represent up to m=2n
elements:
m elements n-bit binary code
Decoding - the conversion of an n-bit input code to an m-bit output code withn ≤ m ≤ 2n such that each valid code word produces a unique output code
A0
: :An-1
D0
D1
::Dm-1
n-2n decodern bits
m-elements ≤ 2n
encoding
decoding(ex. 256 alpha-num. chars) (ex. 8-bit ASCII code)
2-to-4 Line Decoder circuit
D0= A1 A0
D1= A1 A0
D2= A1 A0
D3= A1 A0
A1
A0
Notice that the outputs of the decoder correspond to the minterms: Di=mi
Decoder Expansion
Larger decoders can be realized by implementing each minterm using a single AND gate:• However for large decoders this requires
multiple input AND gates which is not always feasible.
• Better to use a hierarchical approach: build larger ones from smaller decoders.
Approach: • Output AND gates have only 2 inputs and
implement the minterms.• The output AND gates are driven by two
decoders with their numbers of inputs either equal or differing by 1.
Rule for building large decoders
k-to-2k decoder:• One needs 2k output AND gates• If k can be divided by 2:
use two k/2-to-2k/2 decoders
• If k cannot divided by 2: use a (k+1)/2 and use a (k-1)/2 decoder.
Previous example: 3-to-8 decoder (k=3):• Use a 2-to-4 and a 1-to-2 decoder
Combinational Logic Implementation- Decoder and OR Gates
Implement m functions of n variables with:• Sum-of-minterms expressions• One n-to-2n-line decoder• m OR gates, one for each output
Example
Design and implement a majority function F(ABC) using a 3-to-8 decoder
Truth table:
Minterms:• F=m(3,5,6,7)
Implementation using decoder:
A B C F0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1
F
01234567
A
B
C
2
1
0
Indicate MSB, LSB
Encoding
Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears: ex. D1=1 output 0001
Examples: Octal-to-Binary encoder Other examples?
01000
1000
A0
: :An-1
D0
D1
::Dm-1
enco
der
0123
m-1
0
1
2
n-1
Priority Encoder If more than one input value is 1, then the encoder
just designed does not work. An encoder that can accept all possible
combinations of input values and produce a meaningful result is a priority encoder.
Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.
D0
D1
D2
D3
A1
A0
?
V
0
1
2
3
1
0
To
pro
cess
or
3-9 Selecting (multiplexers) Selecting of data or information is a critical
function in digital systems and computers Circuits that perform selecting have:
• A set of n information inputs from which the selection is made
• A set of k control (select) lines for making the selection• A single output 0
123::
n-1
I0I1I2I3
In-1
OUT
Sk-1..S1 S0
n ≤ 2k inputs
k select lines
k-1 .. 1 0
4:1 MUX realization
Expression for OUT
Circuit implementation: SOP• 4 AND gates (4 product terms)• 2-to-4 line decoder (to generate the
minterms)
S1 S0 OUT 0 0 I0 0 1 I1 1 0 I2 1 1 I3
OUT = S1S0 I0+ S1S0 I1+ S1S0 I2+ S1S0 I3
or OUT = Σ mi Iii=0
2k-1
m3m2m1m0
Exercise Build a 8:1 MUX using two 4:1 and one 2:1 muxes
4:1
0123
1 0
I0I1I2I3
4:1
0123
1 0
I4I5I6I7
S1 S0
S1 S0
0
1
OUT
S2
Ex: S2S1S0=110 : select I6
Multiplexer-based combinational circuitsrealization- Approach 1
A mux can be easily used to implement a function defined by a truth table (lookup table)
Indeed the output F of a mux is equal to:
F = Σ mi Iii=0
2k-1
Give the input Ii the value of 0 or 1as shown in the truth table
4:1
0123
1 0
F0110
A B
Example
A B OUT =F 0 0 I0 0 0 1 I1 1 1 0 I2 1
1 1 I3 0
m0
m1
m2
m3
F= Σm(1,2)
Combinational Logic Implementation- Multiplexer Approach 2
Implement any m functions of n + 1 variables by using:• An m-wide 2n-to-1-line multiplexer
Design:• Find the truth table for the functions.• Based on the values of the first n variables,
separate the truth table rows into pairs• For each pair and output, define a rudimentary
function of the final variable (0, 1, X, )X