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CSE331 W13.1 Irwini Fall 2007 PSU
CSE 331Computer Organization and
DesignFall 2007
Week 13
Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)Section 2: Krishna Narayanan
Course material on ANGEL: cms.psu.edu
[adapted from D. Patterson slides]
CSE331 W13.2 Irwini Fall 2007 PSU
Head’s Up Last week’s material
Multicycle MIPS datapath and control path implementation, microprogramming
This week’s material Input/Output – dealing with exceptions and interrupts
- Reading assignment – PH: 5.6, 8.1, 8.5, A.7-A.8
Next week’s material Intro to pipelined datapath design
- Reading assignment – PH: 6.1
Reminders HW 7 is due Monday, Dec 3rd (by 11:55pm) Quiz 7 closes Tues., Dec 4th (by 11:55pm) Final Exam is Tues., Dec 18th, 10:10 to noon, 112 Walker Dec. 12th deadline for filing grade corrections/updates
CSE331 W13.3 Irwini Fall 2007 PSU
Well, surely a higher college GPA ought to be correlated with career success … the data didn’t bear this out. … fast-trackers have identifiable qualities and show definite trends. One quality is a whatever-it-takes attitude … a willingness to do whatever it takes to make a project succeed … If that means working weekends … they do it. Another quality is a solid, unflappable understanding of all the technologies they are using or developing. … Finally, these high-output types seemed to innately grasp that they are members of a large team … they are the ones always helping everyone else.
The Pentium Chronicles, Colwell, pg. 140
CSE331 W13.4 Irwini Fall 2007 PSU
Major Components of a Computer
Processor
Control
Datapath
Memory
Devices
Input
Output
Important metrics for an I/O system Performance Compatibility Expandability and diversity Dependability Cost, size, weight
CSE331 W13.5 Irwini Fall 2007 PSU
Input and Output Devices I/O devices are incredibly diverse with respect to
Behavior – input, output or storage Partner – human or machine Data rate – the peak rate at which data can be transferred
between the I/O device and the main memory or processor
Device Behavior Partner Data rate (Mb/s)
Keyboard input human 0.0001
Mouse input human 0.0038
Laser printer output human 3.2000
Network/LAN input or output
machine 100.0000-1000.0000
Magnetic disk storage machine 240.0000-2560.0000
Graphics display
output human 800.0000-8000.0000
8 orders of magnitude
range
CSE331 W13.6 Irwini Fall 2007 PSU
Input/Output in SPIM via System Calls
SPIM provides a small set of operating-system-like services through the syscall instruction
Load the system call code into register $v0 and the arguments into registers $a0 trhough $a3
Return values are put in register $v0
Service Code Args Results
print_int 1 $a0 = integer
print_string 4 $a0 = string
read_int 5 integer in $v0
read_string 8 $a0 = buffer, $a1 = length
print_char 11 $a0 = char
read_char 12 char in $a0 ?$v0?
CSE331 W13.7 Irwini Fall 2007 PSU
Communication of I/O Devices and Processor How the processor directs the I/O devices
Special I/O instructions- Must specify both the device and the command
Memory-mapped I/O- Portions of the high-order memory address space are
assigned to each I/O device. Read (lw) and writes (sw) to those memory addresses are interpreted as commands to the I/O devices
- Load/stores to the I/O address space done only by the OS How the I/O device communicates with the
processor Polling – the processor periodically checks the status of an
I/O device to determine its need for service- Processor is totally in control – but does all the work- Can waste a lot of processor time due to speed differences
Interrupt-driven – the I/O device issues an interrupts to the processor to indicate that it needs attention
CSE331 W13.8 Irwini Fall 2007 PSU
“Real” I/O in SPIM
Processor
Control
DatapathMemory
Devices
Receiver
Transmitter
SPIM supports one memory-mapped I/O device – a terminal with two independent units
Transmitter writes characters to the display Receiver reads characters from the keyboard
CSE331 W13.9 Irwini Fall 2007 PSU
Review: MIPS (spim) Memory AllocationMemory
230
words
0000 0000
f f f f f f f c
UserCode
Reserved
Static data
Mem Map I/O
0040 0000
1000 00001000 8000 ( 1004 0000)
7f f e f f fcStack
Dynamic data
$sp
$gp
PC
Kernel Code & Data 8000 0080
f f f f 0000
CSE331 W13.10 Irwini Fall 2007 PSU
Terminal Receiver (Input) Control with SPIM
Input is controlled via two memory-mapped device registers (i.e., each is a special memory location)
unused
0
ready(read only)
1
interrupt enable
Receiver control(0xffff0000)
unused
07
received byte from keyboard(read only)
Receiver data(0xffff0004)
The keyboard inputs into the Receiver data register which sets the ready bit in the Receiver control register (i.e., the keyboard input is ready to be read by the program)
Reading the next input character from the Receiver data register resets the ready bit in the Receiver control register
CSE331 W13.11 Irwini Fall 2007 PSU
Terminal Output Control with SPIM
Output is controlled via two memory-mapped device registers (i.e., each is a special memory location)
unused
0
ready(read only)
1
interrupt enable
Transmitter control(0xffff0008)
unused
07
transmitted byte to display
Transmitter data(0xffff000c)
The display outputs the Transmitter data register character which sets the ready bit in the Transmitter control register (i.e., the display is ready to accept a new output character)
Writing the next character to output into the Transmitter data register resets the ready bit in the Transmitter control register
CSE331 W13.12 Irwini Fall 2007 PSU
MIPS I/O Instructions
MIPS has 2 coprocessors: Coprocessor 0 handles exceptions including input and output interrupts, Coprocessor 1 handles floating point
Coprocessors have their own register sets so have instructions to move values between these registers and the CPU’s registers
mfc0 rd, rt #move from coprocessor 0
0x10 0 rt rd 0 0
mtc0 rt, rd #move to coprocessor 00x10 4 rt rd 0 0
Register # Use
BadVAddr 8 bad mem addr
Count 9 timer
Compare 11 timer compare
Status 12 intr mask & enable bits
Cause 13 excp type and pending intr’s
EPC 14 addr of instr causing excp
CSE331 W13.13 Irwini Fall 2007 PSU
Polling in SPIM Be sure that memory-mapped I/O is enabled
(through the PCSpim “Settings” dialog box)
li $t0, 0xffff0000 #recv ctrlli $t1, 0xffff0004 #recv datali $t2, 0xffff0008 #trans ctrlli $t3, 0xffff000c #trans data
mtc0 $zero, $12 #disable interrupts
I1: lw $t4, 0($t0) #poll recv ready bitandi $t4, $t4, 1beq $t4, $zero, Il #loop til recv readylw $t6, 0($t1) #read input character
I2: lw $t4, 0($t2) #poll trans ready bitandi $t4, $t4, 1beq $t4, zero, I2 #loop til trans readysw $t6, 0($t3) #echo (print)
character
CSE331 W13.14 Irwini Fall 2007 PSU
The Downsides of Polling
Input and output devices are very slow compared to the processor
These time lags are simulated in SPIM which measures time in instructions executed, not in real clock time
After the transmitter starts to write a character, the transmitter’s ready bit becomes 0. It doesn’t become ready again until the processor has executed a (large) fixed number of instructions. (You don’t want to single step the simulator!)
Polling will execute the “loop til ready” code thousands of times. While the input or output is occurring, nothing else can be done – a waste of resources.
There is a better way
CSE331 W13.15 Irwini Fall 2007 PSU
I/O Interrupts An I/O interrupt is used to signal an I/O request for
service Can have different urgencies (so may need to be prioritized) Need to identity the device generating the interrupt
An I/O interrupt is asynchronous wrt instr execution An I/O interrupt is not associated with any instruction and
does not prevent any instruction from completion- You can pick your own convenient point to take an interrupt
Advantage User program progress is only halted during the actual
transfer of I/O data to/from user memory space Disadvantage – special hardware is needed to
Cause an interrupt (I/O device) Detect an interrupt and save the proper information to
resume after servicing the interrupt (processor)
CSE331 W13.17 Irwini Fall 2007 PSU
Interrupt Driven Input
memory
userprogram
1. input interrupt
2.1 save PC
Processor
ReceiverMemory
addsubandorbeq
lbusb...jr
2.2 jump to interruptservice routine
2.4 returnto user code
Keyboard
2.3 service interrupt
inputinterruptserviceroutine
CSE331 W13.18 Irwini Fall 2007 PSU
Interrupt Driven Input in SPIM
1. the Receiver indicates with an interrupt that it has input a new character from the keyboard into the Receiver data register
- writing to the Receiver data register sets the Receiver control register ready bit to 1
2. the user process responds to the interrupt by transferring control to an interrupt service routine that copies the input character into the user memory space
- reading the Receiver data register resets the Receiver control register ready bit to 0
unused
readyinterrupt enable
Receiver control(0xffff0000)
unused
received byte
Receiver data(0xffff0004)
65
1 10
CSE331 W13.20 Irwini Fall 2007 PSU
Interrupt Driven Output
Processor
TrnsmttrMemory
Display
addsubandorbeq
lbusb...jr
memory
userprogram
1.output interrupt
2.1 save PC
outputinterruptserviceroutine
2.2 jump to interruptservice routine
2.4 returnto user code
2.3 service interrupt
CSE331 W13.21 Irwini Fall 2007 PSU
Interrupt Driven Output in SPIM
1. the transmitter indicates with an interrupt that it has successfully output the character in the Transmitter data register in memory to the display
- reading from the Transmitter data register sets the Transmitter control register ready bit to 1
2. the user process responds to the interrupt by transferring control to an interrupt service routine that writes the next character to output from the user memory space into the Transmitter data register
- writing to the Transmitter data register resets the Transmitter control register ready bit to 0
unused
readyinterrupt enable
Transmitter control(0xffff0008)
unused
transmitted byte
Transmitter data(0xffff000c)
65
1 10
CSE331 W13.22 Irwini Fall 2007 PSU
Additions to MIPS ISA for I/O Coprocessor 0 records the information the software
needs to handle exceptions (including interrupts) EPC (register 14) – holds the address+4 of the instruction
that was executing when the exception occurred Status (register 12) – exception mask and enable bits
- Intr Mask = 1 bit for each of 6 hw and 2 sw exception levels (1 enables exception at that level, 0 disables them)
- User mode = 0 if running in kernel mode when exception occurred; 1 if running in user mode (fixed at 1 in SPIM)
- Excp level = set to 1 (disable exceptions) when an exception occurs; should be reset by exception handler when done
- Intr enable = 1 if exception are enabled; 0 if disabled
15 8 4 1 0
Intr Mask
Intr enableUser modeExcp level
CSE331 W13.23 Irwini Fall 2007 PSU
Additions to MIPS ISA, Con’t Cause (register 13) – exception pending and type bits
- PI: bits set if exception occurs but not yet serviced– so can handle more than one exception occurring at same time, or
records exception requests when exception are disabled
- Exception code: encodes reasons for exception– 0 (INT) external interrupt (I/O device request)
– 4 (AdEL) address error trap (load or instr fetch)
– 5 (AdES) address error trap (store)
– 6 (IBE) bus error on instruction fetch trap
– 7 (DBE) bus error on data load or store trap
– 8 (Sys) syscall trap
– 9 (Bp) breakpoint trap
– 10 (RI) reserved (or undefined) instruction trap
– 12 (Ov) arithmetic overflow trap
15 8Pending
exception (PI)
6 2Exception
code
31Branchdelay
PI2 = trans intrPI3 = recv intr PI2 = trans intr
CSE331 W13.24 Irwini Fall 2007 PSU
MIPS Exception Return Instruction
Exception return – sets the Excp level bit in coprocessor 0’s Status register to 0 (reenabling exception) and returns to the instruction pointed to by coprocessor 0’s EPC register
eret #return from exception
0x10 1 0 0 0 0x18
CSE331 W13.25 Irwini Fall 2007 PSU
Example I/O Interrupts in SPIM - Enable
li $t0, 0xffff0000 #recv ctrlli $t1, 0xffff0004 #recv datali $t2, 0xffff0008 #trans ctrlli $t3, 0xffff000c #trans data
mfc0 $t4, $13andi $t4, $t4, 0xffff00ff #clear Pending
interruptmtc0 $t4, $13 #(PI) bits in Cause reg
li $t4, 0x2sw $t4, 0($t0) #enable recv interruptssw $t4, 0($t2) #enable trans
interrupts
mfc0 $t4, $12ori $t4, $t4, 0xff01 #enable intr and maskmtc0 $t4, $12 #in Status reg
#do something useful while I/O is taking place#when I/O interrupts occur transfer control to#exception handler (at address 0x80000180)
CSE331 W13.26 Irwini Fall 2007 PSU
Example I/O Interrupts in SPIM - Handler
.ktext 0x80000180mfc0 $t4, $13 #get ExcpCode from Causesrl $t5, $t4, 2andi $t5, $t5, 0x1f #ExcpCode in $t5, if 0bne $t5, $zero, excp #then I/O intr has
occurred
ck_recv:andi $t5, $t4, 0x800 #check for PI3 (input),beq $t5, $zero, ck_trans #if 0,then trans
intr
I1: lw $t5, 0($t0) #check recv readyandi $t5, $t5, 1beq $t5, $zero, no_recv_readylw $t6, 0($t1) #input character into $t6
andi $t4, $t4, 0xfffff7ff #clear PI3 bit in Cause reg
mtc0 $t4, $13
CSE331 W13.27 Irwini Fall 2007 PSU
Example I/O Interrupts in SPIM – Handler, con’t
ck_trans:beq $t1, $zero, ret_hand #no character to
echo yetandi $t5, $t4, 0x400 #check for PI2 (output)beq $t5, $zero, ret_hand #if 0, then no
trans intr
I2: lw $t5, 0($t2) #check trans readyandi $t5, $t5, 1beq $t5, $zero, no_trans_readysw $t6, 0($t3) #echo character to
displaymfc0 $t4, $13andi $t4, $t4, 0xfffffbff #clear PI2 bit in
Cause regmtc0 $t4, $13
ret_hand:mfc0 $t4, $12ori $t4, $t4, 0xff01 #enable intr and maskmtc0 $t4, $12 #in Status reg
eret #return from intr
CSE331 W13.29 Irwini Fall 2007 PSU
“… designed the P6 frontside bus to be transaction-oriented. Chips that connected to the bus were known as bus agents … This transaction orientation is [now] a standard feature of most modern microprocessor buses, despite its complexity and the implication that all bus agents must continuously monitor the bus and track the overall state … it’s a good trade-off between the expense (wires, motherboard routing, and CPU package pins) and inexpensive (transistors on the CPU)
The Pentium Chronicles, Colwell, pg. 76
CSE331 W13.30 Irwini Fall 2007 PSU
Exceptions in General
Exception = unprogrammed control transfer system takes action to handle the exception
- must record the address of the offending or next to execute instruction and save (and restore) user state
returns control to user after handling the exception
user program
normal control flow:
sequential, jumps,
branches, calls, returns
SystemExceptionHandlerException
return fromexception
CSE331 W13.31 Irwini Fall 2007 PSU
Two Types of Exceptions Interrupts
caused by external events (i.e., request from I/O device) asynchronous to program execution may be handled between instructions simply suspend and resume user program
Traps caused by internal events
- exceptional conditions (e.g., arithmetic overflow, undefined instr.)
- errors (e.g., hardware malfunction, memory parity error)- faults (e.g., non-resident page – page fault)
synchronous to program execution condition must be remedied by the trap handler instruction may be retried (or simulated) and program
continued or program may be aborted
CSE331 W13.32 Irwini Fall 2007 PSU
Additions to MIPS ISA for Interrupts
Control signals to write EPC (EPCWrite), Cause and Status (Cause&StatusWrite)
Hardware to record the type of interrupt in Cause Modify the finite state machine so that
the address of interrupt handler (8000 0180hex) can be loaded into the PC, so must increase the size of PC mux
and save the address of the next instr in EPC
CSE331 W13.34 Irwini Fall 2007 PSU
Interrupt Modified Multicycle Datapath
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
3
4
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
3
EP
C
8000 0180
Cause&StatusWrite
EPCWriteInterrupt
Ca
us
e
Sta
tus
CSE331 W13.36 Irwini Fall 2007 PSU
Interrupt Modified FSMIorD = 0
MemRead;IRWriteALUSrcA = 0ALUsrcB = 01ALUOp = 00
PCSource = 00PCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01
PCSource = 01PCWriteCond
PCSource = 10PCWrite
MemReadIorD = 1
MemWriteIorD = 1
RegDst = 1RegWrite
MemtoReg = 0
RegDst = 0RegWrite
MemtoReg = 1
Start
Instr Fetch Decode
Write Back
Memory Access
Execute
(Op = R-
type)
(Op =
beq)
(Op = lw or
sw) (Op = j)
(Op = lw)(Op = sw)
0 1
2
3
4
5
6
7
8 9
Interruptpending?
Cause&StatusWriteEPCWrite;PCWriteIntrOrExcp = 0PCSource = 11
11
CSE331 W13.37 Irwini Fall 2007 PSU
Additions to MIPS ISA for Traps
Control signals to write EPC (EPCWrite & IntrOrExcp), Cause and Status (Cause&StatusWrite)
Hardware to record the type of trap in Cause Further modify the finite state machine so that
for traps, record the address of the current (offending) instruction in the EPC, so must undo the PC = PC + 4 done during fetch
CSE331 W13.39 Irwini Fall 2007 PSU
Trap Modified Multicycle Datapath
Address
Read Data(Instr. or Data)
Memory
PC
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
Write Data
IRM
DR
AB
AL
Uo
ut
SignExtend
Shiftleft 2 ALU
control
Shiftleft 2
ALUOpControl
IRWriteMemtoReg
MemWriteMemRead
IorD
PCWrite
PCWriteCond
RegDstRegWrite
ALUSrcAALUSrcB
zero
PCSource
1
1
1
1
1
10
0
0
0
0
0
2
2
301
Instr[5-0]
Instr[25-0]
PC[31-28]
Instr[15-0]
Instr[3
1-2
6]
32
3
EP
C
8000 0180
CauseWrite
1
0
EPCWrite
IntrOrExcp
Trap
4
Ca
us
e
Sta
tus
CSE331 W13.40 Irwini Fall 2007 PSU
How Control Detects Two Traps Undefined instruction (RI) – detected when no next
state is defined in state 1 (decode) for the opcode value
Define the next state value for all undefined op values as new state 10
Arithmetic overflow (Ov) – The overflow signal from the ALU is used in state 6 (if don’t want to complete RegWrite)
Need to modify the FSM in a similar fashion for remaining traps
Challenge is to handle the interactions between instructions and exception-causing events so that the control logic remains small and fast
- Complex interactions makes the control unit the most challenging aspect of hardware design, especially in pipelined processors
CSE331 W13.42 Irwini Fall 2007 PSU
Trap Modified FSMIorD = 0
MemRead;IRWriteALUSrcA = 0ALUsrcB = 01ALUOp = 00
PCSource = 00PCWrite
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
ALUSrcA = 1ALUSrcB = 00ALUOp = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01
PCSource = 01PCWriteCond
PCSource = 10PCWrite
MemReadIorD = 1
MemWriteIorD = 1
RegDst = 1RegWrite
MemtoReg = 0
RegDst = 0RegWrite
MemtoReg = 1
Start
Instr Fetch Decode
Write Back
Memory Access
Execute
(Op = R-
type)
(Op =
beq)
(Op = lw or
sw) (Op = j)
(Op = lw)(Op = sw)
0 1
2
3
4
5
6
7
8 9
(Op = other)
Cause&StatusWriteALUSrcA =0ALUSrcB = 01ALUOp = 01
EPCWrite;PCWriteIntrOrExcp = 1PCSource = 11
Overflow
No Overflow
10
Interruptpending?
Cause&StatusWriteEPCWrite;PCWriteIntrOrExcp = 0PCSource = 11
11
CSE331 W13.44 Irwini Fall 2007 PSU
I/O System Interconnect Issues
Cache Memory
Memory - I/O Bus
MainMemory
I/OController
Disk Disk
I/OController
I/OController
Terminal Network
interrupt signals
Usually have more than one I/O device in the system connected to the processor via a bus
each I/O device is controlled by an I/O Controller
Processor
bus
CSE331 W13.45 Irwini Fall 2007 PSU
Buses A bus is a shared communication link (a single set
of wires used to connect multiple subsystems) that needs to support a range of devices with widely varying latencies and data transfer rates
Advantages- Versatile – new devices can be added easily and can be
moved between computer systems that use the same bus standard
- Low cost – a single set of wires is shared in multiple ways Disadvantages
- Creates a communication bottleneck – bus bandwidth limits the maximum I/O throughput
The maximum bus speed is largely limited by The length of the bus The number of devices on the bus
CSE331 W13.46 Irwini Fall 2007 PSU
I/O Performance Measures I/O bandwidth (throughput) – amount of information
that can be input (output) and communicated across an interconnect (e.g., a bus) to the processor/memory (I/O device) per unit time1. How much data can we move through the system in a
certain time?2. How many I/O operations can we do per unit time?
I/O response time (latency) – the total elapsed time to accomplish an input or output operation An especially important performance metric in real-time
systems
Many applications require both high throughput and short response times
CSE331 W13.47 Irwini Fall 2007 PSU
Types of Buses Processor-memory bus (proprietary)
Short and high speed Matched to the memory system to maximize the memory-
processor bandwidth Optimized for cache block transfers
Backplane bus (industry standard, e.g., ATA, PCIexpress)
The backplane is an interconnection structure within the chassis
Used as an intermediary bus connecting I/O busses to the processor-memory bus
I/O bus (industry standard, e.g., SCSI, USB, Firewire) Usually is lengthy and slower Needs to accommodate a wide range of I/O devices Connects to the processor-memory bus or backplane bus
CSE331 W13.48 Irwini Fall 2007 PSU
Example: The Pentium 4’s Buses
System Bus (“Front Side Bus”): 64b x 800 MHz (6.4GB/s), 533 MHz, or 400 MHz
2 serial ATAs:
150 MB/s
8 USBs: 60 MB/s
2 parallel ATA: 100 MB/s
Hub Bus: 8b x 266 MHz
Memory Controller Hub (“Northbridge”)
I/O Controller Hub (“Southbridge”)
Gbit ethernet: 0.266 GB/sDDR SDRAM
Main Memory
Graphics output: 2.0 GB/s
PCI: 32b x 33 MHz
CSE331 W13.49 Irwini Fall 2007 PSU
Bus Bandwidth Determinates The bandwidth of a bus is determined by
Whether its is synchronous or asynchronous and the timing characteristics of the protocol used
The bus width (i.e., number of data lines) Whether the bus supports block transfers or only
word at a time transfers
Firewire USB 2.0
Type I/O I/O
Data lines 4 2
Clocking Asynchronous Synchronous
Max # devices 63 127
Max length 4.5 meters 5 meters
Peak bandwidth 50 MB/s (400 Mbps)
100 MB/s (800 Mbps)
0.2 MB/s (low) 1.5 MB/s (full) 60 MB/s (high)
CSE331 W13.50 Irwini Fall 2007 PSU
Buses in Transition Companies are transitioning from synchronous,
parallel, wide buses to asynchronous narrow buses Reflection on wires and clock skew makes it difficult
to use 16 to 64 parallel wires running at a high clock rate (e.g., ~400 MHz) so companies are transitioning to buses with a few one-way wires running at a very high “clock” rate (~2 GHz)
PCI PCIexpress ATA Serial ATA
Total # wires 120 36 80 7
# data wires 32 – 64 (2-way)
2 x 4 (1-way)
16 (2-way)
2 x 2 (1-way)
Clock (MHz) 33 – 133 635 50 150
Peak BW (MB/s)
128 – 1064 300 100 375 (3 Gbps)
CSE331 W13.51 Irwini Fall 2007 PSU
ATA Cable Sizes
Serial ATA cables (red) are much thinner than parallel ATA cables (green)