CSET 4650 Field Programmable Logic Devices

CSET 4650 CSET 4650 Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Antifuse-Based FPGAs:Antifuse-Based FPGAs:ActelActel

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Antifuse FPGAsAntifuse FPGAs

One-time programmable devicesOne-time programmable devices

Primary vendorsPrimary vendorsActelActel

QuickLogicQuickLogic

No longer producing antifuse devicesNo longer producing antifuse devicesXilinxXilinx

CypressCypress

Focus on Actel todayFocus on Actel today

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New ArchitectureNew Architecture

Actel FPGAs have evolved Actel FPGAs have evolved from the channeled logic from the channeled logic array architecture (e.g., array architecture (e.g., used in ACT series) to the used in ACT series) to the “Sea-of-Modules” “Sea-of-Modules” architecturearchitecture

Made possible because Made possible because antifuses and wires can be antifuses and wires can be fabricated above the chip fabricated above the chip “floor” in the third “floor” in the third dimensiondimension

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Antifuse SwitchAntifuse Switch

Metal 3 (parallel to page)

Metal-to-Metal Antifuse

Metal 2 (into page)

Via

Metal 1

contact

Silicon

Antifuses are originally open circuits that take on low resistance only Antifuses are originally open circuits that take on low resistance only when programmed. when programmed.

Antifuses are manufactured using modified CMOS technology.Antifuses are manufactured using modified CMOS technology.

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Antifuse SwitchAntifuse Switch

Here is a three-dimensional Here is a three-dimensional representation of the same representation of the same type of routing resourcestype of routing resources

Some contacts shown are Some contacts shown are permanent, not switchedpermanent, not switched

Programmable antifuses are Programmable antifuses are shown in greenshown in green

Routing elements of this Routing elements of this type allow more density of type allow more density of logic elements in siliconlogic elements in silicon

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ONO Antifuse: ActelONO Antifuse: Actel

The figure below illustrates Actel’s PLICE (programmable The figure below illustrates Actel’s PLICE (programmable logic interconnect circuit element) antifuse structure.logic interconnect circuit element) antifuse structure.

The antifuse, positioned between two interconnect wires, The antifuse, positioned between two interconnect wires, consists of three sandwiched layers: consists of three sandwiched layers:

conductors at top and bottom conductors at top and bottom

an insulator in the middlean insulator in the middle

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ONO Antifuse: ActelONO Antifuse: Actel

Unprogrammed, the insulator isolates the top and bottom Unprogrammed, the insulator isolates the top and bottom layers; programmed, the insulator becomes a low-resistance layers; programmed, the insulator becomes a low-resistance link.link.PLICE uses polysilicon and n+ diffusion as conductors and a PLICE uses polysilicon and n+ diffusion as conductors and a custom-developed compound, ONO (oxide-nitride-oxide), as custom-developed compound, ONO (oxide-nitride-oxide), as an insulator. an insulator. Other antifuses rely on metal for conductors, with amorphous Other antifuses rely on metal for conductors, with amorphous silicon as the middle layer.silicon as the middle layer.

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ONO Antifuse: ActelONO Antifuse: ActelAn antifuse is the opposite of a fuse. An antifuse is the opposite of a fuse.

It is an open circuit until a current is forced through it (about 5 mA). It is an open circuit until a current is forced through it (about 5 mA). The current melts a thin insulating layer to form a thin permanent and The current melts a thin insulating layer to form a thin permanent and resistive link.resistive link.

(a) A cross section. (b) A simplified drawing. The ONO (oxide–nitride–oxide) dielectric is less than 10 nm thick, so this diagram is not to scale. (c) From above, an antifuse is approximately the same size as a contact.

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Antifuse AdvantagesAntifuse Advantages

Highest densityHighest densitya simple cross pointa simple cross point

10X the density of SRAM10X the density of SRAM

Lowest switch resistanceLowest switch resistance~25 Ohms~25 Ohms

Very low capacitanceVery low capacitance~1 fF per node~1 fF per node

approaching the metal line approaching the metal line capacitancecapacitance

non-volatilenon-volatile

Nearly impossible to Nearly impossible to reverse engineerreverse engineer

Radiation hardRadiation hard

Live within 1 millisecond Live within 1 millisecond of the power supply of the power supply reaching spec voltagereaching spec voltage

Software is easy to place Software is easy to place and routeand route

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Antifuse DisadvantagesAntifuse Disadvantages

Requires programmer Requires programmer

Requires a socketRequires a socketa problem for devices with a problem for devices with more than 200 pinsmore than 200 pins

Those who design by test Those who design by test will throw out a lot of parts will throw out a lot of parts

Requires one or two Requires one or two transistors per wire for transistors per wire for programming programming

ONO antifuses require only ONO antifuses require only about 5mA for programmingabout 5mA for programming

~ 10mA for Metal antifuses~ 10mA for Metal antifuses

Some antifuse defects not Some antifuse defects not testable until programmingtestable until programming

hence only 98% to 99 % hence only 98% to 99 % programming yieldprogramming yield

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FPGA Qualitative ComparisonFPGA Qualitative Comparison

SRAM Antifuse Flash EPROM

Speed Worst Best Worst Medium

Power Varies Near Best Best Worst

Density Medium Second Best Worst

Radiation Worst Best Medium Medium

Routing Cell size 1 1/10 1/7 PLD

Reprogrammable Yes No Yes Yes

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Actel’s Current Antifuse DevicesActel’s Current Antifuse Devices

Axcelerator Axcelerator High-speed antifuse FPGAs with gate densities of up to 2 million High-speed antifuse FPGAs with gate densities of up to 2 million equivalent gates equivalent gates

SX-A / SX SX-A / SX Antifuse devices 8k to 72k gates Antifuse devices 8k to 72k gates

eX eX Antifuse devices 3k to 12k gates Antifuse devices 3k to 12k gates

MX MX Antifuse devices 3k to 54k gatesAntifuse devices 3k to 54k gates

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Actel’s Legacy DevicesActel’s Legacy Devices

Integrator Series FPGAs: Integrator Series FPGAs: 1200XL and 3200DX Families v3.01200XL and 3200DX Families v3.0

Accelerator Series FPGAs Accelerator Series FPGAs ACT 3 Family (-3 speed grade only)ACT 3 Family (-3 speed grade only)

ACT 2 Family FPGAs v4.0.1ACT 2 Family FPGAs v4.0.1

ACT 1 Series FPGAsACT 1 Series FPGAs

Devices being phased out or already discontinued.

Speed GradeStd = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard –P = Approximately 30% faster than Standard –F = Approximately 40% slower than Standard

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Actel MX FamilyActel MX Family

low power consumptionlow power consumption

5.0V, 3.3V and mixed voltage systems compatible 5.0V, 3.3V and mixed voltage systems compatible

design securitydesign security

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Naming conventionNaming convention

Six devices in the MX Six devices in the MX family, vary in number family, vary in number of equivalent gatesof equivalent gates

Five speed gradesFive speed grades

A variety of package A variety of package options and operating options and operating temperature rangestemperature ranges

Same convention used Same convention used for all Actel FPGAsfor all Actel FPGAs

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MX 40M and 42M devicesMX 40M and 42M devices

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40MX Logic Module

Same as ACT 1 logic element

eight-input, one-output logic circuit (702 possibilities)

can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of two, three, or four inputs

can also implement a variety of D latches, exclusivity functions, AND-ORs and OR-ANDs

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42MX C-Module Implementation

42MX devices contain three types of logic modules:

combinatorial (C-modules)sequential (S-modules)decode (D-modules)

figure at right illustrates the combinatorial logic module766 possibilities

Actel’s name for combinational logic

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42MX S-Module Implementation

S-module implements the same S-module implements the same combinatorial logic function as the combinatorial logic function as the C-module while adding a sequential C-module while adding a sequential element. element.

Sequential element can be Sequential element can be configured as either a D-flip-flop or configured as either a D-flip-flop or a transparent latch. a transparent latch.

S-module register can be bypassed S-module register can be bypassed so that it implements purely so that it implements purely combinatorial (combinational) logic combinatorial (combinational) logic functions.functions.

S-Module

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42MX S-Module Implementation

A closer look at the S-Module configurationsA closer look at the S-Module configurations

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A42MX24 and A42MX36 D-ModuleImplementation

D-modules are arranged around the periphery of the device.

D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that found in CPLD architectures

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A42MX36 Dual-Port SRAM Block

The SRAM modules are The SRAM modules are arranged in 256-bit blocks arranged in 256-bit blocks that can be configured as that can be configured as 32x8 or 64x4. 32x8 or 64x4.

SRAM modules can be SRAM modules can be cascaded together to form cascaded together to form memory spaces of user-memory spaces of user-definable width and depth.definable width and depth.

A42MX36 SRAM modules A42MX36 SRAM modules contain independent read contain independent read and write ports.and write ports.

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From Before: Actel’s ACT SeriesFrom Before: Actel’s ACT Series

Based on channeled gate array architecture

Segmented routing tracksSegmented routing tracks

Interconnect and logic elements in same plane

Each logic element (labelled ‘L’) is a combination of multiplexers which can be configured as a multi-input gate

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MX Routing StructureMX Routing StructureMX architecture uses vertical and MX architecture uses vertical and horizontal routing tracks to horizontal routing tracks to interconnect the logic and I/O interconnect the logic and I/O modules.modules.Routing tracks are metal Routing tracks are metal interconnects that may be continuous interconnects that may be continuous or split into segments. or split into segments. Varying segment lengths allow the Varying segment lengths allow the interconnect of over 90% of design interconnect of over 90% of design tracks only two antifuse connections.tracks only two antifuse connections.Segments can be joined together at Segments can be joined together at the ends using antifuses to increase the ends using antifuses to increase their lengths up to the full length of their lengths up to the full length of the track.the track.All interconnects can be All interconnects can be accomplished with a maximum of accomplished with a maximum of four antifuses.four antifuses.

Actel’s Channeled RoutingActel’s Channeled Routing

L L L L L L L L

L L L L L L L L

L L L L L L L L

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Horizontal RoutingHorizontal Routing

Horizontal routing tracks span the whole row length Horizontal routing tracks span the whole row length or are divided into multiple segments and are located or are divided into multiple segments and are located in between the rows of modules. in between the rows of modules. Any segment that spans more than one-third of the Any segment that spans more than one-third of the row length is considered a long horizontal segment. row length is considered a long horizontal segment. Within horizontal routing, dedicated routing tracks Within horizontal routing, dedicated routing tracks are used for global clock networks and for power are used for global clock networks and for power and ground tie-off tracks. and ground tie-off tracks. Non-dedicated tracks are used for signal nets.Non-dedicated tracks are used for signal nets.

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Vertical RoutingVertical Routing

Another set of routing tracks run vertically. Another set of routing tracks run vertically.

There are three types of vertical tracks: There are three types of vertical tracks: input, output, and long input, output, and long

Long tracks span the column length of the module, Long tracks span the column length of the module, and can be divided into multiple segmentsand can be divided into multiple segments

Each segment in an input track is dedicated to the Each segment in an input track is dedicated to the input of a particular moduleinput of a particular module

Each segment in an output track is dedicated to the Each segment in an output track is dedicated to the output of a particular module output of a particular module

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Vertical Routing (continued)Vertical Routing (continued)

Long segments are uncommitted and can be Long segments are uncommitted and can be assigned during routing assigned during routing

Each output segment spans four channels Each output segment spans four channels two above and two below the logic moduletwo above and two below the logic module

except near the top and bottom of the array, where edge except near the top and bottom of the array, where edge effects occureffects occur

Long vertical tracks contain either one or two Long vertical tracks contain either one or two segmentssegments

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Antifuse StructuresAntifuse Structures

An antifuse is a "normally open" structureAn antifuse is a "normally open" structurethe opposite of a “normally closed” fuse the opposite of a “normally closed” fuse

The use of antifuses to implement a programmable The use of antifuses to implement a programmable logic device results in logic device results in

highly testable structureshighly testable structures

efficient programming algorithmsefficient programming algorithms

There are no pre-existing connectionsThere are no pre-existing connectionstemporary connections can be made using pass transistorstemporary connections can be made using pass transistors

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Antifuse Structures (continued)Antifuse Structures (continued)

These temporary connections can isolateThese temporary connections can isolateindividual antifuses to be programmedindividual antifuses to be programmed

individual circuit structures to be testedindividual circuit structures to be testedcan be done before and after programming can be done before and after programming

For example For example all metal tracks can be tested for continuity and shorts all metal tracks can be tested for continuity and shorts between adjacent tracksbetween adjacent tracks

the functionality of all logic modules can be verifiedthe functionality of all logic modules can be verified

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From Before: Actel ACT Series I/O LogicFrom Before: Actel ACT Series I/O Logic

Simple tristate buffersSimple tristate buffers

Allowed pins to be used as Allowed pins to be used as an input or an output, or an input or an output, or bothboth

ACT 1 I/O ModuleACT 1 I/O Module



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42MX devices feature Multiplex I/Os and support 5.0V, 3.3V, and mixed 3.3V/5.0V operationsprovide the interface between the device pins and the logic arraymodules contain tristate buffers, with input and output latches that can be configured for input, output, or bidirectional operation. 42MX I/O Module42MX I/O Module

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A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with version 2.1 of the PCI specification

chip-wide PCI fuse

When the PCI fuse is not programmed, the output drive is standard. PCI Output Structure of

A42MX24 andA42MX36 Devices

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Actel eX FamilyActel eX Family

Low power consumption Low power consumption Extremely small chip-scale Extremely small chip-scale packages packages Design security Design security Nonvolatile single chip Nonvolatile single chip Up to 100% resource Up to 100% resource utilization with 100% pin utilization with 100% pin locking locking 2.5V, 3.3V, and 5.0V 2.5V, 3.3V, and 5.0V Mixed Voltage Operation Mixed Voltage Operation with 5.0V Input Tolerance with 5.0V Input Tolerance and 5.0V Drive Strengthand 5.0V Drive Strength

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eX naming conventioneX naming conventionthree devices in the eX three devices in the eX family, vary in number family, vary in number of equivalent gates and of equivalent gates and flip-flopsflip-flopsthree speed gradesthree speed gradesa variety of package a variety of package options and operating options and operating temperature rangestemperature rangessame convention used same convention used for all Actel FPGAsfor all Actel FPGAs

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Device selectionDevice selection

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The eX family architecture uses a “sea-of-modules” structure where the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing.Interconnection among these logic modules is achieved using metal-to-metal programmable antifuse interconnect elements.

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eX family provides two types of logic modules

the register cell (R-Cell)

the combinatorial (combinational) cell (C-Cell)

C-Cell is shown at rightC-Cell is shown at rightsimilar to ACT logic cell of the similar to ACT logic cell of the same namesame name

inverter input (DB) addedinverter input (DB) added

allows ~4000 possible allows ~4000 possible combinational functions to be combinational functions to be implementedimplemented

C-Cell

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eX R-CelleX R-CellThe R-Cell contains a flip-flop The R-Cell contains a flip-flop featuring asynchronous clear, featuring asynchronous clear, asynchronous preset, and clock enable asynchronous preset, and clock enable (using the S0 and S1 lines) control (using the S0 and S1 lines) control signals. signals. The R-Cell registers feature The R-Cell registers feature programmable clock polarity programmable clock polarity selectable on a register-by-register selectable on a register-by-register basis. basis. This provides additional flexibility This provides additional flexibility while allowing mapping of while allowing mapping of synthesized functions into the eX synthesized functions into the eX FPGA. FPGA. The clock source for the R-Cell can be The clock source for the R-Cell can be chosen from either the hard-wired chosen from either the hard-wired clock or the routed clock.clock or the routed clock. R-Cell

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C-cell and R-cell logic modules are arranged into horizontal banks C-cell and R-cell logic modules are arranged into horizontal banks called Clusters, each of which contains two C-cells and one R-cell in a called Clusters, each of which contains two C-cells and one R-cell in a C-R-C configuration.C-R-C configuration.

Cluster Organization

Clusters are further Clusters are further organized into organized into modules called modules called SuperClusters. SuperClusters. Each SuperCluster Each SuperCluster is a two-wide is a two-wide grouping of grouping of Clusters.Clusters.

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Actel eX Family: Actel eX Family: Routing Resources

Clusters and SuperClusters can be connected through the use of two Clusters and SuperClusters can be connected through the use of two local routing resources called FastConnect and DirectConnect.local routing resources called FastConnect and DirectConnect.

DirectConnect and FastConnect for SuperClusters

This routing architecture This routing architecture reduces the number of reduces the number of antifuses required to antifuses required to complete a circuit.complete a circuit.

DirectConnect is a DirectConnect is a horizontal routing horizontal routing resource that provides resource that provides connections from a C-cell connections from a C-cell to its neighboring Rcell in to its neighboring Rcell in a given SuperCluster. a given SuperCluster.

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Actel eX Family: Actel eX Family: Routing Resources

DirectConnect uses a hardwired signal path DirectConnect uses a hardwired signal path requiring no programmable interconnection.requiring no programmable interconnection.

FastConnect enables horizontal routing between any FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately vertical routing with the SuperCluster immediately below it. below it.

Only one programmable connection is used in a Only one programmable connection is used in a FastConnect path.FastConnect path.

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eX devices have a variety of I/O features, such as PCI compliance, programmable input threshold voltage, configurable output slew rate, and selectable output state during power-up support for both hot-swapping and cold-sparingmixed I/O standards can be set for individual pins

only allowed with standards that use the same supply voltage

Simplified I/O Circuitry

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Each I/O on an eX device can be configured as an input, an output, a tristate output, or a bidirectional pin

I/O cells in eX devices do not contain embedded latches or flip-flops and can be inferred directly from HDL code.

I/O Features

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Actel SX-A and SX FamilyActel SX-A and SX Family12,000 to 108,000 usable system gates 12,000 to 108,000 usable system gates 3.7ns clock-to-output (pin-to-pin) 3.7ns clock-to-output (pin-to-pin) 350MHz internal clock frequency 350MHz internal clock frequency 66MHz, 64-bit 3.3V/5.0V PCI 66MHz, 64-bit 3.3V/5.0V PCI performanceperformanceHot swappable I/Os (SX-A) Hot swappable I/Os (SX-A) Able to run at OC3 to OC192 data Able to run at OC3 to OC192 data rates rates 2.5V, 3.3V, and 5.0V mixed voltage 2.5V, 3.3V, and 5.0V mixed voltage support support 100% resource utilization with 100% 100% resource utilization with 100% pin locking pin locking Low power consumption (less than 1W Low power consumption (less than 1W @ 200MHz) @ 200MHz) Complete BST/JTAG supportComplete BST/JTAG support

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Actel SX-A and SX FamilyActel SX-A and SX Family

54SX Family 54SX Family FPGAsFPGAs

available in four available in four speed gradesspeed grades

six package optionssix package options

four component four component densitiesdensities

four operating four operating temperature rangestemperature ranges

54SX32A

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As with the eX Family, the SX-A and SX Families use As with the eX Family, the SX-A and SX Families use Actel’s “Sea of Modules” architectureActel’s “Sea of Modules” architecture

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the C-cell implements a range of combinatorial functions up to 5-inputs inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture

C-Cell

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the R-cell contains a flip-flop featuring

asynchronous clear

asynchronous preset

clock enable (using the S0 and S1 lines) control signals

the R-cell registers feature programmable clock polarity selectable on a register-by-register basis.

R-Cell

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C-cell and R-cell logic modules are arranged in horizontal banks called Clusters

two types of Clusters: Type 1 contains two C-cells and one R-cell

Type 2 contains one C-cell and two R-cells

SuperCluster 1 is a two-wide grouping of Type 1 clusters.

SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster

Cluster OrganizationCluster Organization

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Clusters and SuperClusters can be Clusters and SuperClusters can be connected through the use of two connected through the use of two local routing resources called local routing resources called FastConnect and DirectConnectFastConnect and DirectConnect

This routing architecture reduces the This routing architecture reduces the number of antifuses required to number of antifuses required to complete a circuitcomplete a circuit

DirectConnect is a horizontal routing DirectConnect is a horizontal routing resource that provides connections resource that provides connections from a C-cell to its neighboring R-from a C-cell to its neighboring R-cell in a given SuperClustercell in a given SuperCluster DirectConnect and FastConnect DirectConnect and FastConnect

for Type 1 SuperClustersfor Type 1 SuperClusters

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Actel SX-A and SX FamilyActel SX-A and SX FamilyDirectConnect uses a hard-DirectConnect uses a hard-wired signal path requiring no wired signal path requiring no programmable programmable interconnection to achieve its interconnection to achieve its fast signal propagation time of fast signal propagation time of less than 0.1 nsless than 0.1 nsFastConnect enables FastConnect enables horizontal routing between horizontal routing between any two logic modules in a any two logic modules in a given SuperCluster and given SuperCluster and vertical routing with the vertical routing with the SuperCluster immediately SuperCluster immediately below itbelow itOnly one programmable Only one programmable connection is used in a connection is used in a FastConnect path, delivering FastConnect path, delivering maximum pin-to-pin maximum pin-to-pin propagation of 0.4 nspropagation of 0.4 ns

DirectConnect and FastConnect DirectConnect and FastConnect for Type 2 SuperClustersfor Type 2 SuperClusters

0.4 ns

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Each I/O module on an SX device can be configured asEach I/O module on an SX device can be configured asan inputan input

an outputan output

a tristate outputa tristate output

a bidirectional pin a bidirectional pin

Even without the inclusion of dedicated I/O registers, these I/O Even without the inclusion of dedicated I/O registers, these I/O modules, in combination with array registers, can achieve modules, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns. clock-to-out (pad-to-pad) timing as fast as 3.7 ns.

I/O cells that have embedded latches and flip-flops require I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not instantiation in HDL code; this is a design complication not encountered in SX FPGAs.encountered in SX FPGAs.

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the SX family locates the routing interconnect resources between the Metal 2 and Metal 3 layersthis eliminates the channels of routing and interconnect resources between logic modulesmetal-to-metal programmable antifuse interconnect elements, which are embedded between the M2 and M3 layers

SX Family Interconnect Elements

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SX-A interconnect resources SX-A interconnect resources are located between the top are located between the top two metal layerstwo metal layers

A54SX72A has four layers of A54SX72A has four layers of metal with the antifuse metal with the antifuse between Metal 3 and Metal 4between Metal 3 and Metal 4

A54SX08A, A54SX16A and A54SX08A, A54SX16A and A54SX32A have three layers A54SX32A have three layers of metal with antifuse of metal with antifuse between Metal 2 and Metal 3between Metal 2 and Metal 3

Same as SX Same as SX SX-A Family Interconnect Elements

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CSET 4650 Field Programmable Logic Devices

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