CHONG-FATT LAW 85 TAMPINES AVENUE 1 #04-28 SINGAPORE 528687 [email protected]+65 9773 1523 SUMMARY Academic qualifications – PhD, MEng (by research) and BEng (First-Class Honors) 15 years of research and design experience in digital ICs Successful completion of 7 industrial SoC projects and more than 10 IPs Excellent knowledge of and experience in all digital IC design abstraction levels – RTL, gate level and transistor level Good knowledge of and experience in the digital IC design flow, particularly from design specification to RTL synthesis, including timing and power analyses Strong scripting and programming skills (Perl, C shell and C) 4 years of foundry design enablement experience, particularly in parasitic extraction (PEX) technology file development, including script and flow development to automate PEX technology file development and qualification 6 years of experience in layout-vs-schematic (LVS) tools, including Mentor Calibre LVS and Cadence PVS Proven track record of innovativeness, with 9 international peer-reviewed publications
15 years of research and design experience in digital ICs
Successful completion of 7 industrial SoC projects and more than 10 IPs
Excellent knowledge of and experience in all digital IC design abstraction levels – RTL, gate level and transistor level
Good knowledge of and experience in the digital IC design flow, particularly from design specification to RTL synthesis, including timing and power analyses
Strong scripting and programming skills (Perl, C shell and C)
4 years of foundry design enablement experience, particularly in parasitic extraction (PEX) technology file development, including script and flow development to automate PEX technology file development and qualification
6 years of experience in layout-vs-schematic (LVS) tools, including Mentor Calibre LVS and Cadence PVS
Proven track record of innovativeness, with 9 international peer-reviewed publications
ACADEMIC QUALIFICATIONS
Doctor of Philosophy School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Dissertation: Design methodologies for low-power, asynchronous-logic digital systems
Master of Engineering (Research-Based) School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Dissertation: Basic logic circuits and arithmetic subsystems for low-power applications
Bachelor of Engineering (First-Class Honors) School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Major: Electronics
32-Bit AVR Microcontrollers (UC3L picoPower and maXTouch series) Chip-level design, integration and verification (RTL, gate level and analog/digital
co-simulation) of 32-bit AVR microcontrollers Implementation and verification of AMBA AHB and APB Enhancement, maintenance and silicon validation of existing IPs
DMA controller
I2C-bus controller (up to high-speed mode)
USART
SPI
Interfaces for analog modules (ADC and analog comparator)
Capacitive Touch Engine (CTE) Specification, design and verification of CTE for touch screen applications Analog/digital co-simulation of CTE with analog modules (sample-and-holds,
integrators and ADCs) Integration of CTE on 32-bit AVR microcontrollers
Advanced Encryption Standard (AES) Cipher and Inverse Cipher Specification, design, verification, logic synthesis, timing analysis, power analysis
and optimization of a low-power AES cipher and inverse cipher Integration of AES cipher and inverse cipher on 32-bit AVR microcontrollers
Input/Output Buffer Information Specification (IBIS) Flow Development and maintenance of automated flow and scripts for generating IBIS
models
MSc Project Supervision Supervision and mentoring of MSc students on internship Completed projects include
A self-timed microprocessor for timing-robust aggressive dynamic voltage scaling
Implementation of an Asynchronous Advanced Encryption Standard Module
Implementing the new ADA 2005 timing event and execution time control features on the AVR32 architecture
IC DESIGN EXPERIENCE
Research Associate School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Aug 2006–Mar 2008
transistor-level simulation and power analysis of digital peripheral IPs
UART
Clock divider
ADC interface Top-level integration, verification, timing analysis, transistor-level simulation and
power analysis
WCDMA Mobile Station Channel Modem Top-level integration, verification and timing analysis of the forward- and reverse-
link datapaths Design, verification, timing analysis, optimization, transistor-level simulation and
power analysis of a compact low-power Viterbi decoder for the forward-link implementation
Back-end design, from synthesis to place-and-route, of the entire system
Integrated Development Environments (IDEs) Specification, design, implementation and testing of IDEs for embedded software
development on aforementioned ICs Design of the interface controller (FPGA implementation) on the IDE boards
FOUNDRY DESIGN ENABLEMENT EXPERIENCE
Senior Member of Technical Staff Mainstream PDK, Design Enablement GLOBALFOUNDRIES Apr 2011–Present
Parasitic Extraction (PEX) Technology File Development Development of PEX technology files for the following process nodes and PEX
tools
28 nm, 40 nm, 55 nm and 65 nm
Synopsys StarRC and Quickcap
Mentor Calibre xRC
Cadence QRC Development of automated flows and scripts for developing and qualifying PEX
technology files; notable contributions include
Generation of process files (StarRC ITF, xRC MIPT, QRC ICT and Quickcap) by parsing process assumptions to extract relevant process parameters
Generation of in-die variation data by parsing process assumptions to extract relevant process parameters and formulas.
Translation of Calibre-to-StarRC mapping files into corresponding xRC and QRC mapping files, thereby ensuring alignment of layer mapping and device parasitic extraction across all technology files of supported tools
Qualification of device parasitic extraction, thereby ensuring a tight boundary between Spice modeling of device parasitic and extraction of device parasitic by extraction tools
Computation of scaling factors for generating 3-Sigma process corner technology files
Alignment of PEX technology files to silicon Electrical Testing (ET) measurements
Collaboration with Process Integration team to ensure good alignment between PEX results and silicon measurements
Technical Leadership Training and mentoring of junior PEX developers Project assignment and supervision
Technical Support Provision of technical support to application engineers and customers to resolve
parasitic extraction issues
EDA TOOL EXPERIENCE
Transistor Level Simulation
Synopsys HSPICE and NanoSim Cadence Virtuoso
Parasitic Extraction Synopsys StarRC, Quickcap and Rapid3D Mentor Calibre xRC and xACT3D Cadence QRC and QRC Field Solver
FPGA Prototyping Altera Quartus II Xilinx ISE Foundation Synopsys Design Compiler
SCRIPTING AND PROGRAMMING SKILLS
Scripting Perl
Tcl
C shell
Programming C/C++
Microsoft Visual Studio
Assembly coding
MATLAB
RESEARCH ACHIEVEMENTS
PhD Candidate School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Jul 2003–Mar 2008
Modeling and Synthesis of Low-Power Asynchronous VLSI Systems Proposal and development of a set of modeling rules and a synthesis method
(based on Verilog HDL) for the design of low-power asynchronous VLSI systems Salient features of the proposed approach include
Low asynchronous control overheads (in terms of circuit area and power dissipation)
Support for largely-transparent asynchronous communication modelling
Easy integration with conventional synchronous VLSI design flow Published in IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
Optimization of Asynchronous Control Networks Proposal and development of two optimization methods for reducing the power
dissipation and circuit areas of asynchronous control networks Optimal Decoupling
Uses a branch-and-bound algorithm to search for the optimum mix of handshake components of different degree of concurrency
The solution provides the best throughput for the design while minimizing asynchronous control overheads
Handshake Component Fusion
A clustering technique that iteratively fuses two handshake components that share input channel sources or output channel destinations into a single component
The fusion preserves the behavior and satisfies the throughput constraint of the design
Published in IEEE Trans. Computer-Aided Design Integr. Circuits Syst.
Fast Timing Analysis of Asynchronous VLSI Systems Proposal and development of a fast and memory-efficient implementation of the
Fourier-Motzkin algorithm for computing all S-invariants of ordinary Petri nets Proposed algorithm supports fast and memory-efficient timing analysis of
asynchronous VLSI systems Published in IET Proc. Computers and Digital Techniques
Design and EDA Tool Flow for Asynchronous VLSI Design Integration of the proposed methods and algorithms for asynchronous VLSI design
into the conventional synchronous VLSI design flow
RESEARCH ACHIEVEMENTS
MEng Candidate School of Electrical and Electronic Engineering Nanyang Technological University (Singapore) Jul 1997–Dec 1998
Low-Power Partial-Product Adder and Multiplier Proposal, design and fabrication of a 16 x 16-bit parallel multiplier utilizing a low-
power partial-product adder Low power dissipation is achieved using pass-transistor logic and reduced voltage
swing design techniques Published in IEEE J. Solid-State Circuits and IET Proc. Circuits, Devices and Systems
Redundant-Binary Partial-Product Generator Proposal and design of a redundant-binary partial-product generator based on a
five-bit recoding technique Salient features of the proposed circuit include
Requires no extra adders to produce the non-power-of-two multiples of the multiplicand
Generates only half the number of partial products generated by the conventional modified Booth’s algorithm
Published in Int. J. Electronics
High-Speed Low-Power Basic Logic Circuits Proposal and design of basic logic circuits based on bootstrapping and BiCMOS
techniques Published in IET Electronics Letters (two articles)
INTERNATIONAL PEER-REVIEWED PUBLICATIONS
Regular Papers C. F. Law, B. H. Gwee and J. S. Chang, “Modeling and synthesis of asynchronous
pipelines,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 682–695, Mar. 2010
C. F. Law, B. H. Gwee and J. S. Chang, “Asynchronous control network optimization using fast minimum cycle time analysis,” IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 27, no. 6, pp. 985–998, June 2008
C. F. Law, B. H. Gwee and J. S. Chang, “Fast and memory-efficient invariant computation of ordinary Petri nets,” IET Proc. Computers and Digital Techniques, vol. 1, no. 5, pp. 612–624, Sept. 2007
C. F. Law, K. S. Yeo and S. S. Rofail, “A low-power 16 x 16-b parallel multiplier utilizing pass-transistor logic”, IEEE J. Solid-State Circuits, vol. 34, no. 10, pp. 1395–1399, Oct. 1999
C. F. Law, K. S. Yeo and S. S. Rofail, “Low-power circuit implementation for partial- product addition using pass-transistor logic”, IET Proc. Circuits, Devices and Systems, vol. 146, no. 3, pp. 124–129, June 1999
C. F. Law, K. S. Yeo and S. S. Rofail, “A redundant-binary partial-product generator based on a five-bit recoding technique”, Int. J. Electronics, vol. 87, no. 4, pp. 413–423, Apr. 2000.
Brief Papers C. F. Law, K. S. Yeo and S. S. Rofail, “A sub-1 V bootstrapped CMOS driver for the giga-
scale-integration era”, Electronics Letters, vol. 35, no. 5, pp. 392–394, Mar. 1999
C. F. Law, K. S. Yeo and S. S. Rofail, “BiCMOS logic circuit for single-battery operation”, Electronics Letters, vol. 34, no. 21, pp. 2013–2015, Oct. 1998
Conference Papers C. F. Law, B. H. Gwee and J. S. Chang, “Optimized algorithm for computing invariants
of ordinary Petri nets”, in Proc. Int. Conf. Computer and Information Science, July 2006, pp. 23–28
SCHOLARSHIPS AND AWARDS
Singapore Millenium Foundation Doctoral Scholarship Jul 2003–Jun 2006 National Science and Technology Board Postgraduate Scholarship Jul 1997–Dec 1998
